rbus_ppb.c revision 1.43 1 1.43 uebayasi /* $NetBSD: rbus_ppb.c,v 1.43 2014/10/17 20:52:00 uebayasi Exp $ */
2 1.1 mcr
3 1.1 mcr /*
4 1.1 mcr * Copyright (c) 1999 The NetBSD Foundation, Inc.
5 1.1 mcr * All rights reserved.
6 1.1 mcr *
7 1.1 mcr * This code is derived from software contributed to The NetBSD Foundation
8 1.1 mcr * by Michael Richardson <mcr (at) sandelman.ottawa.on.ca>
9 1.1 mcr *
10 1.1 mcr * Redistribution and use in source and binary forms, with or without
11 1.1 mcr * modification, are permitted provided that the following conditions
12 1.1 mcr * are met:
13 1.1 mcr * 1. Redistributions of source code must retain the above copyright
14 1.1 mcr * notice, this list of conditions and the following disclaimer.
15 1.1 mcr * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 mcr * notice, this list of conditions and the following disclaimer in the
17 1.1 mcr * documentation and/or other materials provided with the distribution.
18 1.1 mcr *
19 1.1 mcr * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 1.1 mcr * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 1.1 mcr * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 1.1 mcr * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 1.1 mcr * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 1.1 mcr * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 1.1 mcr * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 1.1 mcr * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 1.1 mcr * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 1.1 mcr * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 1.1 mcr * POSSIBILITY OF SUCH DAMAGE.
30 1.1 mcr */
31 1.1 mcr
32 1.1 mcr /*
33 1.1 mcr * CardBus front-end for the Intel/Digital DECchip 21152 PCI-PCI bridge
34 1.1 mcr */
35 1.2 lukem
36 1.2 lukem #include <sys/cdefs.h>
37 1.43 uebayasi __KERNEL_RCSID(0, "$NetBSD: rbus_ppb.c,v 1.43 2014/10/17 20:52:00 uebayasi Exp $");
38 1.1 mcr
39 1.1 mcr #include <sys/param.h>
40 1.1 mcr #include <sys/systm.h>
41 1.1 mcr #include <sys/mbuf.h>
42 1.1 mcr #include <sys/malloc.h>
43 1.1 mcr #include <sys/kernel.h>
44 1.1 mcr #include <sys/socket.h>
45 1.1 mcr #include <sys/ioctl.h>
46 1.1 mcr #include <sys/errno.h>
47 1.1 mcr #include <sys/device.h>
48 1.38 dyoung #include <sys/kmem.h>
49 1.1 mcr
50 1.1 mcr #include <sys/rnd.h>
51 1.1 mcr
52 1.1 mcr #include <machine/endian.h>
53 1.1 mcr
54 1.20 ad #include <sys/bus.h>
55 1.20 ad #include <sys/intr.h>
56 1.1 mcr
57 1.1 mcr #include <dev/pci/pcivar.h>
58 1.1 mcr #include <dev/pci/pcireg.h>
59 1.1 mcr #include <dev/pci/pcidevs.h>
60 1.1 mcr #include <dev/pci/ppbreg.h>
61 1.1 mcr
62 1.1 mcr #include <dev/ic/i82365reg.h>
63 1.1 mcr
64 1.41 drochner #include <dev/cardbus/rbus.h>
65 1.1 mcr #include <dev/pci/pccbbreg.h>
66 1.1 mcr #include <dev/pci/pccbbvar.h>
67 1.1 mcr
68 1.1 mcr #include <dev/cardbus/cardbusvar.h>
69 1.12 mycroft #include <dev/pci/pcidevs.h>
70 1.1 mcr
71 1.23 jmcneill #include <x86/pci/pci_addr_fixup.h>
72 1.23 jmcneill #include <x86/pci/pci_bus_fixup.h>
73 1.1 mcr #include <i386/pci/pci_intr_fixup.h>
74 1.1 mcr #include <i386/pci/pcibios.h>
75 1.1 mcr
76 1.1 mcr struct ppb_softc;
77 1.1 mcr
78 1.31 cegger static int ppb_cardbus_match(device_t, cfdata_t, void *);
79 1.31 cegger static void ppb_cardbus_attach(device_t, device_t, void *);
80 1.31 cegger static int ppb_activate(device_t, enum devact);
81 1.16 drochner int rppbprint(void *, const char *);
82 1.16 drochner int rbus_intr_fixup(pci_chipset_tag_t, int, int, int);
83 1.16 drochner void rbus_do_header_fixup(pci_chipset_tag_t, pcitag_t, void *);
84 1.1 mcr
85 1.16 drochner static void rbus_pci_phys_allocate(pci_chipset_tag_t, pcitag_t, void *);
86 1.16 drochner
87 1.16 drochner static int rbus_do_phys_allocate(pci_chipset_tag_t, pcitag_t, int,
88 1.16 drochner void *, int, bus_addr_t *, bus_size_t);
89 1.16 drochner
90 1.16 drochner static void rbus_pci_phys_countspace(pci_chipset_tag_t, pcitag_t, void *);
91 1.16 drochner
92 1.16 drochner static int rbus_do_phys_countspace(pci_chipset_tag_t, pcitag_t, int,
93 1.16 drochner void *, int, bus_addr_t *, bus_size_t);
94 1.16 drochner
95 1.16 drochner unsigned int rbus_round_up(unsigned int, unsigned int);
96 1.1 mcr
97 1.1 mcr
98 1.1 mcr struct ppb_cardbus_softc {
99 1.25 joerg device_t sc_dev;
100 1.3 thorpej pcitag_t sc_tag;
101 1.1 mcr int foo;
102 1.1 mcr };
103 1.1 mcr
104 1.25 joerg CFATTACH_DECL_NEW(rbus_ppb, sizeof(struct ppb_cardbus_softc),
105 1.39 dyoung ppb_cardbus_match, ppb_cardbus_attach, NULL, ppb_activate);
106 1.1 mcr
107 1.1 mcr #ifdef CBB_DEBUG
108 1.1 mcr int rbus_ppb_debug = 0; /* hack with kdb */
109 1.1 mcr #define DPRINTF(X) if(rbus_ppb_debug) printf X
110 1.1 mcr #else
111 1.1 mcr #define DPRINTF(X)
112 1.1 mcr #endif
113 1.1 mcr
114 1.1 mcr static int
115 1.31 cegger ppb_cardbus_match(device_t parent, cfdata_t match, void *aux)
116 1.1 mcr {
117 1.1 mcr struct cardbus_attach_args *ca = aux;
118 1.1 mcr
119 1.35 dyoung if (PCI_VENDOR(ca->ca_id) == PCI_VENDOR_DEC &&
120 1.35 dyoung PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_DEC_21152)
121 1.1 mcr return (1);
122 1.1 mcr
123 1.1 mcr if(PCI_CLASS(ca->ca_class) == PCI_CLASS_BRIDGE &&
124 1.1 mcr PCI_SUBCLASS(ca->ca_class) == PCI_SUBCLASS_BRIDGE_PCI) {
125 1.1 mcr /* XXX */
126 1.1 mcr printf("recognizing generic bridge chip\n");
127 1.1 mcr }
128 1.1 mcr
129 1.1 mcr return (0);
130 1.1 mcr }
131 1.1 mcr
132 1.1 mcr
133 1.1 mcr int
134 1.27 dsl rppbprint(void *aux, const char *pnp)
135 1.1 mcr {
136 1.1 mcr struct pcibus_attach_args *pba = aux;
137 1.1 mcr
138 1.1 mcr /* only PCIs can attach to PPBs; easy. */
139 1.1 mcr if (pnp)
140 1.9 thorpej aprint_normal("pci at %s", pnp);
141 1.9 thorpej aprint_normal(" bus %d (rbus)", pba->pba_bus);
142 1.1 mcr return (UNCONF);
143 1.1 mcr }
144 1.1 mcr
145 1.1 mcr int
146 1.1 mcr rbus_intr_fixup(pci_chipset_tag_t pc,
147 1.1 mcr int minbus,
148 1.1 mcr int maxbus,
149 1.1 mcr int line)
150 1.1 mcr {
151 1.1 mcr pci_device_foreach_min(pc, minbus,
152 1.1 mcr maxbus, rbus_do_header_fixup, (void *)&line);
153 1.1 mcr return 0;
154 1.1 mcr }
155 1.1 mcr
156 1.1 mcr void
157 1.27 dsl rbus_do_header_fixup(pci_chipset_tag_t pc, pcitag_t tag, void *context)
158 1.1 mcr {
159 1.1 mcr int bus, device, function;
160 1.43 uebayasi pcireg_t intr;
161 1.1 mcr int *pline = (int *)context;
162 1.1 mcr int line = *pline;
163 1.1 mcr
164 1.1 mcr pci_decompose_tag(pc, tag, &bus, &device, &function);
165 1.1 mcr
166 1.1 mcr intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);
167 1.1 mcr
168 1.1 mcr intr &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT);
169 1.1 mcr intr |= (line << PCI_INTERRUPT_LINE_SHIFT);
170 1.1 mcr pci_conf_write(pc, tag, PCI_INTERRUPT_REG, intr);
171 1.1 mcr
172 1.1 mcr }
173 1.1 mcr
174 1.15 perry /*
175 1.1 mcr * This function takes a range of PCI bus numbers and
176 1.1 mcr * allocates space for all devices found in this space (the BARs) from
177 1.1 mcr * the rbus space maps (I/O and memory).
178 1.1 mcr *
179 1.1 mcr * It assumes that "rbus" is defined. The whole concept does.
180 1.1 mcr *
181 1.1 mcr * It uses pci_device_foreach_min() to call rbus_pci_phys_allocate.
182 1.1 mcr * This function is mostly stolen from
183 1.15 perry * pci_addr_fixup.c:pciaddr_resource_reserve.
184 1.1 mcr *
185 1.1 mcr */
186 1.1 mcr struct rbus_pci_addr_fixup_context {
187 1.1 mcr struct ppb_cardbus_softc *csc;
188 1.1 mcr cardbus_chipset_tag_t ct;
189 1.1 mcr struct cardbus_softc *sc;
190 1.1 mcr struct cardbus_attach_args *caa;
191 1.1 mcr int minbus;
192 1.1 mcr int maxbus;
193 1.1 mcr bus_size_t *bussize_ioreqs;
194 1.1 mcr bus_size_t *bussize_memreqs;
195 1.1 mcr rbus_tag_t *iobustags;
196 1.1 mcr rbus_tag_t *membustags;
197 1.15 perry };
198 1.1 mcr
199 1.15 perry unsigned int
200 1.16 drochner rbus_round_up(unsigned int size, unsigned int minval)
201 1.1 mcr {
202 1.1 mcr unsigned int power2;
203 1.1 mcr
204 1.1 mcr if(size == 0) {
205 1.1 mcr return 0;
206 1.1 mcr }
207 1.1 mcr
208 1.16 drochner power2=minval;
209 1.1 mcr
210 1.1 mcr while(power2 < (1 << 31) &&
211 1.1 mcr power2 < size) {
212 1.1 mcr power2 = power2 << 1;
213 1.1 mcr }
214 1.15 perry
215 1.1 mcr return power2;
216 1.1 mcr }
217 1.15 perry
218 1.1 mcr static void
219 1.1 mcr rbus_pci_addr_fixup(struct ppb_cardbus_softc *csc,
220 1.1 mcr cardbus_chipset_tag_t ct,
221 1.1 mcr struct cardbus_softc *sc,
222 1.1 mcr pci_chipset_tag_t pc,
223 1.1 mcr struct cardbus_attach_args *caa,
224 1.38 dyoung int minbus, const int maxbus)
225 1.1 mcr {
226 1.1 mcr struct rbus_pci_addr_fixup_context rct;
227 1.38 dyoung const size_t size = sizeof(bus_size_t[maxbus+1]);
228 1.38 dyoung int busnum;
229 1.1 mcr bus_addr_t start;
230 1.1 mcr bus_space_handle_t handle;
231 1.1 mcr u_int32_t reg;
232 1.1 mcr
233 1.1 mcr rct.csc=csc;
234 1.1 mcr rct.ct=ct;
235 1.1 mcr rct.sc=sc;
236 1.1 mcr rct.caa=caa;
237 1.1 mcr rct.minbus = minbus;
238 1.1 mcr rct.maxbus = maxbus;
239 1.38 dyoung if ((rct.bussize_ioreqs = kmem_zalloc(size, KM_SLEEP)) == NULL ||
240 1.38 dyoung (rct.bussize_memreqs = kmem_zalloc(size, KM_SLEEP)) == NULL ||
241 1.38 dyoung (rct.iobustags =
242 1.38 dyoung kmem_zalloc(maxbus * sizeof(rbus_tag_t), KM_SLEEP)) == NULL ||
243 1.38 dyoung (rct.membustags =
244 1.38 dyoung kmem_zalloc(maxbus * sizeof(rbus_tag_t), KM_SLEEP)) == NULL)
245 1.38 dyoung panic("%s: memory allocation failed", __func__);
246 1.1 mcr
247 1.1 mcr printf("%s: sizing buses %d-%d\n",
248 1.25 joerg device_xname(rct.csc->sc_dev),
249 1.1 mcr minbus, maxbus);
250 1.1 mcr
251 1.1 mcr pci_device_foreach_min(pc, minbus, maxbus,
252 1.1 mcr rbus_pci_phys_countspace, &rct);
253 1.1 mcr
254 1.1 mcr /*
255 1.1 mcr * we need to determine amount of address space for each
256 1.1 mcr * bus. To do this, we have to roll up amounts and then
257 1.1 mcr * we need to divide up the cardbus's extent to allocate
258 1.1 mcr * some space to each bus.
259 1.1 mcr */
260 1.1 mcr
261 1.1 mcr for(busnum=maxbus; busnum > minbus; busnum--) {
262 1.1 mcr if(pci_bus_parent[busnum] != 0) {
263 1.1 mcr if(pci_bus_parent[busnum] < minbus ||
264 1.1 mcr pci_bus_parent[busnum] >= maxbus) {
265 1.1 mcr printf("%s: bus %d has illegal parent %d\n",
266 1.25 joerg device_xname(rct.csc->sc_dev),
267 1.1 mcr busnum, pci_bus_parent[busnum]);
268 1.1 mcr continue;
269 1.1 mcr }
270 1.1 mcr
271 1.1 mcr /* first round amount of space up */
272 1.1 mcr rct.bussize_ioreqs[busnum] =
273 1.1 mcr rbus_round_up(rct.bussize_ioreqs[busnum], PPB_IO_MIN);
274 1.1 mcr rct.bussize_ioreqs[pci_bus_parent[busnum]] +=
275 1.1 mcr rct.bussize_ioreqs[busnum];
276 1.1 mcr
277 1.1 mcr rct.bussize_memreqs[busnum] =
278 1.1 mcr rbus_round_up(rct.bussize_memreqs[busnum], PPB_MEM_MIN);
279 1.1 mcr rct.bussize_memreqs[pci_bus_parent[busnum]] +=
280 1.1 mcr rct.bussize_memreqs[busnum];
281 1.1 mcr
282 1.1 mcr }
283 1.1 mcr }
284 1.1 mcr
285 1.1 mcr rct.bussize_ioreqs[minbus] =
286 1.1 mcr rbus_round_up(rct.bussize_ioreqs[minbus], 4096);
287 1.1 mcr rct.bussize_memreqs[minbus] =
288 1.1 mcr rbus_round_up(rct.bussize_memreqs[minbus], 8);
289 1.1 mcr
290 1.38 dyoung printf("%s: total needs IO %08zx and MEM %08zx\n",
291 1.25 joerg device_xname(rct.csc->sc_dev),
292 1.1 mcr rct.bussize_ioreqs[minbus], rct.bussize_memreqs[minbus]);
293 1.1 mcr
294 1.1 mcr if(!caa->ca_rbus_iot) {
295 1.1 mcr panic("no iot bus");
296 1.1 mcr }
297 1.1 mcr
298 1.1 mcr if(rct.bussize_ioreqs[minbus]) {
299 1.1 mcr if(rbus_space_alloc(caa->ca_rbus_iot, 0,
300 1.1 mcr rct.bussize_ioreqs[minbus],
301 1.1 mcr rct.bussize_ioreqs[minbus]-1 /* mask */,
302 1.1 mcr rct.bussize_ioreqs[minbus] /* align */,
303 1.1 mcr /* flags */ 0,
304 1.1 mcr &start,
305 1.1 mcr &handle) != 0) {
306 1.38 dyoung panic("rbus_ppb: can not allocate %zu bytes in IO bus %d",
307 1.1 mcr rct.bussize_ioreqs[minbus], minbus);
308 1.1 mcr }
309 1.1 mcr rct.iobustags[minbus]=rbus_new(caa->ca_rbus_iot,
310 1.15 perry start,
311 1.1 mcr rct.bussize_ioreqs[minbus],
312 1.1 mcr 0 /* offset to add to physical address
313 1.1 mcr to make processor address */,
314 1.1 mcr RBUS_SPACE_DEDICATE);
315 1.1 mcr }
316 1.1 mcr
317 1.1 mcr if(rct.bussize_memreqs[minbus]) {
318 1.1 mcr if(rbus_space_alloc(caa->ca_rbus_memt, 0,
319 1.1 mcr rct.bussize_memreqs[minbus],
320 1.1 mcr rct.bussize_memreqs[minbus]-1 /* mask */,
321 1.1 mcr rct.bussize_memreqs[minbus] /* align */,
322 1.1 mcr /* flags */ 0,
323 1.1 mcr &start,
324 1.1 mcr &handle) != 0) {
325 1.38 dyoung panic("%s: can not allocate %zu bytes in MEM bus %d",
326 1.25 joerg device_xname(rct.csc->sc_dev),
327 1.1 mcr rct.bussize_memreqs[minbus], minbus);
328 1.1 mcr }
329 1.1 mcr rct.membustags[minbus]=rbus_new(caa->ca_rbus_memt,
330 1.1 mcr start,
331 1.1 mcr rct.bussize_memreqs[minbus],
332 1.1 mcr 0 /* offset to add to physical
333 1.1 mcr address to make processor
334 1.1 mcr address */,
335 1.1 mcr RBUS_SPACE_DEDICATE);
336 1.1 mcr }
337 1.1 mcr
338 1.1 mcr for(busnum=minbus+1; busnum <= maxbus; busnum++) {
339 1.1 mcr int busparent;
340 1.1 mcr
341 1.1 mcr busparent = pci_bus_parent[busnum];
342 1.1 mcr
343 1.38 dyoung printf("%s: bus %d (parent=%d) needs IO %08zx and MEM %08zx\n",
344 1.25 joerg device_xname(rct.csc->sc_dev),
345 1.1 mcr busnum,
346 1.1 mcr busparent,
347 1.1 mcr rct.bussize_ioreqs[busnum],
348 1.1 mcr rct.bussize_memreqs[busnum]);
349 1.1 mcr
350 1.1 mcr if(busparent > maxbus) {
351 1.1 mcr panic("rbus_ppb: illegal parent");
352 1.1 mcr }
353 1.1 mcr
354 1.1 mcr if(rct.bussize_ioreqs[busnum]) {
355 1.1 mcr if(rbus_space_alloc(rct.iobustags[busparent],
356 1.1 mcr 0,
357 1.1 mcr rct.bussize_ioreqs[busnum],
358 1.1 mcr rct.bussize_ioreqs[busnum]-1 /*mask */,
359 1.1 mcr rct.bussize_ioreqs[busnum] /* align */,
360 1.1 mcr /* flags */ 0,
361 1.1 mcr &start,
362 1.1 mcr &handle) != 0) {
363 1.38 dyoung panic("rbus_ppb: can not allocate %zu bytes in IO bus %d",
364 1.1 mcr rct.bussize_ioreqs[busnum], busnum);
365 1.1 mcr }
366 1.1 mcr rct.iobustags[busnum]=rbus_new(rct.iobustags[busparent],
367 1.1 mcr start,
368 1.1 mcr rct.bussize_ioreqs[busnum],
369 1.1 mcr 0 /* offset to add to physical
370 1.1 mcr address
371 1.1 mcr to make processor address */,
372 1.1 mcr RBUS_SPACE_DEDICATE);
373 1.1 mcr
374 1.1 mcr /* program the bridge */
375 1.15 perry
376 1.1 mcr /* enable I/O space */
377 1.1 mcr reg = pci_conf_read(pc, pci_bus_tag[busnum],
378 1.1 mcr PCI_COMMAND_STATUS_REG);
379 1.1 mcr reg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE;
380 1.1 mcr pci_conf_write(pc, pci_bus_tag[busnum],
381 1.1 mcr PCI_COMMAND_STATUS_REG, reg);
382 1.1 mcr
383 1.1 mcr /* now init the limit register for I/O */
384 1.1 mcr pci_conf_write(pc, pci_bus_tag[busnum], PPB_REG_IOSTATUS,
385 1.1 mcr (((start & 0xf000) >> 8) << PPB_IOBASE_SHIFT) |
386 1.1 mcr ((((start +
387 1.1 mcr rct.bussize_ioreqs[busnum] +
388 1.1 mcr 4095) & 0xf000) >> 8) << PPB_IOLIMIT_SHIFT));
389 1.1 mcr }
390 1.15 perry
391 1.1 mcr if(rct.bussize_memreqs[busnum]) {
392 1.1 mcr if(rbus_space_alloc(rct.membustags[busparent],
393 1.1 mcr 0,
394 1.15 perry rct.bussize_memreqs[busnum] /* size */,
395 1.15 perry rct.bussize_memreqs[busnum]-1 /*mask */,
396 1.1 mcr rct.bussize_memreqs[busnum] /* align */,
397 1.1 mcr /* flags */ 0,
398 1.1 mcr &start,
399 1.1 mcr &handle) != 0) {
400 1.38 dyoung panic("rbus_ppb: can not allocate %zu bytes in MEM bus %d",
401 1.1 mcr rct.bussize_memreqs[busnum], busnum);
402 1.1 mcr }
403 1.1 mcr rct.membustags[busnum]=rbus_new(rct.membustags[busparent],
404 1.1 mcr start,
405 1.1 mcr rct.bussize_memreqs[busnum],
406 1.1 mcr 0 /* offset to add to physical
407 1.1 mcr address to make processor
408 1.1 mcr address */,
409 1.1 mcr RBUS_SPACE_DEDICATE);
410 1.1 mcr
411 1.1 mcr /* program the bridge */
412 1.1 mcr /* enable memory space */
413 1.1 mcr reg = pci_conf_read(pc, pci_bus_tag[busnum],
414 1.1 mcr PCI_COMMAND_STATUS_REG);
415 1.1 mcr reg |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE;
416 1.1 mcr pci_conf_write(pc, pci_bus_tag[busnum],
417 1.1 mcr PCI_COMMAND_STATUS_REG, reg);
418 1.1 mcr
419 1.1 mcr /* now init the limit register for memory */
420 1.1 mcr pci_conf_write(pc, pci_bus_tag[busnum], PPB_REG_MEM,
421 1.1 mcr ((start & PPB_MEM_MASK)
422 1.1 mcr >> PPB_MEM_SHIFT) << PPB_MEMBASE_SHIFT |
423 1.1 mcr (((start +
424 1.1 mcr rct.bussize_memreqs[busnum] +
425 1.1 mcr PPB_MEM_MIN-1) >> PPB_MEM_SHIFT)
426 1.1 mcr << PPB_MEMLIMIT_SHIFT));
427 1.1 mcr
428 1.1 mcr /* and set the prefetchable limits as well */
429 1.1 mcr pci_conf_write(pc, pci_bus_tag[busnum], PPB_REG_PREFMEM,
430 1.1 mcr ((start & PPB_MEM_MASK)
431 1.1 mcr >> PPB_MEM_SHIFT) << PPB_MEMBASE_SHIFT |
432 1.1 mcr (((start +
433 1.1 mcr rct.bussize_memreqs[busnum] +
434 1.1 mcr PPB_MEM_MIN-1) >> PPB_MEM_SHIFT)
435 1.1 mcr << PPB_MEMLIMIT_SHIFT));
436 1.1 mcr
437 1.1 mcr /* pci_conf_print(pc, pci_bus_tag[busnum], NULL); */
438 1.1 mcr }
439 1.1 mcr }
440 1.1 mcr
441 1.1 mcr printf("%s: configuring buses %d-%d\n",
442 1.25 joerg device_xname(rct.csc->sc_dev),
443 1.1 mcr minbus, maxbus);
444 1.1 mcr pci_device_foreach_min(pc, minbus, maxbus,
445 1.1 mcr rbus_pci_phys_allocate, &rct);
446 1.38 dyoung
447 1.38 dyoung kmem_free(rct.bussize_ioreqs, size);
448 1.38 dyoung kmem_free(rct.bussize_memreqs, size);
449 1.38 dyoung kmem_free(rct.iobustags, maxbus * sizeof(rbus_tag_t));
450 1.38 dyoung kmem_free(rct.membustags, maxbus * sizeof(rbus_tag_t));
451 1.1 mcr }
452 1.1 mcr
453 1.1 mcr static void
454 1.27 dsl rbus_pci_phys_countspace(pci_chipset_tag_t pc, pcitag_t tag, void *context)
455 1.1 mcr {
456 1.1 mcr int bus, device, function;
457 1.1 mcr struct rbus_pci_addr_fixup_context *rct =
458 1.1 mcr (struct rbus_pci_addr_fixup_context *)context;
459 1.1 mcr
460 1.1 mcr pci_decompose_tag(pc, tag, &bus, &device, &function);
461 1.1 mcr
462 1.1 mcr printf("%s: configuring device %02x:%02x:%02x\n",
463 1.25 joerg device_xname(rct->csc->sc_dev),
464 1.1 mcr bus, device, function);
465 1.1 mcr
466 1.1 mcr pciaddr_resource_manage(pc, tag,
467 1.1 mcr rbus_do_phys_countspace, context);
468 1.1 mcr }
469 1.1 mcr
470 1.15 perry
471 1.1 mcr int
472 1.28 dsl rbus_do_phys_countspace(pci_chipset_tag_t pc, pcitag_t tag, int mapreg, void *ctx, int type, bus_addr_t *addr, bus_size_t size)
473 1.1 mcr {
474 1.1 mcr struct rbus_pci_addr_fixup_context *rct =
475 1.1 mcr (struct rbus_pci_addr_fixup_context *)ctx;
476 1.1 mcr int bus, device, function;
477 1.1 mcr
478 1.1 mcr pci_decompose_tag(pc, tag, &bus, &device, &function);
479 1.1 mcr
480 1.1 mcr if(size > (1<<24)) {
481 1.1 mcr printf("%s: skipping huge space request of size=%08x\n",
482 1.25 joerg device_xname(rct->csc->sc_dev), (unsigned int)size);
483 1.1 mcr return 0;
484 1.1 mcr }
485 1.1 mcr
486 1.1 mcr if(PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_IO) {
487 1.1 mcr rct->bussize_ioreqs[bus] += size;
488 1.1 mcr } else {
489 1.1 mcr rct->bussize_memreqs[bus]+= size;
490 1.1 mcr }
491 1.15 perry
492 1.1 mcr return 0;
493 1.1 mcr }
494 1.1 mcr
495 1.1 mcr static void
496 1.27 dsl rbus_pci_phys_allocate(pci_chipset_tag_t pc, pcitag_t tag, void *context)
497 1.1 mcr {
498 1.1 mcr int bus, device, function, command;
499 1.1 mcr struct rbus_pci_addr_fixup_context *rct =
500 1.1 mcr (struct rbus_pci_addr_fixup_context *)context;
501 1.15 perry
502 1.1 mcr pci_decompose_tag(pc, tag, &bus, &device, &function);
503 1.1 mcr
504 1.1 mcr printf("%s: configuring device %02x:%02x:%02x\n",
505 1.25 joerg device_xname(rct->csc->sc_dev),
506 1.1 mcr bus, device, function);
507 1.1 mcr
508 1.1 mcr pciaddr_resource_manage(pc, tag,
509 1.1 mcr rbus_do_phys_allocate, context);
510 1.1 mcr
511 1.1 mcr /* now turn the device's memory and I/O on */
512 1.1 mcr command = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
513 1.1 mcr command |= PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE;
514 1.1 mcr pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, command);
515 1.1 mcr }
516 1.1 mcr
517 1.1 mcr int
518 1.28 dsl rbus_do_phys_allocate(pci_chipset_tag_t pc, pcitag_t tag, int mapreg, void *ctx, int type, bus_addr_t *addr, bus_size_t size)
519 1.1 mcr {
520 1.1 mcr struct rbus_pci_addr_fixup_context *rct =
521 1.1 mcr (struct rbus_pci_addr_fixup_context *)ctx;
522 1.1 mcr cardbus_chipset_tag_t ct = rct->ct;
523 1.1 mcr struct cardbus_softc *sc = rct->sc;
524 1.1 mcr cardbus_function_t *cf = sc->sc_cf;
525 1.1 mcr rbus_tag_t rbustag;
526 1.1 mcr bus_addr_t mask = size -1;
527 1.1 mcr bus_addr_t base = 0;
528 1.1 mcr bus_space_handle_t handle;
529 1.1 mcr int busflags = 0;
530 1.1 mcr int flags = 0;
531 1.16 drochner const char *bustype;
532 1.1 mcr int bus, device, function;
533 1.1 mcr
534 1.1 mcr pci_decompose_tag(pc, tag, &bus, &device, &function);
535 1.1 mcr
536 1.1 mcr /*
537 1.1 mcr * some devices come up with garbage in them (Tulip?)
538 1.1 mcr * we are in charge here, so give them address
539 1.15 perry * space anyway.
540 1.1 mcr *
541 1.1 mcr * XXX this may be due to no secondary PCI reset!!!
542 1.1 mcr */
543 1.1 mcr #if 0
544 1.1 mcr if (*addr) {
545 1.1 mcr printf("Already allocated space at %08x\n",
546 1.1 mcr (unsigned int)*addr);
547 1.1 mcr return (0);
548 1.1 mcr }
549 1.1 mcr #endif
550 1.1 mcr
551 1.1 mcr if(size > (1<<24)) {
552 1.1 mcr printf("%s: skipping huge space request of size=%08x\n",
553 1.25 joerg device_xname(rct->csc->sc_dev), (unsigned int)size);
554 1.1 mcr return 0;
555 1.1 mcr }
556 1.1 mcr
557 1.1 mcr if(PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_IO) {
558 1.1 mcr rbustag = rct->iobustags[bus];
559 1.1 mcr bustype = "io";
560 1.1 mcr } else {
561 1.1 mcr rbustag = rct->membustags[bus];
562 1.1 mcr bustype = "mem";
563 1.1 mcr }
564 1.1 mcr
565 1.1 mcr if((*cf->cardbus_space_alloc)(ct, rbustag, base, size,
566 1.1 mcr mask, size, busflags|flags,
567 1.1 mcr addr, &handle)) {
568 1.1 mcr printf("%s: no available resources (size=%08x) for bar %2d. fixup failed\n",
569 1.25 joerg device_xname(rct->csc->sc_dev), (unsigned int)size, mapreg);
570 1.1 mcr
571 1.1 mcr *addr = 0;
572 1.1 mcr pci_conf_write(pc, tag, mapreg, *addr);
573 1.1 mcr return (1);
574 1.1 mcr }
575 1.1 mcr
576 1.1 mcr printf("%s: alloc %s space of size %08x for %02d:%02d:%02d -> %08x\n",
577 1.25 joerg device_xname(rct->csc->sc_dev),
578 1.15 perry bustype,
579 1.1 mcr (unsigned int)size,
580 1.1 mcr bus, device, function, (unsigned int)*addr);
581 1.1 mcr
582 1.1 mcr /* write new address to PCI device configuration header */
583 1.1 mcr pci_conf_write(pc, tag, mapreg, *addr);
584 1.1 mcr
585 1.1 mcr /* check */
586 1.1 mcr {
587 1.1 mcr DPRINTF(("%s: pci_addr_fixup: ",
588 1.25 joerg device_xname(rct->csc->sc_dev)));
589 1.1 mcr #ifdef CBB_DEBUG
590 1.1 mcr if(rbus_ppb_debug) { pciaddr_print_devid(pc, tag); }
591 1.1 mcr #endif
592 1.1 mcr }
593 1.1 mcr
594 1.1 mcr /* double check that the value got inserted correctly */
595 1.1 mcr if (pciaddr_ioaddr(pci_conf_read(pc, tag, mapreg)) != *addr) {
596 1.1 mcr pci_conf_write(pc, tag, mapreg, 0); /* clear */
597 1.1 mcr printf("%s: fixup failed. (new address=%#x)\n",
598 1.25 joerg device_xname(rct->csc->sc_dev),
599 1.1 mcr (unsigned)*addr);
600 1.1 mcr return (1);
601 1.1 mcr }
602 1.1 mcr
603 1.1 mcr DPRINTF(("new address 0x%08x\n",
604 1.1 mcr (unsigned)*addr));
605 1.1 mcr
606 1.1 mcr return (0);
607 1.1 mcr }
608 1.1 mcr
609 1.1 mcr static void
610 1.25 joerg ppb_cardbus_attach(device_t parent, device_t self, void *aux)
611 1.1 mcr {
612 1.19 thorpej struct ppb_cardbus_softc *csc = device_private(self);
613 1.24 joerg struct cardbus_softc *parent_sc = device_private(parent);
614 1.1 mcr struct cardbus_attach_args *ca = aux;
615 1.1 mcr cardbus_devfunc_t ct = ca->ca_ct;
616 1.1 mcr cardbus_chipset_tag_t cc = ct->ct_cc;
617 1.1 mcr struct pccbb_softc *psc = (struct pccbb_softc *)cc;
618 1.1 mcr struct pcibus_attach_args pba;
619 1.1 mcr char devinfo[256];
620 1.1 mcr pcireg_t busdata;
621 1.1 mcr int minbus, maxbus;
622 1.1 mcr
623 1.25 joerg csc->sc_dev = self;
624 1.25 joerg
625 1.11 itojun pci_devinfo(ca->ca_id, ca->ca_class, 0, devinfo, sizeof(devinfo));
626 1.1 mcr printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(ca->ca_class));
627 1.1 mcr
628 1.32 dyoung csc->sc_tag = ca->ca_tag;
629 1.3 thorpej
630 1.35 dyoung busdata = Cardbus_conf_read(ct, ca->ca_tag, PPB_REG_BUSINFO);
631 1.1 mcr minbus = pcibios_max_bus;
632 1.10 lukem maxbus = minbus; /* XXX; gcc */
633 1.1 mcr
634 1.1 mcr if (PPB_BUSINFO_SECONDARY(busdata) == 0) {
635 1.21 cegger aprint_error_dev(self, "not configured by system firmware calling pci_bus_fixup(%d)\n", 0);
636 1.1 mcr
637 1.1 mcr /*
638 1.1 mcr * first, pull the reset wire on the secondary bridge
639 1.1 mcr * to clear all devices
640 1.1 mcr */
641 1.35 dyoung busdata = Cardbus_conf_read(ct, ca->ca_tag,
642 1.1 mcr PPB_REG_BRIDGECONTROL);
643 1.35 dyoung Cardbus_conf_write(ct, ca->ca_tag, PPB_REG_BRIDGECONTROL,
644 1.1 mcr busdata | PPB_BC_SECONDARY_RESET);
645 1.1 mcr delay(1);
646 1.35 dyoung Cardbus_conf_write(ct, ca->ca_tag, PPB_REG_BRIDGECONTROL,
647 1.1 mcr busdata);
648 1.1 mcr
649 1.1 mcr /* then go initialize the bridge control registers */
650 1.1 mcr maxbus = pci_bus_fixup(psc->sc_pc, 0);
651 1.1 mcr }
652 1.1 mcr
653 1.35 dyoung busdata = Cardbus_conf_read(ct, ca->ca_tag, PPB_REG_BUSINFO);
654 1.1 mcr if(PPB_BUSINFO_SECONDARY(busdata) == 0) {
655 1.21 cegger aprint_error_dev(self, "still not configured, not fixable.\n");
656 1.21 cegger return;
657 1.1 mcr }
658 1.1 mcr
659 1.15 perry #if 0
660 1.1 mcr minbus = PPB_BUSINFO_SECONDARY(busdata);
661 1.1 mcr maxbus = PPB_BUSINFO_SUBORDINATE(busdata);
662 1.1 mcr #endif
663 1.15 perry
664 1.1 mcr /* now, go and assign addresses for the new devices */
665 1.1 mcr rbus_pci_addr_fixup(csc, cc, parent_sc,
666 1.1 mcr psc->sc_pc,
667 1.1 mcr ca,
668 1.1 mcr minbus, maxbus);
669 1.1 mcr
670 1.1 mcr /*
671 1.1 mcr * now configure all connected devices to the IRQ which
672 1.1 mcr * was assigned to this slot, as they will all arrive from
673 1.1 mcr * that IRQ.
674 1.1 mcr */
675 1.41 drochner rbus_intr_fixup(psc->sc_pc, minbus, maxbus, 0);
676 1.1 mcr
677 1.15 perry /*
678 1.1 mcr * enable direct routing of interrupts. We do this because
679 1.1 mcr * we can not manage to get pccb_intr_establish() called until
680 1.1 mcr * PCI subsystem is merged with rbus. The major thing that this
681 1.1 mcr * routine does is avoid calling the driver's interrupt routine
682 1.1 mcr * when the card has been removed.
683 1.1 mcr *
684 1.1 mcr * The rbus_ppb.c can not cope with card desertions until the merging
685 1.1 mcr * anyway.
686 1.1 mcr */
687 1.1 mcr pccbb_intr_route(psc);
688 1.1 mcr
689 1.1 mcr /*
690 1.1 mcr * Attach the PCI bus than hangs off of it.
691 1.1 mcr *
692 1.1 mcr * XXX Don't pass-through Memory Read Multiple. Should we?
693 1.1 mcr * XXX Consult the spec...
694 1.15 perry */
695 1.1 mcr pba.pba_iot = ca->ca_iot;
696 1.1 mcr pba.pba_memt = ca->ca_memt;
697 1.1 mcr pba.pba_dmat = ca->ca_dmat;
698 1.1 mcr pba.pba_pc = psc->sc_pc;
699 1.40 dyoung pba.pba_flags = PCI_FLAGS_IO_OKAY|PCI_FLAGS_MEM_OKAY;
700 1.1 mcr pba.pba_bus = PPB_BUSINFO_SECONDARY(busdata);
701 1.4 lukem pba.pba_bridgetag = &csc->sc_tag;
702 1.1 mcr /*pba.pba_intrswiz = parent_sc->sc_intrswiz; */
703 1.1 mcr pba.pba_intrtag = psc->sc_pa.pa_intrtag;
704 1.1 mcr
705 1.13 drochner config_found_ia(self, "pcibus", &pba, rppbprint);
706 1.1 mcr }
707 1.1 mcr
708 1.1 mcr int
709 1.31 cegger ppb_activate(device_t self, enum devact act)
710 1.1 mcr {
711 1.1 mcr printf("ppb_activate called\n");
712 1.1 mcr return 0;
713 1.1 mcr }
714 1.1 mcr
715