rbus_ppb.c revision 1.1
1 /* $NetBSD: rbus_ppb.c,v 1.1 2001/07/06 18:05:59 mcr Exp $ */ 2 3 /* 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Michael Richardson <mcr (at) sandelman.ottawa.on.ca> 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * CardBus front-end for the Intel/Digital DECchip 21152 PCI-PCI bridge 41 */ 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/mbuf.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/socket.h> 49 #include <sys/ioctl.h> 50 #include <sys/errno.h> 51 #include <sys/device.h> 52 53 #if NRND > 0 54 #include <sys/rnd.h> 55 #endif 56 57 #include <machine/endian.h> 58 59 #include <machine/bus.h> 60 #include <machine/intr.h> 61 62 #include <dev/pci/pcivar.h> 63 #include <dev/pci/pcireg.h> 64 #include <dev/pci/pcidevs.h> 65 #include <dev/pci/ppbreg.h> 66 67 #include <dev/ic/i82365reg.h> 68 #include <dev/ic/i82365var.h> 69 70 #include <dev/pci/pccbbreg.h> 71 #include <dev/pci/pccbbvar.h> 72 73 #include <dev/cardbus/cardbusvar.h> 74 #include <dev/cardbus/cardbusdevs.h> 75 76 #include <i386/pci/pci_addr_fixup.h> 77 #include <i386/pci/pci_bus_fixup.h> 78 #include <i386/pci/pci_intr_fixup.h> 79 #include <i386/pci/pcibios.h> 80 81 struct ppb_softc; 82 83 static int ppb_cardbus_match __P((struct device *, struct cfdata *, void *)); 84 static void ppb_cardbus_attach __P((struct device *, struct device *, void *)); 85 static int ppb_cardbus_detach __P((struct device * self, int flags)); 86 /*static*/ void ppb_cardbus_setup __P((struct ppb_softc * sc)); 87 /*static*/ int ppb_cardbus_enable __P((struct ppb_softc * sc)); 88 /*static*/ void ppb_cardbus_disable __P((struct ppb_softc * sc)); 89 static int ppb_activate __P((struct device *self, enum devact act)); 90 int rppbprint __P((void *aux, const char *pnp)); 91 int rbus_intr_fixup __P((pci_chipset_tag_t pc, int minbus, 92 int maxbus, int line)); 93 void rbus_do_header_fixup __P((pci_chipset_tag_t pc, pcitag_t tag, 94 void *context)); 95 96 static void rbus_pci_phys_allocate __P((pci_chipset_tag_t pc, 97 pcitag_t tag, 98 void *context)); 99 100 static int rbus_do_phys_allocate __P((pci_chipset_tag_t pc, 101 pcitag_t tag, 102 int mapreg, 103 void *ctx, 104 int type, 105 bus_addr_t *addr, 106 bus_size_t size)); 107 108 static void rbus_pci_phys_countspace __P((pci_chipset_tag_t pc, 109 pcitag_t tag, 110 void *context)); 111 112 static int rbus_do_phys_countspace __P((pci_chipset_tag_t pc, 113 pcitag_t tag, 114 int mapreg, 115 void *ctx, 116 int type, 117 bus_addr_t *addr, 118 bus_size_t size)); 119 120 unsigned int rbus_round_up __P((unsigned int size, unsigned int min)); 121 122 123 struct ppb_cardbus_softc { 124 struct device sc_dev; 125 int foo; 126 }; 127 128 struct cfattach rbus_ppb_ca = { 129 sizeof(struct ppb_cardbus_softc), 130 ppb_cardbus_match, 131 ppb_cardbus_attach, 132 ppb_cardbus_detach, 133 ppb_activate 134 }; 135 136 #ifdef CBB_DEBUG 137 int rbus_ppb_debug = 0; /* hack with kdb */ 138 #define DPRINTF(X) if(rbus_ppb_debug) printf X 139 #else 140 #define DPRINTF(X) 141 #endif 142 143 static int 144 ppb_cardbus_match(parent, match, aux) 145 struct device *parent; 146 struct cfdata *match; 147 void *aux; 148 { 149 struct cardbus_attach_args *ca = aux; 150 151 if (CARDBUS_VENDOR(ca->ca_id) == PCI_VENDOR_DEC && 152 CARDBUS_PRODUCT(ca->ca_id) == PCI_PRODUCT_DEC_21152) 153 return (1); 154 155 if(PCI_CLASS(ca->ca_class) == PCI_CLASS_BRIDGE && 156 PCI_SUBCLASS(ca->ca_class) == PCI_SUBCLASS_BRIDGE_PCI) { 157 /* XXX */ 158 printf("recognizing generic bridge chip\n"); 159 } 160 161 return (0); 162 } 163 164 165 int 166 rppbprint(aux, pnp) 167 void *aux; 168 const char *pnp; 169 { 170 struct pcibus_attach_args *pba = aux; 171 172 /* only PCIs can attach to PPBs; easy. */ 173 if (pnp) 174 printf("pci at %s", pnp); 175 printf(" bus %d (rbus)", pba->pba_bus); 176 return (UNCONF); 177 } 178 179 int 180 rbus_intr_fixup(pci_chipset_tag_t pc, 181 int minbus, 182 int maxbus, 183 int line) 184 { 185 pci_device_foreach_min(pc, minbus, 186 maxbus, rbus_do_header_fixup, (void *)&line); 187 return 0; 188 } 189 190 void 191 rbus_do_header_fixup(pc, tag, context) 192 pci_chipset_tag_t pc; 193 pcitag_t tag; 194 void *context; 195 { 196 int pin, irq; 197 int bus, device, function; 198 pcireg_t intr, id; 199 int *pline = (int *)context; 200 int line = *pline; 201 202 pci_decompose_tag(pc, tag, &bus, &device, &function); 203 id = pci_conf_read(pc, tag, PCI_ID_REG); 204 205 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 206 pin = PCI_INTERRUPT_PIN(intr); 207 irq = PCI_INTERRUPT_LINE(intr); 208 209 #if 0 210 printf("do_header %02x:%02x:%02x pin=%d => line %d\n", 211 bus, device, function, pin, line); 212 #endif 213 214 intr &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT); 215 intr |= (line << PCI_INTERRUPT_LINE_SHIFT); 216 pci_conf_write(pc, tag, PCI_INTERRUPT_REG, intr); 217 218 } 219 220 /* 221 * This function takes a range of PCI bus numbers and 222 * allocates space for all devices found in this space (the BARs) from 223 * the rbus space maps (I/O and memory). 224 * 225 * It assumes that "rbus" is defined. The whole concept does. 226 * 227 * It uses pci_device_foreach_min() to call rbus_pci_phys_allocate. 228 * This function is mostly stolen from 229 * pci_addr_fixup.c:pciaddr_resource_reserve. 230 * 231 */ 232 struct rbus_pci_addr_fixup_context { 233 struct ppb_cardbus_softc *csc; 234 cardbus_chipset_tag_t ct; 235 struct cardbus_softc *sc; 236 struct cardbus_attach_args *caa; 237 int minbus; 238 int maxbus; 239 bus_size_t *bussize_ioreqs; 240 bus_size_t *bussize_memreqs; 241 rbus_tag_t *iobustags; 242 rbus_tag_t *membustags; 243 }; 244 245 unsigned int 246 rbus_round_up(unsigned int size, unsigned int min) 247 { 248 unsigned int power2; 249 250 if(size == 0) { 251 return 0; 252 } 253 254 power2=min; 255 256 while(power2 < (1 << 31) && 257 power2 < size) { 258 power2 = power2 << 1; 259 } 260 261 return power2; 262 } 263 264 static void 265 rbus_pci_addr_fixup(struct ppb_cardbus_softc *csc, 266 cardbus_chipset_tag_t ct, 267 struct cardbus_softc *sc, 268 pci_chipset_tag_t pc, 269 struct cardbus_attach_args *caa, 270 int minbus, int maxbus) 271 { 272 struct rbus_pci_addr_fixup_context rct; 273 int size, busnum; 274 bus_addr_t start; 275 bus_space_handle_t handle; 276 u_int32_t reg; 277 278 rct.csc=csc; 279 rct.ct=ct; 280 rct.sc=sc; 281 rct.caa=caa; 282 rct.minbus = minbus; 283 rct.maxbus = maxbus; 284 size = sizeof(bus_size_t)*(maxbus+1); 285 rct.bussize_ioreqs = alloca(size); 286 rct.bussize_memreqs = alloca(size); 287 rct.iobustags = alloca(maxbus * sizeof(rbus_tag_t)); 288 rct.membustags = alloca(maxbus * sizeof(rbus_tag_t)); 289 290 bzero(rct.bussize_ioreqs, size); 291 bzero(rct.bussize_memreqs, size); 292 293 printf("%s: sizing buses %d-%d\n", 294 rct.csc->sc_dev.dv_xname, 295 minbus, maxbus); 296 297 pci_device_foreach_min(pc, minbus, maxbus, 298 rbus_pci_phys_countspace, &rct); 299 300 /* 301 * we need to determine amount of address space for each 302 * bus. To do this, we have to roll up amounts and then 303 * we need to divide up the cardbus's extent to allocate 304 * some space to each bus. 305 */ 306 307 for(busnum=maxbus; busnum > minbus; busnum--) { 308 if(pci_bus_parent[busnum] != 0) { 309 if(pci_bus_parent[busnum] < minbus || 310 pci_bus_parent[busnum] >= maxbus) { 311 printf("%s: bus %d has illegal parent %d\n", 312 rct.csc->sc_dev.dv_xname, 313 busnum, pci_bus_parent[busnum]); 314 continue; 315 } 316 317 /* first round amount of space up */ 318 rct.bussize_ioreqs[busnum] = 319 rbus_round_up(rct.bussize_ioreqs[busnum], PPB_IO_MIN); 320 rct.bussize_ioreqs[pci_bus_parent[busnum]] += 321 rct.bussize_ioreqs[busnum]; 322 323 rct.bussize_memreqs[busnum] = 324 rbus_round_up(rct.bussize_memreqs[busnum], PPB_MEM_MIN); 325 rct.bussize_memreqs[pci_bus_parent[busnum]] += 326 rct.bussize_memreqs[busnum]; 327 328 } 329 } 330 331 rct.bussize_ioreqs[minbus] = 332 rbus_round_up(rct.bussize_ioreqs[minbus], 4096); 333 rct.bussize_memreqs[minbus] = 334 rbus_round_up(rct.bussize_memreqs[minbus], 8); 335 336 printf("%s: total needs IO %08lx and MEM %08lx\n", 337 rct.csc->sc_dev.dv_xname, 338 rct.bussize_ioreqs[minbus], rct.bussize_memreqs[minbus]); 339 340 if(!caa->ca_rbus_iot) { 341 panic("no iot bus"); 342 } 343 344 if(rct.bussize_ioreqs[minbus]) { 345 if(rbus_space_alloc(caa->ca_rbus_iot, 0, 346 rct.bussize_ioreqs[minbus], 347 rct.bussize_ioreqs[minbus]-1 /* mask */, 348 rct.bussize_ioreqs[minbus] /* align */, 349 /* flags */ 0, 350 &start, 351 &handle) != 0) { 352 panic("rbus_ppb: can not allocate %ld bytes in IO bus %d\n", 353 rct.bussize_ioreqs[minbus], minbus); 354 } 355 rct.iobustags[minbus]=rbus_new(caa->ca_rbus_iot, 356 start, 357 rct.bussize_ioreqs[minbus], 358 0 /* offset to add to physical address 359 to make processor address */, 360 RBUS_SPACE_DEDICATE); 361 } 362 363 if(rct.bussize_memreqs[minbus]) { 364 if(rbus_space_alloc(caa->ca_rbus_memt, 0, 365 rct.bussize_memreqs[minbus], 366 rct.bussize_memreqs[minbus]-1 /* mask */, 367 rct.bussize_memreqs[minbus] /* align */, 368 /* flags */ 0, 369 &start, 370 &handle) != 0) { 371 panic("%s: can not allocate %ld bytes in MEM bus %d\n", 372 rct.csc->sc_dev.dv_xname, 373 rct.bussize_memreqs[minbus], minbus); 374 } 375 rct.membustags[minbus]=rbus_new(caa->ca_rbus_memt, 376 start, 377 rct.bussize_memreqs[minbus], 378 0 /* offset to add to physical 379 address to make processor 380 address */, 381 RBUS_SPACE_DEDICATE); 382 } 383 384 for(busnum=minbus+1; busnum <= maxbus; busnum++) { 385 int busparent; 386 387 busparent = pci_bus_parent[busnum]; 388 389 printf("%s: bus %d (parent=%d) needs IO %08lx and MEM %08lx\n", 390 rct.csc->sc_dev.dv_xname, 391 busnum, 392 busparent, 393 rct.bussize_ioreqs[busnum], 394 rct.bussize_memreqs[busnum]); 395 396 if(busparent > maxbus) { 397 panic("rbus_ppb: illegal parent"); 398 } 399 400 if(rct.bussize_ioreqs[busnum]) { 401 if(rbus_space_alloc(rct.iobustags[busparent], 402 0, 403 rct.bussize_ioreqs[busnum], 404 rct.bussize_ioreqs[busnum]-1 /*mask */, 405 rct.bussize_ioreqs[busnum] /* align */, 406 /* flags */ 0, 407 &start, 408 &handle) != 0) { 409 panic("rbus_ppb: can not allocate %ld bytes in IO bus %d\n", 410 rct.bussize_ioreqs[busnum], busnum); 411 } 412 rct.iobustags[busnum]=rbus_new(rct.iobustags[busparent], 413 start, 414 rct.bussize_ioreqs[busnum], 415 0 /* offset to add to physical 416 address 417 to make processor address */, 418 RBUS_SPACE_DEDICATE); 419 420 /* program the bridge */ 421 422 /* enable I/O space */ 423 reg = pci_conf_read(pc, pci_bus_tag[busnum], 424 PCI_COMMAND_STATUS_REG); 425 reg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE; 426 pci_conf_write(pc, pci_bus_tag[busnum], 427 PCI_COMMAND_STATUS_REG, reg); 428 429 /* now init the limit register for I/O */ 430 pci_conf_write(pc, pci_bus_tag[busnum], PPB_REG_IOSTATUS, 431 (((start & 0xf000) >> 8) << PPB_IOBASE_SHIFT) | 432 ((((start + 433 rct.bussize_ioreqs[busnum] + 434 4095) & 0xf000) >> 8) << PPB_IOLIMIT_SHIFT)); 435 } 436 437 if(rct.bussize_memreqs[busnum]) { 438 if(rbus_space_alloc(rct.membustags[busparent], 439 0, 440 rct.bussize_memreqs[busnum] /* size */, 441 rct.bussize_memreqs[busnum]-1 /*mask */, 442 rct.bussize_memreqs[busnum] /* align */, 443 /* flags */ 0, 444 &start, 445 &handle) != 0) { 446 panic("rbus_ppb: can not allocate %ld bytes in MEM bus %d\n", 447 rct.bussize_memreqs[busnum], busnum); 448 } 449 rct.membustags[busnum]=rbus_new(rct.membustags[busparent], 450 start, 451 rct.bussize_memreqs[busnum], 452 0 /* offset to add to physical 453 address to make processor 454 address */, 455 RBUS_SPACE_DEDICATE); 456 457 /* program the bridge */ 458 /* enable memory space */ 459 reg = pci_conf_read(pc, pci_bus_tag[busnum], 460 PCI_COMMAND_STATUS_REG); 461 reg |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 462 pci_conf_write(pc, pci_bus_tag[busnum], 463 PCI_COMMAND_STATUS_REG, reg); 464 465 /* now init the limit register for memory */ 466 pci_conf_write(pc, pci_bus_tag[busnum], PPB_REG_MEM, 467 ((start & PPB_MEM_MASK) 468 >> PPB_MEM_SHIFT) << PPB_MEMBASE_SHIFT | 469 (((start + 470 rct.bussize_memreqs[busnum] + 471 PPB_MEM_MIN-1) >> PPB_MEM_SHIFT) 472 << PPB_MEMLIMIT_SHIFT)); 473 474 /* and set the prefetchable limits as well */ 475 pci_conf_write(pc, pci_bus_tag[busnum], PPB_REG_PREFMEM, 476 ((start & PPB_MEM_MASK) 477 >> PPB_MEM_SHIFT) << PPB_MEMBASE_SHIFT | 478 (((start + 479 rct.bussize_memreqs[busnum] + 480 PPB_MEM_MIN-1) >> PPB_MEM_SHIFT) 481 << PPB_MEMLIMIT_SHIFT)); 482 483 /* pci_conf_print(pc, pci_bus_tag[busnum], NULL); */ 484 } 485 } 486 487 printf("%s: configuring buses %d-%d\n", 488 rct.csc->sc_dev.dv_xname, 489 minbus, maxbus); 490 pci_device_foreach_min(pc, minbus, maxbus, 491 rbus_pci_phys_allocate, &rct); 492 } 493 494 static void 495 rbus_pci_phys_countspace(pc, tag, context) 496 pci_chipset_tag_t pc; 497 pcitag_t tag; 498 void *context; 499 { 500 int bus, device, function; 501 struct rbus_pci_addr_fixup_context *rct = 502 (struct rbus_pci_addr_fixup_context *)context; 503 504 pci_decompose_tag(pc, tag, &bus, &device, &function); 505 506 printf("%s: configuring device %02x:%02x:%02x\n", 507 rct->csc->sc_dev.dv_xname, 508 bus, device, function); 509 510 pciaddr_resource_manage(pc, tag, 511 rbus_do_phys_countspace, context); 512 } 513 514 515 int 516 rbus_do_phys_countspace(pc, tag, mapreg, ctx, type, addr, size) 517 pci_chipset_tag_t pc; 518 pcitag_t tag; 519 void *ctx; 520 int mapreg, type; 521 bus_addr_t *addr; 522 bus_size_t size; 523 { 524 struct rbus_pci_addr_fixup_context *rct = 525 (struct rbus_pci_addr_fixup_context *)ctx; 526 int bus, device, function; 527 528 pci_decompose_tag(pc, tag, &bus, &device, &function); 529 530 if(size > (1<<24)) { 531 printf("%s: skipping huge space request of size=%08x\n", 532 rct->csc->sc_dev.dv_xname, (unsigned int)size); 533 return 0; 534 } 535 536 if(PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_IO) { 537 rct->bussize_ioreqs[bus] += size; 538 } else { 539 rct->bussize_memreqs[bus]+= size; 540 } 541 542 return 0; 543 } 544 545 static void 546 rbus_pci_phys_allocate(pc, tag, context) 547 pci_chipset_tag_t pc; 548 pcitag_t tag; 549 void *context; 550 { 551 int bus, device, function, command; 552 struct rbus_pci_addr_fixup_context *rct = 553 (struct rbus_pci_addr_fixup_context *)context; 554 //cardbus_chipset_tag_t ct = rct->ct; 555 // struct cardbus_softc *sc = rct->sc; 556 557 pci_decompose_tag(pc, tag, &bus, &device, &function); 558 559 printf("%s: configuring device %02x:%02x:%02x\n", 560 rct->csc->sc_dev.dv_xname, 561 bus, device, function); 562 563 pciaddr_resource_manage(pc, tag, 564 rbus_do_phys_allocate, context); 565 566 /* now turn the device's memory and I/O on */ 567 command = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 568 command |= PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE; 569 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, command); 570 } 571 572 int 573 rbus_do_phys_allocate(pc, tag, mapreg, ctx, type, addr, size) 574 pci_chipset_tag_t pc; 575 pcitag_t tag; 576 void *ctx; 577 int mapreg, type; 578 bus_addr_t *addr; 579 bus_size_t size; 580 { 581 struct rbus_pci_addr_fixup_context *rct = 582 (struct rbus_pci_addr_fixup_context *)ctx; 583 cardbus_chipset_tag_t ct = rct->ct; 584 struct cardbus_softc *sc = rct->sc; 585 cardbus_function_t *cf = sc->sc_cf; 586 rbus_tag_t rbustag; 587 bus_space_tag_t bustag; 588 bus_addr_t mask = size -1; 589 bus_addr_t base = 0; 590 bus_space_handle_t handle; 591 int busflags = 0; 592 int flags = 0; 593 char *bustype; 594 int bus, device, function; 595 596 pci_decompose_tag(pc, tag, &bus, &device, &function); 597 598 /* 599 * some devices come up with garbage in them (Tulip?) 600 * we are in charge here, so give them address 601 * space anyway. 602 * 603 * XXX this may be due to no secondary PCI reset!!! 604 */ 605 #if 0 606 if (*addr) { 607 printf("Already allocated space at %08x\n", 608 (unsigned int)*addr); 609 return (0); 610 } 611 #endif 612 613 if(size > (1<<24)) { 614 printf("%s: skipping huge space request of size=%08x\n", 615 rct->csc->sc_dev.dv_xname, (unsigned int)size); 616 return 0; 617 } 618 619 if(PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_IO) { 620 bustag = sc->sc_iot; 621 rbustag = rct->iobustags[bus]; 622 bustype = "io"; 623 } else { 624 bustag = sc->sc_memt; 625 rbustag = rct->membustags[bus]; 626 bustype = "mem"; 627 } 628 629 if((*cf->cardbus_space_alloc)(ct, rbustag, base, size, 630 mask, size, busflags|flags, 631 addr, &handle)) { 632 printf("%s: no available resources (size=%08x) for bar %2d. fixup failed\n", 633 rct->csc->sc_dev.dv_xname, (unsigned int)size, mapreg); 634 635 *addr = 0; 636 pci_conf_write(pc, tag, mapreg, *addr); 637 return (1); 638 } 639 640 printf("%s: alloc %s space of size %08x for %02d:%02d:%02d -> %08x\n", 641 rct->csc->sc_dev.dv_xname, 642 bustype, 643 (unsigned int)size, 644 bus, device, function, (unsigned int)*addr); 645 646 /* write new address to PCI device configuration header */ 647 pci_conf_write(pc, tag, mapreg, *addr); 648 649 /* check */ 650 { 651 DPRINTF(("%s: pci_addr_fixup: ", 652 rct->csc->sc_dev.dv_xname)); 653 #ifdef CBB_DEBUG 654 if(rbus_ppb_debug) { pciaddr_print_devid(pc, tag); } 655 #endif 656 } 657 658 /* double check that the value got inserted correctly */ 659 if (pciaddr_ioaddr(pci_conf_read(pc, tag, mapreg)) != *addr) { 660 pci_conf_write(pc, tag, mapreg, 0); /* clear */ 661 printf("%s: fixup failed. (new address=%#x)\n", 662 rct->csc->sc_dev.dv_xname, 663 (unsigned)*addr); 664 return (1); 665 } 666 667 DPRINTF(("new address 0x%08x\n", 668 (unsigned)*addr)); 669 670 return (0); 671 } 672 673 static void 674 ppb_cardbus_attach(parent, self, aux) 675 struct device *parent, *self; 676 void *aux; 677 { 678 struct ppb_cardbus_softc *csc = (struct ppb_cardbus_softc *) self; 679 struct cardbus_softc *parent_sc = 680 (struct cardbus_softc *) csc->sc_dev.dv_parent; 681 struct cardbus_attach_args *ca = aux; 682 cardbus_devfunc_t ct = ca->ca_ct; 683 cardbus_chipset_tag_t cc = ct->ct_cc; 684 cardbus_function_tag_t cf = ct->ct_cf; 685 struct pccbb_softc *psc = (struct pccbb_softc *)cc; 686 struct pcibus_attach_args pba; 687 char devinfo[256]; 688 pcireg_t busdata; 689 int mybus, rv; 690 u_int16_t pciirq; 691 int minbus, maxbus; 692 693 mybus = ct->ct_bus; 694 pciirq = 0; 695 rv = 0; 696 697 /* shut up compiler */ 698 csc->foo=parent_sc->sc_intrline; 699 700 701 pci_devinfo(ca->ca_id, ca->ca_class, 0, devinfo); 702 printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(ca->ca_class)); 703 704 busdata = cardbus_conf_read(cc, cf, ca->ca_tag, PPB_REG_BUSINFO); 705 minbus = pcibios_max_bus; 706 707 if (PPB_BUSINFO_SECONDARY(busdata) == 0) { 708 printf("%s: not configured by system firmware calling pci_bus_fixup(%d)\n", 709 self->dv_xname, 0); 710 711 /* 712 * first, pull the reset wire on the secondary bridge 713 * to clear all devices 714 */ 715 busdata = cardbus_conf_read(cc, cf, ca->ca_tag, 716 PPB_REG_BRIDGECONTROL); 717 cardbus_conf_write(cc, cf, ca->ca_tag, PPB_REG_BRIDGECONTROL, 718 busdata | PPB_BC_SECONDARY_RESET); 719 delay(1); 720 cardbus_conf_write(cc, cf, ca->ca_tag, PPB_REG_BRIDGECONTROL, 721 busdata); 722 723 /* then go initialize the bridge control registers */ 724 maxbus = pci_bus_fixup(psc->sc_pc, 0); 725 } 726 727 busdata = cardbus_conf_read(cc, cf, ca->ca_tag, PPB_REG_BUSINFO); 728 if(PPB_BUSINFO_SECONDARY(busdata) == 0) { 729 printf("%s: still not configured, not fixable.\n", 730 self->dv_xname); 731 return; 732 } 733 734 #if 0 735 minbus = PPB_BUSINFO_SECONDARY(busdata); 736 maxbus = PPB_BUSINFO_SUBORDINATE(busdata); 737 #endif 738 739 /* now, go and assign addresses for the new devices */ 740 rbus_pci_addr_fixup(csc, cc, parent_sc, 741 psc->sc_pc, 742 ca, 743 minbus, maxbus); 744 745 /* 746 * now configure all connected devices to the IRQ which 747 * was assigned to this slot, as they will all arrive from 748 * that IRQ. 749 */ 750 rbus_intr_fixup(psc->sc_pc, minbus, maxbus, ca->ca_intrline); 751 752 /* 753 * enable direct routing of interrupts. We do this because 754 * we can not manage to get pccb_intr_establish() called until 755 * PCI subsystem is merged with rbus. The major thing that this 756 * routine does is avoid calling the driver's interrupt routine 757 * when the card has been removed. 758 * 759 * The rbus_ppb.c can not cope with card desertions until the merging 760 * anyway. 761 */ 762 pccbb_intr_route(psc); 763 764 /* 765 * Attach the PCI bus than hangs off of it. 766 * 767 * XXX Don't pass-through Memory Read Multiple. Should we? 768 * XXX Consult the spec... 769 */ 770 pba.pba_busname = "pci"; 771 pba.pba_iot = ca->ca_iot; 772 pba.pba_memt = ca->ca_memt; 773 pba.pba_dmat = ca->ca_dmat; 774 pba.pba_pc = psc->sc_pc; 775 pba.pba_flags = PCI_FLAGS_IO_ENABLED|PCI_FLAGS_MEM_ENABLED; 776 pba.pba_bus = PPB_BUSINFO_SECONDARY(busdata); 777 /*pba.pba_intrswiz = parent_sc->sc_intrswiz; */ 778 pba.pba_intrtag = psc->sc_pa.pa_intrtag; 779 780 config_found(self, &pba, rppbprint); 781 } 782 783 void 784 ppb_cardbus_setup(struct ppb_softc * sc) 785 { 786 struct ppb_cardbus_softc *csc = (struct ppb_cardbus_softc *) sc; 787 #if 0 788 cardbus_chipset_tag_t cc = psc->sc_cc; 789 cardbus_function_tag_t cf = psc->sc_cf; 790 #endif 791 792 /* shut up compiler */ 793 csc->foo=2; 794 795 printf("ppb_cardbus_setup called\n"); 796 #if 0 797 /* not sure what to do here */ 798 cardbustag_t tag = cardbus_make_tag(cc, cf, csc->ct->ct_bus, 799 csc->ct->ct_dev, csc->ct->ct_func); 800 801 command = Cardbus_conf_read(csc->ct, tag, CARDBUS_COMMAND_STATUS_REG); 802 if (csc->base0_reg) { 803 Cardbus_conf_write(csc->ct, tag, 804 CARDBUS_BASE0_REG, csc->base0_reg); 805 (cf->cardbus_ctrl) (cc, CARDBUS_MEM_ENABLE); 806 command |= CARDBUS_COMMAND_MEM_ENABLE | 807 CARDBUS_COMMAND_MASTER_ENABLE; 808 } else if (csc->base1_reg) { 809 Cardbus_conf_write(csc->ct, tag, 810 CARDBUS_BASE1_REG, csc->base1_reg); 811 (cf->cardbus_ctrl) (cc, CARDBUS_IO_ENABLE); 812 command |= (CARDBUS_COMMAND_IO_ENABLE | 813 CARDBUS_COMMAND_MASTER_ENABLE); 814 } 815 816 (cf->cardbus_ctrl) (cc, CARDBUS_BM_ENABLE); 817 818 /* enable the card */ 819 Cardbus_conf_write(csc->ct, tag, CARDBUS_COMMAND_STATUS_REG, command); 820 #endif 821 } 822 823 int 824 ppb_cardbus_enable(struct ppb_softc * sc) 825 { 826 #if 0 827 struct ppb_cardbus_softc *csc = (struct fxp_cardbus_softc *) sc; 828 struct cardbus_softc *psc = 829 (struct cardbus_softc *) sc->sc_dev.dv_parent; 830 cardbus_chipset_tag_t cc = psc->sc_cc; 831 cardbus_function_tag_t cf = psc->sc_cf; 832 833 Cardbus_function_enable(csc->ct); 834 835 fxp_cardbus_setup(sc); 836 837 /* Map and establish the interrupt. */ 838 839 sc->sc_ih = cardbus_intr_establish(cc, cf, psc->sc_intrline, IPL_NET, 840 fxp_intr, sc); 841 if (NULL == sc->sc_ih) { 842 printf("%s: couldn't establish interrupt\n", 843 sc->sc_dev.dv_xname); 844 return 1; 845 } 846 847 printf("%s: interrupting at %d\n", sc->sc_dev.dv_xname, 848 psc->sc_intrline); 849 850 #endif 851 return 0; 852 } 853 854 void 855 ppb_cardbus_disable(struct ppb_softc * sc) 856 { 857 #if 0 858 struct cardbus_softc *psc = 859 (struct cardbus_softc *) sc->sc_dev.dv_parent; 860 cardbus_chipset_tag_t cc = psc->sc_cc; 861 cardbus_function_tag_t cf = psc->sc_cf; 862 863 /* Remove interrupt handler. */ 864 cardbus_intr_disestablish(cc, cf, sc->sc_ih); 865 866 Cardbus_function_disable(((struct fxp_cardbus_softc *) sc)->ct); 867 #endif 868 } 869 870 static int 871 ppb_cardbus_detach(self, flags) 872 struct device *self; 873 int flags; 874 { 875 /* struct ppb_softc *sc = (struct ppb_softc *) self;*/ 876 struct ppb_cardbus_softc *csc = (struct ppb_cardbus_softc *) self; 877 878 #if 0 879 struct cardbus_devfunc *ct = csc->ct; 880 int rv, reg; 881 882 #ifdef DIAGNOSTIC 883 if (ct == NULL) 884 panic("%s: data structure lacks\n", sc->sc_dev.dv_xname); 885 #endif 886 887 rv = fxp_detach(sc); 888 if (rv == 0) { 889 /* 890 * Unhook the interrupt handler. 891 */ 892 cardbus_intr_disestablish(ct->ct_cc, ct->ct_cf, sc->sc_ih); 893 894 /* 895 * release bus space and close window 896 */ 897 if (csc->base0_reg) 898 reg = CARDBUS_BASE0_REG; 899 else 900 reg = CARDBUS_BASE1_REG; 901 Cardbus_mapreg_unmap(ct, reg, sc->sc_st, sc->sc_sh, csc->size); 902 } 903 return (rv); 904 905 #endif 906 csc->foo=1; 907 return 0; 908 909 } 910 911 int 912 ppb_activate(self, act) 913 struct device *self; 914 enum devact act; 915 { 916 printf("ppb_activate called\n"); 917 return 0; 918 } 919 920
Indexes created Fri Sep 26 20:09:58 GMT 2025