rbus_ppb.c revision 1.19
1 /* $NetBSD: rbus_ppb.c,v 1.19 2006/03/29 06:22:38 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Michael Richardson <mcr (at) sandelman.ottawa.on.ca> 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * CardBus front-end for the Intel/Digital DECchip 21152 PCI-PCI bridge 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: rbus_ppb.c,v 1.19 2006/03/29 06:22:38 thorpej Exp $"); 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/mbuf.h> 49 #include <sys/malloc.h> 50 #include <sys/kernel.h> 51 #include <sys/socket.h> 52 #include <sys/ioctl.h> 53 #include <sys/errno.h> 54 #include <sys/device.h> 55 56 #if NRND > 0 57 #include <sys/rnd.h> 58 #endif 59 60 #include <machine/endian.h> 61 62 #include <machine/bus.h> 63 #include <machine/intr.h> 64 65 #include <dev/pci/pcivar.h> 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcidevs.h> 68 #include <dev/pci/ppbreg.h> 69 70 #include <dev/ic/i82365reg.h> 71 #include <dev/ic/i82365var.h> 72 73 #include <dev/pci/pccbbreg.h> 74 #include <dev/pci/pccbbvar.h> 75 76 #include <dev/cardbus/cardbusvar.h> 77 #include <dev/pci/pcidevs.h> 78 79 #include <i386/pci/pci_addr_fixup.h> 80 #include <i386/pci/pci_bus_fixup.h> 81 #include <i386/pci/pci_intr_fixup.h> 82 #include <i386/pci/pcibios.h> 83 84 struct ppb_softc; 85 86 static int ppb_cardbus_match(struct device *, struct cfdata *, void *); 87 static void ppb_cardbus_attach(struct device *, struct device *, void *); 88 static int ppb_cardbus_detach(struct device * self, int flags); 89 /*static*/ void ppb_cardbus_setup(struct ppb_softc * sc); 90 /*static*/ int ppb_cardbus_enable(struct ppb_softc * sc); 91 /*static*/ void ppb_cardbus_disable(struct ppb_softc * sc); 92 static int ppb_activate(struct device *, enum devact); 93 int rppbprint(void *, const char *); 94 int rbus_intr_fixup(pci_chipset_tag_t, int, int, int); 95 void rbus_do_header_fixup(pci_chipset_tag_t, pcitag_t, void *); 96 97 static void rbus_pci_phys_allocate(pci_chipset_tag_t, pcitag_t, void *); 98 99 static int rbus_do_phys_allocate(pci_chipset_tag_t, pcitag_t, int, 100 void *, int, bus_addr_t *, bus_size_t); 101 102 static void rbus_pci_phys_countspace(pci_chipset_tag_t, pcitag_t, void *); 103 104 static int rbus_do_phys_countspace(pci_chipset_tag_t, pcitag_t, int, 105 void *, int, bus_addr_t *, bus_size_t); 106 107 unsigned int rbus_round_up(unsigned int, unsigned int); 108 109 110 struct ppb_cardbus_softc { 111 struct device sc_dev; 112 pcitag_t sc_tag; 113 int foo; 114 }; 115 116 CFATTACH_DECL(rbus_ppb, sizeof(struct ppb_cardbus_softc), 117 ppb_cardbus_match, ppb_cardbus_attach, ppb_cardbus_detach, ppb_activate); 118 119 #ifdef CBB_DEBUG 120 int rbus_ppb_debug = 0; /* hack with kdb */ 121 #define DPRINTF(X) if(rbus_ppb_debug) printf X 122 #else 123 #define DPRINTF(X) 124 #endif 125 126 static int 127 ppb_cardbus_match(parent, match, aux) 128 struct device *parent; 129 struct cfdata *match; 130 void *aux; 131 { 132 struct cardbus_attach_args *ca = aux; 133 134 if (CARDBUS_VENDOR(ca->ca_id) == PCI_VENDOR_DEC && 135 CARDBUS_PRODUCT(ca->ca_id) == PCI_PRODUCT_DEC_21152) 136 return (1); 137 138 if(PCI_CLASS(ca->ca_class) == PCI_CLASS_BRIDGE && 139 PCI_SUBCLASS(ca->ca_class) == PCI_SUBCLASS_BRIDGE_PCI) { 140 /* XXX */ 141 printf("recognizing generic bridge chip\n"); 142 } 143 144 return (0); 145 } 146 147 148 int 149 rppbprint(aux, pnp) 150 void *aux; 151 const char *pnp; 152 { 153 struct pcibus_attach_args *pba = aux; 154 155 /* only PCIs can attach to PPBs; easy. */ 156 if (pnp) 157 aprint_normal("pci at %s", pnp); 158 aprint_normal(" bus %d (rbus)", pba->pba_bus); 159 return (UNCONF); 160 } 161 162 int 163 rbus_intr_fixup(pci_chipset_tag_t pc, 164 int minbus, 165 int maxbus, 166 int line) 167 { 168 pci_device_foreach_min(pc, minbus, 169 maxbus, rbus_do_header_fixup, (void *)&line); 170 return 0; 171 } 172 173 void 174 rbus_do_header_fixup(pc, tag, context) 175 pci_chipset_tag_t pc; 176 pcitag_t tag; 177 void *context; 178 { 179 int pin, irq; 180 int bus, device, function; 181 pcireg_t intr, id; 182 int *pline = (int *)context; 183 int line = *pline; 184 185 pci_decompose_tag(pc, tag, &bus, &device, &function); 186 id = pci_conf_read(pc, tag, PCI_ID_REG); 187 188 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 189 pin = PCI_INTERRUPT_PIN(intr); 190 irq = PCI_INTERRUPT_LINE(intr); 191 192 #if 0 193 printf("do_header %02x:%02x:%02x pin=%d => line %d\n", 194 bus, device, function, pin, line); 195 #endif 196 197 intr &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT); 198 intr |= (line << PCI_INTERRUPT_LINE_SHIFT); 199 pci_conf_write(pc, tag, PCI_INTERRUPT_REG, intr); 200 201 } 202 203 /* 204 * This function takes a range of PCI bus numbers and 205 * allocates space for all devices found in this space (the BARs) from 206 * the rbus space maps (I/O and memory). 207 * 208 * It assumes that "rbus" is defined. The whole concept does. 209 * 210 * It uses pci_device_foreach_min() to call rbus_pci_phys_allocate. 211 * This function is mostly stolen from 212 * pci_addr_fixup.c:pciaddr_resource_reserve. 213 * 214 */ 215 struct rbus_pci_addr_fixup_context { 216 struct ppb_cardbus_softc *csc; 217 cardbus_chipset_tag_t ct; 218 struct cardbus_softc *sc; 219 struct cardbus_attach_args *caa; 220 int minbus; 221 int maxbus; 222 bus_size_t *bussize_ioreqs; 223 bus_size_t *bussize_memreqs; 224 rbus_tag_t *iobustags; 225 rbus_tag_t *membustags; 226 }; 227 228 unsigned int 229 rbus_round_up(unsigned int size, unsigned int minval) 230 { 231 unsigned int power2; 232 233 if(size == 0) { 234 return 0; 235 } 236 237 power2=minval; 238 239 while(power2 < (1 << 31) && 240 power2 < size) { 241 power2 = power2 << 1; 242 } 243 244 return power2; 245 } 246 247 static void 248 rbus_pci_addr_fixup(struct ppb_cardbus_softc *csc, 249 cardbus_chipset_tag_t ct, 250 struct cardbus_softc *sc, 251 pci_chipset_tag_t pc, 252 struct cardbus_attach_args *caa, 253 int minbus, int maxbus) 254 { 255 struct rbus_pci_addr_fixup_context rct; 256 int size, busnum; 257 bus_addr_t start; 258 bus_space_handle_t handle; 259 u_int32_t reg; 260 261 rct.csc=csc; 262 rct.ct=ct; 263 rct.sc=sc; 264 rct.caa=caa; 265 rct.minbus = minbus; 266 rct.maxbus = maxbus; 267 size = sizeof(bus_size_t)*(maxbus+1); 268 rct.bussize_ioreqs = alloca(size); 269 rct.bussize_memreqs = alloca(size); 270 rct.iobustags = alloca(maxbus * sizeof(rbus_tag_t)); 271 rct.membustags = alloca(maxbus * sizeof(rbus_tag_t)); 272 273 bzero(rct.bussize_ioreqs, size); 274 bzero(rct.bussize_memreqs, size); 275 276 printf("%s: sizing buses %d-%d\n", 277 rct.csc->sc_dev.dv_xname, 278 minbus, maxbus); 279 280 pci_device_foreach_min(pc, minbus, maxbus, 281 rbus_pci_phys_countspace, &rct); 282 283 /* 284 * we need to determine amount of address space for each 285 * bus. To do this, we have to roll up amounts and then 286 * we need to divide up the cardbus's extent to allocate 287 * some space to each bus. 288 */ 289 290 for(busnum=maxbus; busnum > minbus; busnum--) { 291 if(pci_bus_parent[busnum] != 0) { 292 if(pci_bus_parent[busnum] < minbus || 293 pci_bus_parent[busnum] >= maxbus) { 294 printf("%s: bus %d has illegal parent %d\n", 295 rct.csc->sc_dev.dv_xname, 296 busnum, pci_bus_parent[busnum]); 297 continue; 298 } 299 300 /* first round amount of space up */ 301 rct.bussize_ioreqs[busnum] = 302 rbus_round_up(rct.bussize_ioreqs[busnum], PPB_IO_MIN); 303 rct.bussize_ioreqs[pci_bus_parent[busnum]] += 304 rct.bussize_ioreqs[busnum]; 305 306 rct.bussize_memreqs[busnum] = 307 rbus_round_up(rct.bussize_memreqs[busnum], PPB_MEM_MIN); 308 rct.bussize_memreqs[pci_bus_parent[busnum]] += 309 rct.bussize_memreqs[busnum]; 310 311 } 312 } 313 314 rct.bussize_ioreqs[minbus] = 315 rbus_round_up(rct.bussize_ioreqs[minbus], 4096); 316 rct.bussize_memreqs[minbus] = 317 rbus_round_up(rct.bussize_memreqs[minbus], 8); 318 319 printf("%s: total needs IO %08lx and MEM %08lx\n", 320 rct.csc->sc_dev.dv_xname, 321 rct.bussize_ioreqs[minbus], rct.bussize_memreqs[minbus]); 322 323 if(!caa->ca_rbus_iot) { 324 panic("no iot bus"); 325 } 326 327 if(rct.bussize_ioreqs[minbus]) { 328 if(rbus_space_alloc(caa->ca_rbus_iot, 0, 329 rct.bussize_ioreqs[minbus], 330 rct.bussize_ioreqs[minbus]-1 /* mask */, 331 rct.bussize_ioreqs[minbus] /* align */, 332 /* flags */ 0, 333 &start, 334 &handle) != 0) { 335 panic("rbus_ppb: can not allocate %ld bytes in IO bus %d", 336 rct.bussize_ioreqs[minbus], minbus); 337 } 338 rct.iobustags[minbus]=rbus_new(caa->ca_rbus_iot, 339 start, 340 rct.bussize_ioreqs[minbus], 341 0 /* offset to add to physical address 342 to make processor address */, 343 RBUS_SPACE_DEDICATE); 344 } 345 346 if(rct.bussize_memreqs[minbus]) { 347 if(rbus_space_alloc(caa->ca_rbus_memt, 0, 348 rct.bussize_memreqs[minbus], 349 rct.bussize_memreqs[minbus]-1 /* mask */, 350 rct.bussize_memreqs[minbus] /* align */, 351 /* flags */ 0, 352 &start, 353 &handle) != 0) { 354 panic("%s: can not allocate %ld bytes in MEM bus %d", 355 rct.csc->sc_dev.dv_xname, 356 rct.bussize_memreqs[minbus], minbus); 357 } 358 rct.membustags[minbus]=rbus_new(caa->ca_rbus_memt, 359 start, 360 rct.bussize_memreqs[minbus], 361 0 /* offset to add to physical 362 address to make processor 363 address */, 364 RBUS_SPACE_DEDICATE); 365 } 366 367 for(busnum=minbus+1; busnum <= maxbus; busnum++) { 368 int busparent; 369 370 busparent = pci_bus_parent[busnum]; 371 372 printf("%s: bus %d (parent=%d) needs IO %08lx and MEM %08lx\n", 373 rct.csc->sc_dev.dv_xname, 374 busnum, 375 busparent, 376 rct.bussize_ioreqs[busnum], 377 rct.bussize_memreqs[busnum]); 378 379 if(busparent > maxbus) { 380 panic("rbus_ppb: illegal parent"); 381 } 382 383 if(rct.bussize_ioreqs[busnum]) { 384 if(rbus_space_alloc(rct.iobustags[busparent], 385 0, 386 rct.bussize_ioreqs[busnum], 387 rct.bussize_ioreqs[busnum]-1 /*mask */, 388 rct.bussize_ioreqs[busnum] /* align */, 389 /* flags */ 0, 390 &start, 391 &handle) != 0) { 392 panic("rbus_ppb: can not allocate %ld bytes in IO bus %d", 393 rct.bussize_ioreqs[busnum], busnum); 394 } 395 rct.iobustags[busnum]=rbus_new(rct.iobustags[busparent], 396 start, 397 rct.bussize_ioreqs[busnum], 398 0 /* offset to add to physical 399 address 400 to make processor address */, 401 RBUS_SPACE_DEDICATE); 402 403 /* program the bridge */ 404 405 /* enable I/O space */ 406 reg = pci_conf_read(pc, pci_bus_tag[busnum], 407 PCI_COMMAND_STATUS_REG); 408 reg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE; 409 pci_conf_write(pc, pci_bus_tag[busnum], 410 PCI_COMMAND_STATUS_REG, reg); 411 412 /* now init the limit register for I/O */ 413 pci_conf_write(pc, pci_bus_tag[busnum], PPB_REG_IOSTATUS, 414 (((start & 0xf000) >> 8) << PPB_IOBASE_SHIFT) | 415 ((((start + 416 rct.bussize_ioreqs[busnum] + 417 4095) & 0xf000) >> 8) << PPB_IOLIMIT_SHIFT)); 418 } 419 420 if(rct.bussize_memreqs[busnum]) { 421 if(rbus_space_alloc(rct.membustags[busparent], 422 0, 423 rct.bussize_memreqs[busnum] /* size */, 424 rct.bussize_memreqs[busnum]-1 /*mask */, 425 rct.bussize_memreqs[busnum] /* align */, 426 /* flags */ 0, 427 &start, 428 &handle) != 0) { 429 panic("rbus_ppb: can not allocate %ld bytes in MEM bus %d", 430 rct.bussize_memreqs[busnum], busnum); 431 } 432 rct.membustags[busnum]=rbus_new(rct.membustags[busparent], 433 start, 434 rct.bussize_memreqs[busnum], 435 0 /* offset to add to physical 436 address to make processor 437 address */, 438 RBUS_SPACE_DEDICATE); 439 440 /* program the bridge */ 441 /* enable memory space */ 442 reg = pci_conf_read(pc, pci_bus_tag[busnum], 443 PCI_COMMAND_STATUS_REG); 444 reg |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 445 pci_conf_write(pc, pci_bus_tag[busnum], 446 PCI_COMMAND_STATUS_REG, reg); 447 448 /* now init the limit register for memory */ 449 pci_conf_write(pc, pci_bus_tag[busnum], PPB_REG_MEM, 450 ((start & PPB_MEM_MASK) 451 >> PPB_MEM_SHIFT) << PPB_MEMBASE_SHIFT | 452 (((start + 453 rct.bussize_memreqs[busnum] + 454 PPB_MEM_MIN-1) >> PPB_MEM_SHIFT) 455 << PPB_MEMLIMIT_SHIFT)); 456 457 /* and set the prefetchable limits as well */ 458 pci_conf_write(pc, pci_bus_tag[busnum], PPB_REG_PREFMEM, 459 ((start & PPB_MEM_MASK) 460 >> PPB_MEM_SHIFT) << PPB_MEMBASE_SHIFT | 461 (((start + 462 rct.bussize_memreqs[busnum] + 463 PPB_MEM_MIN-1) >> PPB_MEM_SHIFT) 464 << PPB_MEMLIMIT_SHIFT)); 465 466 /* pci_conf_print(pc, pci_bus_tag[busnum], NULL); */ 467 } 468 } 469 470 printf("%s: configuring buses %d-%d\n", 471 rct.csc->sc_dev.dv_xname, 472 minbus, maxbus); 473 pci_device_foreach_min(pc, minbus, maxbus, 474 rbus_pci_phys_allocate, &rct); 475 } 476 477 static void 478 rbus_pci_phys_countspace(pc, tag, context) 479 pci_chipset_tag_t pc; 480 pcitag_t tag; 481 void *context; 482 { 483 int bus, device, function; 484 struct rbus_pci_addr_fixup_context *rct = 485 (struct rbus_pci_addr_fixup_context *)context; 486 487 pci_decompose_tag(pc, tag, &bus, &device, &function); 488 489 printf("%s: configuring device %02x:%02x:%02x\n", 490 rct->csc->sc_dev.dv_xname, 491 bus, device, function); 492 493 pciaddr_resource_manage(pc, tag, 494 rbus_do_phys_countspace, context); 495 } 496 497 498 int 499 rbus_do_phys_countspace(pc, tag, mapreg, ctx, type, addr, size) 500 pci_chipset_tag_t pc; 501 pcitag_t tag; 502 void *ctx; 503 int mapreg, type; 504 bus_addr_t *addr; 505 bus_size_t size; 506 { 507 struct rbus_pci_addr_fixup_context *rct = 508 (struct rbus_pci_addr_fixup_context *)ctx; 509 int bus, device, function; 510 511 pci_decompose_tag(pc, tag, &bus, &device, &function); 512 513 if(size > (1<<24)) { 514 printf("%s: skipping huge space request of size=%08x\n", 515 rct->csc->sc_dev.dv_xname, (unsigned int)size); 516 return 0; 517 } 518 519 if(PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_IO) { 520 rct->bussize_ioreqs[bus] += size; 521 } else { 522 rct->bussize_memreqs[bus]+= size; 523 } 524 525 return 0; 526 } 527 528 static void 529 rbus_pci_phys_allocate(pc, tag, context) 530 pci_chipset_tag_t pc; 531 pcitag_t tag; 532 void *context; 533 { 534 int bus, device, function, command; 535 struct rbus_pci_addr_fixup_context *rct = 536 (struct rbus_pci_addr_fixup_context *)context; 537 //cardbus_chipset_tag_t ct = rct->ct; 538 // struct cardbus_softc *sc = rct->sc; 539 540 pci_decompose_tag(pc, tag, &bus, &device, &function); 541 542 printf("%s: configuring device %02x:%02x:%02x\n", 543 rct->csc->sc_dev.dv_xname, 544 bus, device, function); 545 546 pciaddr_resource_manage(pc, tag, 547 rbus_do_phys_allocate, context); 548 549 /* now turn the device's memory and I/O on */ 550 command = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 551 command |= PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE; 552 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, command); 553 } 554 555 int 556 rbus_do_phys_allocate(pc, tag, mapreg, ctx, type, addr, size) 557 pci_chipset_tag_t pc; 558 pcitag_t tag; 559 void *ctx; 560 int mapreg, type; 561 bus_addr_t *addr; 562 bus_size_t size; 563 { 564 struct rbus_pci_addr_fixup_context *rct = 565 (struct rbus_pci_addr_fixup_context *)ctx; 566 cardbus_chipset_tag_t ct = rct->ct; 567 struct cardbus_softc *sc = rct->sc; 568 cardbus_function_t *cf = sc->sc_cf; 569 rbus_tag_t rbustag; 570 bus_space_tag_t bustag; 571 bus_addr_t mask = size -1; 572 bus_addr_t base = 0; 573 bus_space_handle_t handle; 574 int busflags = 0; 575 int flags = 0; 576 const char *bustype; 577 int bus, device, function; 578 579 pci_decompose_tag(pc, tag, &bus, &device, &function); 580 581 /* 582 * some devices come up with garbage in them (Tulip?) 583 * we are in charge here, so give them address 584 * space anyway. 585 * 586 * XXX this may be due to no secondary PCI reset!!! 587 */ 588 #if 0 589 if (*addr) { 590 printf("Already allocated space at %08x\n", 591 (unsigned int)*addr); 592 return (0); 593 } 594 #endif 595 596 if(size > (1<<24)) { 597 printf("%s: skipping huge space request of size=%08x\n", 598 rct->csc->sc_dev.dv_xname, (unsigned int)size); 599 return 0; 600 } 601 602 if(PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_IO) { 603 bustag = sc->sc_iot; 604 rbustag = rct->iobustags[bus]; 605 bustype = "io"; 606 } else { 607 bustag = sc->sc_memt; 608 rbustag = rct->membustags[bus]; 609 bustype = "mem"; 610 } 611 612 if((*cf->cardbus_space_alloc)(ct, rbustag, base, size, 613 mask, size, busflags|flags, 614 addr, &handle)) { 615 printf("%s: no available resources (size=%08x) for bar %2d. fixup failed\n", 616 rct->csc->sc_dev.dv_xname, (unsigned int)size, mapreg); 617 618 *addr = 0; 619 pci_conf_write(pc, tag, mapreg, *addr); 620 return (1); 621 } 622 623 printf("%s: alloc %s space of size %08x for %02d:%02d:%02d -> %08x\n", 624 rct->csc->sc_dev.dv_xname, 625 bustype, 626 (unsigned int)size, 627 bus, device, function, (unsigned int)*addr); 628 629 /* write new address to PCI device configuration header */ 630 pci_conf_write(pc, tag, mapreg, *addr); 631 632 /* check */ 633 { 634 DPRINTF(("%s: pci_addr_fixup: ", 635 rct->csc->sc_dev.dv_xname)); 636 #ifdef CBB_DEBUG 637 if(rbus_ppb_debug) { pciaddr_print_devid(pc, tag); } 638 #endif 639 } 640 641 /* double check that the value got inserted correctly */ 642 if (pciaddr_ioaddr(pci_conf_read(pc, tag, mapreg)) != *addr) { 643 pci_conf_write(pc, tag, mapreg, 0); /* clear */ 644 printf("%s: fixup failed. (new address=%#x)\n", 645 rct->csc->sc_dev.dv_xname, 646 (unsigned)*addr); 647 return (1); 648 } 649 650 DPRINTF(("new address 0x%08x\n", 651 (unsigned)*addr)); 652 653 return (0); 654 } 655 656 static void 657 ppb_cardbus_attach(parent, self, aux) 658 struct device *parent, *self; 659 void *aux; 660 { 661 struct ppb_cardbus_softc *csc = device_private(self); 662 struct cardbus_softc *parent_sc = 663 device_private(device_parent(&csc->sc_dev)); 664 struct cardbus_attach_args *ca = aux; 665 cardbus_devfunc_t ct = ca->ca_ct; 666 cardbus_chipset_tag_t cc = ct->ct_cc; 667 cardbus_function_tag_t cf = ct->ct_cf; 668 struct pccbb_softc *psc = (struct pccbb_softc *)cc; 669 struct pcibus_attach_args pba; 670 char devinfo[256]; 671 pcireg_t busdata; 672 int mybus, rv; 673 u_int16_t pciirq; 674 int minbus, maxbus; 675 676 mybus = ct->ct_bus; 677 pciirq = 0; 678 rv = 0; 679 680 /* shut up compiler */ 681 csc->foo=parent_sc->sc_intrline; 682 683 684 pci_devinfo(ca->ca_id, ca->ca_class, 0, devinfo, sizeof(devinfo)); 685 printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(ca->ca_class)); 686 687 csc->sc_tag = ca->ca_tag; /* XXX cardbustag_t == pcitag_t */ 688 689 busdata = cardbus_conf_read(cc, cf, ca->ca_tag, PPB_REG_BUSINFO); 690 minbus = pcibios_max_bus; 691 maxbus = minbus; /* XXX; gcc */ 692 693 if (PPB_BUSINFO_SECONDARY(busdata) == 0) { 694 printf("%s: not configured by system firmware calling pci_bus_fixup(%d)\n", 695 self->dv_xname, 0); 696 697 /* 698 * first, pull the reset wire on the secondary bridge 699 * to clear all devices 700 */ 701 busdata = cardbus_conf_read(cc, cf, ca->ca_tag, 702 PPB_REG_BRIDGECONTROL); 703 cardbus_conf_write(cc, cf, ca->ca_tag, PPB_REG_BRIDGECONTROL, 704 busdata | PPB_BC_SECONDARY_RESET); 705 delay(1); 706 cardbus_conf_write(cc, cf, ca->ca_tag, PPB_REG_BRIDGECONTROL, 707 busdata); 708 709 /* then go initialize the bridge control registers */ 710 maxbus = pci_bus_fixup(psc->sc_pc, 0); 711 } 712 713 busdata = cardbus_conf_read(cc, cf, ca->ca_tag, PPB_REG_BUSINFO); 714 if(PPB_BUSINFO_SECONDARY(busdata) == 0) { 715 printf("%s: still not configured, not fixable.\n", 716 self->dv_xname); 717 return; 718 } 719 720 #if 0 721 minbus = PPB_BUSINFO_SECONDARY(busdata); 722 maxbus = PPB_BUSINFO_SUBORDINATE(busdata); 723 #endif 724 725 /* now, go and assign addresses for the new devices */ 726 rbus_pci_addr_fixup(csc, cc, parent_sc, 727 psc->sc_pc, 728 ca, 729 minbus, maxbus); 730 731 /* 732 * now configure all connected devices to the IRQ which 733 * was assigned to this slot, as they will all arrive from 734 * that IRQ. 735 */ 736 rbus_intr_fixup(psc->sc_pc, minbus, maxbus, ca->ca_intrline); 737 738 /* 739 * enable direct routing of interrupts. We do this because 740 * we can not manage to get pccb_intr_establish() called until 741 * PCI subsystem is merged with rbus. The major thing that this 742 * routine does is avoid calling the driver's interrupt routine 743 * when the card has been removed. 744 * 745 * The rbus_ppb.c can not cope with card desertions until the merging 746 * anyway. 747 */ 748 pccbb_intr_route(psc); 749 750 /* 751 * Attach the PCI bus than hangs off of it. 752 * 753 * XXX Don't pass-through Memory Read Multiple. Should we? 754 * XXX Consult the spec... 755 */ 756 pba.pba_iot = ca->ca_iot; 757 pba.pba_memt = ca->ca_memt; 758 pba.pba_dmat = ca->ca_dmat; 759 pba.pba_pc = psc->sc_pc; 760 pba.pba_flags = PCI_FLAGS_IO_ENABLED|PCI_FLAGS_MEM_ENABLED; 761 pba.pba_bus = PPB_BUSINFO_SECONDARY(busdata); 762 pba.pba_bridgetag = &csc->sc_tag; 763 /*pba.pba_intrswiz = parent_sc->sc_intrswiz; */ 764 pba.pba_intrtag = psc->sc_pa.pa_intrtag; 765 766 config_found_ia(self, "pcibus", &pba, rppbprint); 767 } 768 769 void 770 ppb_cardbus_setup(struct ppb_softc * sc) 771 { 772 struct ppb_cardbus_softc *csc = (struct ppb_cardbus_softc *) sc; 773 #if 0 774 cardbus_chipset_tag_t cc = psc->sc_cc; 775 cardbus_function_tag_t cf = psc->sc_cf; 776 #endif 777 778 /* shut up compiler */ 779 csc->foo=2; 780 781 printf("ppb_cardbus_setup called\n"); 782 #if 0 783 /* not sure what to do here */ 784 cardbustag_t tag = cardbus_make_tag(cc, cf, csc->ct->ct_bus, 785 csc->ct->ct_dev, csc->ct->ct_func); 786 787 command = Cardbus_conf_read(csc->ct, tag, CARDBUS_COMMAND_STATUS_REG); 788 if (csc->base0_reg) { 789 Cardbus_conf_write(csc->ct, tag, 790 CARDBUS_BASE0_REG, csc->base0_reg); 791 (cf->cardbus_ctrl) (cc, CARDBUS_MEM_ENABLE); 792 command |= CARDBUS_COMMAND_MEM_ENABLE | 793 CARDBUS_COMMAND_MASTER_ENABLE; 794 } else if (csc->base1_reg) { 795 Cardbus_conf_write(csc->ct, tag, 796 CARDBUS_BASE1_REG, csc->base1_reg); 797 (cf->cardbus_ctrl) (cc, CARDBUS_IO_ENABLE); 798 command |= (CARDBUS_COMMAND_IO_ENABLE | 799 CARDBUS_COMMAND_MASTER_ENABLE); 800 } 801 802 (cf->cardbus_ctrl) (cc, CARDBUS_BM_ENABLE); 803 804 /* enable the card */ 805 Cardbus_conf_write(csc->ct, tag, CARDBUS_COMMAND_STATUS_REG, command); 806 #endif 807 } 808 809 int 810 ppb_cardbus_enable(struct ppb_softc * sc) 811 { 812 #if 0 813 struct ppb_cardbus_softc *csc = (struct fxp_cardbus_softc *) sc; 814 struct cardbus_softc *psc = 815 (struct cardbus_softc *) device_parent(&sc->sc_dev); 816 cardbus_chipset_tag_t cc = psc->sc_cc; 817 cardbus_function_tag_t cf = psc->sc_cf; 818 819 Cardbus_function_enable(csc->ct); 820 821 fxp_cardbus_setup(sc); 822 823 /* Map and establish the interrupt. */ 824 825 sc->sc_ih = cardbus_intr_establish(cc, cf, psc->sc_intrline, IPL_NET, 826 fxp_intr, sc); 827 if (NULL == sc->sc_ih) { 828 printf("%s: couldn't establish interrupt\n", 829 sc->sc_dev.dv_xname); 830 return 1; 831 } 832 833 printf("%s: interrupting at %d\n", sc->sc_dev.dv_xname, 834 psc->sc_intrline); 835 836 #endif 837 return 0; 838 } 839 840 void 841 ppb_cardbus_disable(struct ppb_softc * sc) 842 { 843 #if 0 844 struct cardbus_softc *psc = 845 (struct cardbus_softc *) device_parent(&sc->sc_dev); 846 cardbus_chipset_tag_t cc = psc->sc_cc; 847 cardbus_function_tag_t cf = psc->sc_cf; 848 849 /* Remove interrupt handler. */ 850 cardbus_intr_disestablish(cc, cf, sc->sc_ih); 851 852 Cardbus_function_disable(((struct fxp_cardbus_softc *) sc)->ct); 853 #endif 854 } 855 856 static int 857 ppb_cardbus_detach(self, flags) 858 struct device *self; 859 int flags; 860 { 861 /* struct ppb_softc *sc = device_private(self);*/ 862 struct ppb_cardbus_softc *csc = device_private(self); 863 864 #if 0 865 struct cardbus_devfunc *ct = csc->ct; 866 int rv, reg; 867 868 #ifdef DIAGNOSTIC 869 if (ct == NULL) 870 panic("%s: data structure lacks", sc->sc_dev.dv_xname); 871 #endif 872 873 rv = fxp_detach(sc); 874 if (rv == 0) { 875 /* 876 * Unhook the interrupt handler. 877 */ 878 cardbus_intr_disestablish(ct->ct_cc, ct->ct_cf, sc->sc_ih); 879 880 /* 881 * release bus space and close window 882 */ 883 if (csc->base0_reg) 884 reg = CARDBUS_BASE0_REG; 885 else 886 reg = CARDBUS_BASE1_REG; 887 Cardbus_mapreg_unmap(ct, reg, sc->sc_st, sc->sc_sh, csc->size); 888 } 889 return (rv); 890 891 #endif 892 csc->foo=1; 893 return 0; 894 895 } 896 897 int 898 ppb_activate(self, act) 899 struct device *self; 900 enum devact act; 901 { 902 printf("ppb_activate called\n"); 903 return 0; 904 } 905 906
Indexes created Sun Sep 28 07:09:56 GMT 2025