rbus_ppb.c revision 1.23
1 /* $NetBSD: rbus_ppb.c,v 1.23 2008/05/18 02:06:14 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Michael Richardson <mcr (at) sandelman.ottawa.on.ca> 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * CardBus front-end for the Intel/Digital DECchip 21152 PCI-PCI bridge 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: rbus_ppb.c,v 1.23 2008/05/18 02:06:14 jmcneill Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/mbuf.h> 42 #include <sys/malloc.h> 43 #include <sys/kernel.h> 44 #include <sys/socket.h> 45 #include <sys/ioctl.h> 46 #include <sys/errno.h> 47 #include <sys/device.h> 48 49 #if NRND > 0 50 #include <sys/rnd.h> 51 #endif 52 53 #include <machine/endian.h> 54 55 #include <sys/bus.h> 56 #include <sys/intr.h> 57 58 #include <dev/pci/pcivar.h> 59 #include <dev/pci/pcireg.h> 60 #include <dev/pci/pcidevs.h> 61 #include <dev/pci/ppbreg.h> 62 63 #include <dev/ic/i82365reg.h> 64 #include <dev/ic/i82365var.h> 65 66 #include <dev/pci/pccbbreg.h> 67 #include <dev/pci/pccbbvar.h> 68 69 #include <dev/cardbus/cardbusvar.h> 70 #include <dev/pci/pcidevs.h> 71 72 #include <x86/pci/pci_addr_fixup.h> 73 #include <x86/pci/pci_bus_fixup.h> 74 #include <i386/pci/pci_intr_fixup.h> 75 #include <i386/pci/pcibios.h> 76 77 struct ppb_softc; 78 79 static int ppb_cardbus_match(struct device *, struct cfdata *, void *); 80 static void ppb_cardbus_attach(struct device *, struct device *, void *); 81 static int ppb_cardbus_detach(struct device * self, int flags); 82 /*static*/ void ppb_cardbus_setup(struct ppb_softc * sc); 83 /*static*/ int ppb_cardbus_enable(struct ppb_softc * sc); 84 /*static*/ void ppb_cardbus_disable(struct ppb_softc * sc); 85 static int ppb_activate(struct device *, enum devact); 86 int rppbprint(void *, const char *); 87 int rbus_intr_fixup(pci_chipset_tag_t, int, int, int); 88 void rbus_do_header_fixup(pci_chipset_tag_t, pcitag_t, void *); 89 90 static void rbus_pci_phys_allocate(pci_chipset_tag_t, pcitag_t, void *); 91 92 static int rbus_do_phys_allocate(pci_chipset_tag_t, pcitag_t, int, 93 void *, int, bus_addr_t *, bus_size_t); 94 95 static void rbus_pci_phys_countspace(pci_chipset_tag_t, pcitag_t, void *); 96 97 static int rbus_do_phys_countspace(pci_chipset_tag_t, pcitag_t, int, 98 void *, int, bus_addr_t *, bus_size_t); 99 100 unsigned int rbus_round_up(unsigned int, unsigned int); 101 102 103 struct ppb_cardbus_softc { 104 struct device sc_dev; 105 pcitag_t sc_tag; 106 int foo; 107 }; 108 109 CFATTACH_DECL(rbus_ppb, sizeof(struct ppb_cardbus_softc), 110 ppb_cardbus_match, ppb_cardbus_attach, ppb_cardbus_detach, ppb_activate); 111 112 #ifdef CBB_DEBUG 113 int rbus_ppb_debug = 0; /* hack with kdb */ 114 #define DPRINTF(X) if(rbus_ppb_debug) printf X 115 #else 116 #define DPRINTF(X) 117 #endif 118 119 static int 120 ppb_cardbus_match(parent, match, aux) 121 struct device *parent; 122 struct cfdata *match; 123 void *aux; 124 { 125 struct cardbus_attach_args *ca = aux; 126 127 if (CARDBUS_VENDOR(ca->ca_id) == PCI_VENDOR_DEC && 128 CARDBUS_PRODUCT(ca->ca_id) == PCI_PRODUCT_DEC_21152) 129 return (1); 130 131 if(PCI_CLASS(ca->ca_class) == PCI_CLASS_BRIDGE && 132 PCI_SUBCLASS(ca->ca_class) == PCI_SUBCLASS_BRIDGE_PCI) { 133 /* XXX */ 134 printf("recognizing generic bridge chip\n"); 135 } 136 137 return (0); 138 } 139 140 141 int 142 rppbprint(aux, pnp) 143 void *aux; 144 const char *pnp; 145 { 146 struct pcibus_attach_args *pba = aux; 147 148 /* only PCIs can attach to PPBs; easy. */ 149 if (pnp) 150 aprint_normal("pci at %s", pnp); 151 aprint_normal(" bus %d (rbus)", pba->pba_bus); 152 return (UNCONF); 153 } 154 155 int 156 rbus_intr_fixup(pci_chipset_tag_t pc, 157 int minbus, 158 int maxbus, 159 int line) 160 { 161 pci_device_foreach_min(pc, minbus, 162 maxbus, rbus_do_header_fixup, (void *)&line); 163 return 0; 164 } 165 166 void 167 rbus_do_header_fixup(pc, tag, context) 168 pci_chipset_tag_t pc; 169 pcitag_t tag; 170 void *context; 171 { 172 int pin, irq; 173 int bus, device, function; 174 pcireg_t intr, id; 175 int *pline = (int *)context; 176 int line = *pline; 177 178 pci_decompose_tag(pc, tag, &bus, &device, &function); 179 id = pci_conf_read(pc, tag, PCI_ID_REG); 180 181 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 182 pin = PCI_INTERRUPT_PIN(intr); 183 irq = PCI_INTERRUPT_LINE(intr); 184 185 #if 0 186 printf("do_header %02x:%02x:%02x pin=%d => line %d\n", 187 bus, device, function, pin, line); 188 #endif 189 190 intr &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT); 191 intr |= (line << PCI_INTERRUPT_LINE_SHIFT); 192 pci_conf_write(pc, tag, PCI_INTERRUPT_REG, intr); 193 194 } 195 196 /* 197 * This function takes a range of PCI bus numbers and 198 * allocates space for all devices found in this space (the BARs) from 199 * the rbus space maps (I/O and memory). 200 * 201 * It assumes that "rbus" is defined. The whole concept does. 202 * 203 * It uses pci_device_foreach_min() to call rbus_pci_phys_allocate. 204 * This function is mostly stolen from 205 * pci_addr_fixup.c:pciaddr_resource_reserve. 206 * 207 */ 208 struct rbus_pci_addr_fixup_context { 209 struct ppb_cardbus_softc *csc; 210 cardbus_chipset_tag_t ct; 211 struct cardbus_softc *sc; 212 struct cardbus_attach_args *caa; 213 int minbus; 214 int maxbus; 215 bus_size_t *bussize_ioreqs; 216 bus_size_t *bussize_memreqs; 217 rbus_tag_t *iobustags; 218 rbus_tag_t *membustags; 219 }; 220 221 unsigned int 222 rbus_round_up(unsigned int size, unsigned int minval) 223 { 224 unsigned int power2; 225 226 if(size == 0) { 227 return 0; 228 } 229 230 power2=minval; 231 232 while(power2 < (1 << 31) && 233 power2 < size) { 234 power2 = power2 << 1; 235 } 236 237 return power2; 238 } 239 240 static void 241 rbus_pci_addr_fixup(struct ppb_cardbus_softc *csc, 242 cardbus_chipset_tag_t ct, 243 struct cardbus_softc *sc, 244 pci_chipset_tag_t pc, 245 struct cardbus_attach_args *caa, 246 int minbus, int maxbus) 247 { 248 struct rbus_pci_addr_fixup_context rct; 249 int size, busnum; 250 bus_addr_t start; 251 bus_space_handle_t handle; 252 u_int32_t reg; 253 254 rct.csc=csc; 255 rct.ct=ct; 256 rct.sc=sc; 257 rct.caa=caa; 258 rct.minbus = minbus; 259 rct.maxbus = maxbus; 260 size = sizeof(bus_size_t)*(maxbus+1); 261 rct.bussize_ioreqs = alloca(size); 262 rct.bussize_memreqs = alloca(size); 263 rct.iobustags = alloca(maxbus * sizeof(rbus_tag_t)); 264 rct.membustags = alloca(maxbus * sizeof(rbus_tag_t)); 265 266 bzero(rct.bussize_ioreqs, size); 267 bzero(rct.bussize_memreqs, size); 268 269 printf("%s: sizing buses %d-%d\n", 270 device_xname(&rct.csc->sc_dev), 271 minbus, maxbus); 272 273 pci_device_foreach_min(pc, minbus, maxbus, 274 rbus_pci_phys_countspace, &rct); 275 276 /* 277 * we need to determine amount of address space for each 278 * bus. To do this, we have to roll up amounts and then 279 * we need to divide up the cardbus's extent to allocate 280 * some space to each bus. 281 */ 282 283 for(busnum=maxbus; busnum > minbus; busnum--) { 284 if(pci_bus_parent[busnum] != 0) { 285 if(pci_bus_parent[busnum] < minbus || 286 pci_bus_parent[busnum] >= maxbus) { 287 printf("%s: bus %d has illegal parent %d\n", 288 device_xname(&rct.csc->sc_dev), 289 busnum, pci_bus_parent[busnum]); 290 continue; 291 } 292 293 /* first round amount of space up */ 294 rct.bussize_ioreqs[busnum] = 295 rbus_round_up(rct.bussize_ioreqs[busnum], PPB_IO_MIN); 296 rct.bussize_ioreqs[pci_bus_parent[busnum]] += 297 rct.bussize_ioreqs[busnum]; 298 299 rct.bussize_memreqs[busnum] = 300 rbus_round_up(rct.bussize_memreqs[busnum], PPB_MEM_MIN); 301 rct.bussize_memreqs[pci_bus_parent[busnum]] += 302 rct.bussize_memreqs[busnum]; 303 304 } 305 } 306 307 rct.bussize_ioreqs[minbus] = 308 rbus_round_up(rct.bussize_ioreqs[minbus], 4096); 309 rct.bussize_memreqs[minbus] = 310 rbus_round_up(rct.bussize_memreqs[minbus], 8); 311 312 printf("%s: total needs IO %08lx and MEM %08lx\n", 313 device_xname(&rct.csc->sc_dev), 314 rct.bussize_ioreqs[minbus], rct.bussize_memreqs[minbus]); 315 316 if(!caa->ca_rbus_iot) { 317 panic("no iot bus"); 318 } 319 320 if(rct.bussize_ioreqs[minbus]) { 321 if(rbus_space_alloc(caa->ca_rbus_iot, 0, 322 rct.bussize_ioreqs[minbus], 323 rct.bussize_ioreqs[minbus]-1 /* mask */, 324 rct.bussize_ioreqs[minbus] /* align */, 325 /* flags */ 0, 326 &start, 327 &handle) != 0) { 328 panic("rbus_ppb: can not allocate %ld bytes in IO bus %d", 329 rct.bussize_ioreqs[minbus], minbus); 330 } 331 rct.iobustags[minbus]=rbus_new(caa->ca_rbus_iot, 332 start, 333 rct.bussize_ioreqs[minbus], 334 0 /* offset to add to physical address 335 to make processor address */, 336 RBUS_SPACE_DEDICATE); 337 } 338 339 if(rct.bussize_memreqs[minbus]) { 340 if(rbus_space_alloc(caa->ca_rbus_memt, 0, 341 rct.bussize_memreqs[minbus], 342 rct.bussize_memreqs[minbus]-1 /* mask */, 343 rct.bussize_memreqs[minbus] /* align */, 344 /* flags */ 0, 345 &start, 346 &handle) != 0) { 347 panic("%s: can not allocate %ld bytes in MEM bus %d", 348 device_xname(&rct.csc->sc_dev), 349 rct.bussize_memreqs[minbus], minbus); 350 } 351 rct.membustags[minbus]=rbus_new(caa->ca_rbus_memt, 352 start, 353 rct.bussize_memreqs[minbus], 354 0 /* offset to add to physical 355 address to make processor 356 address */, 357 RBUS_SPACE_DEDICATE); 358 } 359 360 for(busnum=minbus+1; busnum <= maxbus; busnum++) { 361 int busparent; 362 363 busparent = pci_bus_parent[busnum]; 364 365 printf("%s: bus %d (parent=%d) needs IO %08lx and MEM %08lx\n", 366 device_xname(&rct.csc->sc_dev), 367 busnum, 368 busparent, 369 rct.bussize_ioreqs[busnum], 370 rct.bussize_memreqs[busnum]); 371 372 if(busparent > maxbus) { 373 panic("rbus_ppb: illegal parent"); 374 } 375 376 if(rct.bussize_ioreqs[busnum]) { 377 if(rbus_space_alloc(rct.iobustags[busparent], 378 0, 379 rct.bussize_ioreqs[busnum], 380 rct.bussize_ioreqs[busnum]-1 /*mask */, 381 rct.bussize_ioreqs[busnum] /* align */, 382 /* flags */ 0, 383 &start, 384 &handle) != 0) { 385 panic("rbus_ppb: can not allocate %ld bytes in IO bus %d", 386 rct.bussize_ioreqs[busnum], busnum); 387 } 388 rct.iobustags[busnum]=rbus_new(rct.iobustags[busparent], 389 start, 390 rct.bussize_ioreqs[busnum], 391 0 /* offset to add to physical 392 address 393 to make processor address */, 394 RBUS_SPACE_DEDICATE); 395 396 /* program the bridge */ 397 398 /* enable I/O space */ 399 reg = pci_conf_read(pc, pci_bus_tag[busnum], 400 PCI_COMMAND_STATUS_REG); 401 reg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE; 402 pci_conf_write(pc, pci_bus_tag[busnum], 403 PCI_COMMAND_STATUS_REG, reg); 404 405 /* now init the limit register for I/O */ 406 pci_conf_write(pc, pci_bus_tag[busnum], PPB_REG_IOSTATUS, 407 (((start & 0xf000) >> 8) << PPB_IOBASE_SHIFT) | 408 ((((start + 409 rct.bussize_ioreqs[busnum] + 410 4095) & 0xf000) >> 8) << PPB_IOLIMIT_SHIFT)); 411 } 412 413 if(rct.bussize_memreqs[busnum]) { 414 if(rbus_space_alloc(rct.membustags[busparent], 415 0, 416 rct.bussize_memreqs[busnum] /* size */, 417 rct.bussize_memreqs[busnum]-1 /*mask */, 418 rct.bussize_memreqs[busnum] /* align */, 419 /* flags */ 0, 420 &start, 421 &handle) != 0) { 422 panic("rbus_ppb: can not allocate %ld bytes in MEM bus %d", 423 rct.bussize_memreqs[busnum], busnum); 424 } 425 rct.membustags[busnum]=rbus_new(rct.membustags[busparent], 426 start, 427 rct.bussize_memreqs[busnum], 428 0 /* offset to add to physical 429 address to make processor 430 address */, 431 RBUS_SPACE_DEDICATE); 432 433 /* program the bridge */ 434 /* enable memory space */ 435 reg = pci_conf_read(pc, pci_bus_tag[busnum], 436 PCI_COMMAND_STATUS_REG); 437 reg |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 438 pci_conf_write(pc, pci_bus_tag[busnum], 439 PCI_COMMAND_STATUS_REG, reg); 440 441 /* now init the limit register for memory */ 442 pci_conf_write(pc, pci_bus_tag[busnum], PPB_REG_MEM, 443 ((start & PPB_MEM_MASK) 444 >> PPB_MEM_SHIFT) << PPB_MEMBASE_SHIFT | 445 (((start + 446 rct.bussize_memreqs[busnum] + 447 PPB_MEM_MIN-1) >> PPB_MEM_SHIFT) 448 << PPB_MEMLIMIT_SHIFT)); 449 450 /* and set the prefetchable limits as well */ 451 pci_conf_write(pc, pci_bus_tag[busnum], PPB_REG_PREFMEM, 452 ((start & PPB_MEM_MASK) 453 >> PPB_MEM_SHIFT) << PPB_MEMBASE_SHIFT | 454 (((start + 455 rct.bussize_memreqs[busnum] + 456 PPB_MEM_MIN-1) >> PPB_MEM_SHIFT) 457 << PPB_MEMLIMIT_SHIFT)); 458 459 /* pci_conf_print(pc, pci_bus_tag[busnum], NULL); */ 460 } 461 } 462 463 printf("%s: configuring buses %d-%d\n", 464 device_xname(&rct.csc->sc_dev), 465 minbus, maxbus); 466 pci_device_foreach_min(pc, minbus, maxbus, 467 rbus_pci_phys_allocate, &rct); 468 } 469 470 static void 471 rbus_pci_phys_countspace(pc, tag, context) 472 pci_chipset_tag_t pc; 473 pcitag_t tag; 474 void *context; 475 { 476 int bus, device, function; 477 struct rbus_pci_addr_fixup_context *rct = 478 (struct rbus_pci_addr_fixup_context *)context; 479 480 pci_decompose_tag(pc, tag, &bus, &device, &function); 481 482 printf("%s: configuring device %02x:%02x:%02x\n", 483 device_xname(&rct->csc->sc_dev), 484 bus, device, function); 485 486 pciaddr_resource_manage(pc, tag, 487 rbus_do_phys_countspace, context); 488 } 489 490 491 int 492 rbus_do_phys_countspace(pc, tag, mapreg, ctx, type, addr, size) 493 pci_chipset_tag_t pc; 494 pcitag_t tag; 495 void *ctx; 496 int mapreg, type; 497 bus_addr_t *addr; 498 bus_size_t size; 499 { 500 struct rbus_pci_addr_fixup_context *rct = 501 (struct rbus_pci_addr_fixup_context *)ctx; 502 int bus, device, function; 503 504 pci_decompose_tag(pc, tag, &bus, &device, &function); 505 506 if(size > (1<<24)) { 507 printf("%s: skipping huge space request of size=%08x\n", 508 device_xname(&rct->csc->sc_dev), (unsigned int)size); 509 return 0; 510 } 511 512 if(PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_IO) { 513 rct->bussize_ioreqs[bus] += size; 514 } else { 515 rct->bussize_memreqs[bus]+= size; 516 } 517 518 return 0; 519 } 520 521 static void 522 rbus_pci_phys_allocate(pc, tag, context) 523 pci_chipset_tag_t pc; 524 pcitag_t tag; 525 void *context; 526 { 527 int bus, device, function, command; 528 struct rbus_pci_addr_fixup_context *rct = 529 (struct rbus_pci_addr_fixup_context *)context; 530 //cardbus_chipset_tag_t ct = rct->ct; 531 // struct cardbus_softc *sc = rct->sc; 532 533 pci_decompose_tag(pc, tag, &bus, &device, &function); 534 535 printf("%s: configuring device %02x:%02x:%02x\n", 536 device_xname(&rct->csc->sc_dev), 537 bus, device, function); 538 539 pciaddr_resource_manage(pc, tag, 540 rbus_do_phys_allocate, context); 541 542 /* now turn the device's memory and I/O on */ 543 command = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 544 command |= PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE; 545 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, command); 546 } 547 548 int 549 rbus_do_phys_allocate(pc, tag, mapreg, ctx, type, addr, size) 550 pci_chipset_tag_t pc; 551 pcitag_t tag; 552 void *ctx; 553 int mapreg, type; 554 bus_addr_t *addr; 555 bus_size_t size; 556 { 557 struct rbus_pci_addr_fixup_context *rct = 558 (struct rbus_pci_addr_fixup_context *)ctx; 559 cardbus_chipset_tag_t ct = rct->ct; 560 struct cardbus_softc *sc = rct->sc; 561 cardbus_function_t *cf = sc->sc_cf; 562 rbus_tag_t rbustag; 563 bus_space_tag_t bustag; 564 bus_addr_t mask = size -1; 565 bus_addr_t base = 0; 566 bus_space_handle_t handle; 567 int busflags = 0; 568 int flags = 0; 569 const char *bustype; 570 int bus, device, function; 571 572 pci_decompose_tag(pc, tag, &bus, &device, &function); 573 574 /* 575 * some devices come up with garbage in them (Tulip?) 576 * we are in charge here, so give them address 577 * space anyway. 578 * 579 * XXX this may be due to no secondary PCI reset!!! 580 */ 581 #if 0 582 if (*addr) { 583 printf("Already allocated space at %08x\n", 584 (unsigned int)*addr); 585 return (0); 586 } 587 #endif 588 589 if(size > (1<<24)) { 590 printf("%s: skipping huge space request of size=%08x\n", 591 device_xname(&rct->csc->sc_dev), (unsigned int)size); 592 return 0; 593 } 594 595 if(PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_IO) { 596 bustag = sc->sc_iot; 597 rbustag = rct->iobustags[bus]; 598 bustype = "io"; 599 } else { 600 bustag = sc->sc_memt; 601 rbustag = rct->membustags[bus]; 602 bustype = "mem"; 603 } 604 605 if((*cf->cardbus_space_alloc)(ct, rbustag, base, size, 606 mask, size, busflags|flags, 607 addr, &handle)) { 608 printf("%s: no available resources (size=%08x) for bar %2d. fixup failed\n", 609 device_xname(&rct->csc->sc_dev), (unsigned int)size, mapreg); 610 611 *addr = 0; 612 pci_conf_write(pc, tag, mapreg, *addr); 613 return (1); 614 } 615 616 printf("%s: alloc %s space of size %08x for %02d:%02d:%02d -> %08x\n", 617 device_xname(&rct->csc->sc_dev), 618 bustype, 619 (unsigned int)size, 620 bus, device, function, (unsigned int)*addr); 621 622 /* write new address to PCI device configuration header */ 623 pci_conf_write(pc, tag, mapreg, *addr); 624 625 /* check */ 626 { 627 DPRINTF(("%s: pci_addr_fixup: ", 628 device_xname(&rct->csc->sc_dev))); 629 #ifdef CBB_DEBUG 630 if(rbus_ppb_debug) { pciaddr_print_devid(pc, tag); } 631 #endif 632 } 633 634 /* double check that the value got inserted correctly */ 635 if (pciaddr_ioaddr(pci_conf_read(pc, tag, mapreg)) != *addr) { 636 pci_conf_write(pc, tag, mapreg, 0); /* clear */ 637 printf("%s: fixup failed. (new address=%#x)\n", 638 device_xname(&rct->csc->sc_dev), 639 (unsigned)*addr); 640 return (1); 641 } 642 643 DPRINTF(("new address 0x%08x\n", 644 (unsigned)*addr)); 645 646 return (0); 647 } 648 649 static void 650 ppb_cardbus_attach(parent, self, aux) 651 struct device *parent, *self; 652 void *aux; 653 { 654 struct ppb_cardbus_softc *csc = device_private(self); 655 struct cardbus_softc *parent_sc = 656 device_private(device_parent(&csc->sc_dev)); 657 struct cardbus_attach_args *ca = aux; 658 cardbus_devfunc_t ct = ca->ca_ct; 659 cardbus_chipset_tag_t cc = ct->ct_cc; 660 cardbus_function_tag_t cf = ct->ct_cf; 661 struct pccbb_softc *psc = (struct pccbb_softc *)cc; 662 struct pcibus_attach_args pba; 663 char devinfo[256]; 664 pcireg_t busdata; 665 int mybus, rv; 666 u_int16_t pciirq; 667 int minbus, maxbus; 668 669 mybus = ct->ct_bus; 670 pciirq = 0; 671 rv = 0; 672 673 /* shut up compiler */ 674 csc->foo=parent_sc->sc_intrline; 675 676 677 pci_devinfo(ca->ca_id, ca->ca_class, 0, devinfo, sizeof(devinfo)); 678 printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(ca->ca_class)); 679 680 csc->sc_tag = ca->ca_tag; /* XXX cardbustag_t == pcitag_t */ 681 682 busdata = cardbus_conf_read(cc, cf, ca->ca_tag, PPB_REG_BUSINFO); 683 minbus = pcibios_max_bus; 684 maxbus = minbus; /* XXX; gcc */ 685 686 if (PPB_BUSINFO_SECONDARY(busdata) == 0) { 687 aprint_error_dev(self, "not configured by system firmware calling pci_bus_fixup(%d)\n", 0); 688 689 /* 690 * first, pull the reset wire on the secondary bridge 691 * to clear all devices 692 */ 693 busdata = cardbus_conf_read(cc, cf, ca->ca_tag, 694 PPB_REG_BRIDGECONTROL); 695 cardbus_conf_write(cc, cf, ca->ca_tag, PPB_REG_BRIDGECONTROL, 696 busdata | PPB_BC_SECONDARY_RESET); 697 delay(1); 698 cardbus_conf_write(cc, cf, ca->ca_tag, PPB_REG_BRIDGECONTROL, 699 busdata); 700 701 /* then go initialize the bridge control registers */ 702 maxbus = pci_bus_fixup(psc->sc_pc, 0); 703 } 704 705 busdata = cardbus_conf_read(cc, cf, ca->ca_tag, PPB_REG_BUSINFO); 706 if(PPB_BUSINFO_SECONDARY(busdata) == 0) { 707 aprint_error_dev(self, "still not configured, not fixable.\n"); 708 return; 709 } 710 711 #if 0 712 minbus = PPB_BUSINFO_SECONDARY(busdata); 713 maxbus = PPB_BUSINFO_SUBORDINATE(busdata); 714 #endif 715 716 /* now, go and assign addresses for the new devices */ 717 rbus_pci_addr_fixup(csc, cc, parent_sc, 718 psc->sc_pc, 719 ca, 720 minbus, maxbus); 721 722 /* 723 * now configure all connected devices to the IRQ which 724 * was assigned to this slot, as they will all arrive from 725 * that IRQ. 726 */ 727 rbus_intr_fixup(psc->sc_pc, minbus, maxbus, ca->ca_intrline); 728 729 /* 730 * enable direct routing of interrupts. We do this because 731 * we can not manage to get pccb_intr_establish() called until 732 * PCI subsystem is merged with rbus. The major thing that this 733 * routine does is avoid calling the driver's interrupt routine 734 * when the card has been removed. 735 * 736 * The rbus_ppb.c can not cope with card desertions until the merging 737 * anyway. 738 */ 739 pccbb_intr_route(psc); 740 741 /* 742 * Attach the PCI bus than hangs off of it. 743 * 744 * XXX Don't pass-through Memory Read Multiple. Should we? 745 * XXX Consult the spec... 746 */ 747 pba.pba_iot = ca->ca_iot; 748 pba.pba_memt = ca->ca_memt; 749 pba.pba_dmat = ca->ca_dmat; 750 pba.pba_pc = psc->sc_pc; 751 pba.pba_flags = PCI_FLAGS_IO_ENABLED|PCI_FLAGS_MEM_ENABLED; 752 pba.pba_bus = PPB_BUSINFO_SECONDARY(busdata); 753 pba.pba_bridgetag = &csc->sc_tag; 754 /*pba.pba_intrswiz = parent_sc->sc_intrswiz; */ 755 pba.pba_intrtag = psc->sc_pa.pa_intrtag; 756 757 config_found_ia(self, "pcibus", &pba, rppbprint); 758 } 759 760 void 761 ppb_cardbus_setup(struct ppb_softc * sc) 762 { 763 struct ppb_cardbus_softc *csc = (struct ppb_cardbus_softc *) sc; 764 #if 0 765 cardbus_chipset_tag_t cc = psc->sc_cc; 766 cardbus_function_tag_t cf = psc->sc_cf; 767 #endif 768 769 /* shut up compiler */ 770 csc->foo=2; 771 772 printf("ppb_cardbus_setup called\n"); 773 #if 0 774 /* not sure what to do here */ 775 cardbustag_t tag = cardbus_make_tag(cc, cf, csc->ct->ct_bus, 776 csc->ct->ct_dev, csc->ct->ct_func); 777 778 command = Cardbus_conf_read(csc->ct, tag, CARDBUS_COMMAND_STATUS_REG); 779 if (csc->base0_reg) { 780 Cardbus_conf_write(csc->ct, tag, 781 CARDBUS_BASE0_REG, csc->base0_reg); 782 (cf->cardbus_ctrl) (cc, CARDBUS_MEM_ENABLE); 783 command |= CARDBUS_COMMAND_MEM_ENABLE | 784 CARDBUS_COMMAND_MASTER_ENABLE; 785 } else if (csc->base1_reg) { 786 Cardbus_conf_write(csc->ct, tag, 787 CARDBUS_BASE1_REG, csc->base1_reg); 788 (cf->cardbus_ctrl) (cc, CARDBUS_IO_ENABLE); 789 command |= (CARDBUS_COMMAND_IO_ENABLE | 790 CARDBUS_COMMAND_MASTER_ENABLE); 791 } 792 793 (cf->cardbus_ctrl) (cc, CARDBUS_BM_ENABLE); 794 795 /* enable the card */ 796 Cardbus_conf_write(csc->ct, tag, CARDBUS_COMMAND_STATUS_REG, command); 797 #endif 798 } 799 800 int 801 ppb_cardbus_enable(struct ppb_softc * sc) 802 { 803 #if 0 804 struct ppb_cardbus_softc *csc = (struct fxp_cardbus_softc *) sc; 805 struct cardbus_softc *psc = 806 (struct cardbus_softc *) device_parent(&sc->sc_dev); 807 cardbus_chipset_tag_t cc = psc->sc_cc; 808 cardbus_function_tag_t cf = psc->sc_cf; 809 810 Cardbus_function_enable(csc->ct); 811 812 fxp_cardbus_setup(sc); 813 814 /* Map and establish the interrupt. */ 815 816 sc->sc_ih = cardbus_intr_establish(cc, cf, psc->sc_intrline, IPL_NET, 817 fxp_intr, sc); 818 if (NULL == sc->sc_ih) { 819 aprint_error_dev(&sc->sc_dev, "couldn't establish interrupt\n"); 820 return 1; 821 } 822 823 printf("%s: interrupting at %d\n", device_xname(&sc->sc_dev), 824 psc->sc_intrline); 825 826 #endif 827 return 0; 828 } 829 830 void 831 ppb_cardbus_disable(struct ppb_softc * sc) 832 { 833 #if 0 834 struct cardbus_softc *psc = 835 (struct cardbus_softc *) device_parent(&sc->sc_dev); 836 cardbus_chipset_tag_t cc = psc->sc_cc; 837 cardbus_function_tag_t cf = psc->sc_cf; 838 839 /* Remove interrupt handler. */ 840 cardbus_intr_disestablish(cc, cf, sc->sc_ih); 841 842 Cardbus_function_disable(((struct fxp_cardbus_softc *) sc)->ct); 843 #endif 844 } 845 846 static int 847 ppb_cardbus_detach(self, flags) 848 struct device *self; 849 int flags; 850 { 851 /* struct ppb_softc *sc = device_private(self);*/ 852 struct ppb_cardbus_softc *csc = device_private(self); 853 854 #if 0 855 struct cardbus_devfunc *ct = csc->ct; 856 int rv, reg; 857 858 #ifdef DIAGNOSTIC 859 if (ct == NULL) 860 panic("%s: data structure lacks", device_xname(&sc->sc_dev)); 861 #endif 862 863 rv = fxp_detach(sc); 864 if (rv == 0) { 865 /* 866 * Unhook the interrupt handler. 867 */ 868 cardbus_intr_disestablish(ct->ct_cc, ct->ct_cf, sc->sc_ih); 869 870 /* 871 * release bus space and close window 872 */ 873 if (csc->base0_reg) 874 reg = CARDBUS_BASE0_REG; 875 else 876 reg = CARDBUS_BASE1_REG; 877 Cardbus_mapreg_unmap(ct, reg, sc->sc_st, sc->sc_sh, csc->size); 878 } 879 return (rv); 880 881 #endif 882 csc->foo=1; 883 return 0; 884 885 } 886 887 int 888 ppb_activate(self, act) 889 struct device *self; 890 enum devact act; 891 { 892 printf("ppb_activate called\n"); 893 return 0; 894 } 895 896
Indexes created Mon Sep 29 13:09:55 GMT 2025