rbus_ppb.c revision 1.43 1 /* $NetBSD: rbus_ppb.c,v 1.43 2014/10/17 20:52:00 uebayasi Exp $ */
2
3 /*
4 * Copyright (c) 1999 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Michael Richardson <mcr (at) sandelman.ottawa.on.ca>
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 /*
33 * CardBus front-end for the Intel/Digital DECchip 21152 PCI-PCI bridge
34 */
35
36 #include <sys/cdefs.h>
37 __KERNEL_RCSID(0, "$NetBSD: rbus_ppb.c,v 1.43 2014/10/17 20:52:00 uebayasi Exp $");
38
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/mbuf.h>
42 #include <sys/malloc.h>
43 #include <sys/kernel.h>
44 #include <sys/socket.h>
45 #include <sys/ioctl.h>
46 #include <sys/errno.h>
47 #include <sys/device.h>
48 #include <sys/kmem.h>
49
50 #include <sys/rnd.h>
51
52 #include <machine/endian.h>
53
54 #include <sys/bus.h>
55 #include <sys/intr.h>
56
57 #include <dev/pci/pcivar.h>
58 #include <dev/pci/pcireg.h>
59 #include <dev/pci/pcidevs.h>
60 #include <dev/pci/ppbreg.h>
61
62 #include <dev/ic/i82365reg.h>
63
64 #include <dev/cardbus/rbus.h>
65 #include <dev/pci/pccbbreg.h>
66 #include <dev/pci/pccbbvar.h>
67
68 #include <dev/cardbus/cardbusvar.h>
69 #include <dev/pci/pcidevs.h>
70
71 #include <x86/pci/pci_addr_fixup.h>
72 #include <x86/pci/pci_bus_fixup.h>
73 #include <i386/pci/pci_intr_fixup.h>
74 #include <i386/pci/pcibios.h>
75
76 struct ppb_softc;
77
78 static int ppb_cardbus_match(device_t, cfdata_t, void *);
79 static void ppb_cardbus_attach(device_t, device_t, void *);
80 static int ppb_activate(device_t, enum devact);
81 int rppbprint(void *, const char *);
82 int rbus_intr_fixup(pci_chipset_tag_t, int, int, int);
83 void rbus_do_header_fixup(pci_chipset_tag_t, pcitag_t, void *);
84
85 static void rbus_pci_phys_allocate(pci_chipset_tag_t, pcitag_t, void *);
86
87 static int rbus_do_phys_allocate(pci_chipset_tag_t, pcitag_t, int,
88 void *, int, bus_addr_t *, bus_size_t);
89
90 static void rbus_pci_phys_countspace(pci_chipset_tag_t, pcitag_t, void *);
91
92 static int rbus_do_phys_countspace(pci_chipset_tag_t, pcitag_t, int,
93 void *, int, bus_addr_t *, bus_size_t);
94
95 unsigned int rbus_round_up(unsigned int, unsigned int);
96
97
98 struct ppb_cardbus_softc {
99 device_t sc_dev;
100 pcitag_t sc_tag;
101 int foo;
102 };
103
104 CFATTACH_DECL_NEW(rbus_ppb, sizeof(struct ppb_cardbus_softc),
105 ppb_cardbus_match, ppb_cardbus_attach, NULL, ppb_activate);
106
107 #ifdef CBB_DEBUG
108 int rbus_ppb_debug = 0; /* hack with kdb */
109 #define DPRINTF(X) if(rbus_ppb_debug) printf X
110 #else
111 #define DPRINTF(X)
112 #endif
113
114 static int
115 ppb_cardbus_match(device_t parent, cfdata_t match, void *aux)
116 {
117 struct cardbus_attach_args *ca = aux;
118
119 if (PCI_VENDOR(ca->ca_id) == PCI_VENDOR_DEC &&
120 PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_DEC_21152)
121 return (1);
122
123 if(PCI_CLASS(ca->ca_class) == PCI_CLASS_BRIDGE &&
124 PCI_SUBCLASS(ca->ca_class) == PCI_SUBCLASS_BRIDGE_PCI) {
125 /* XXX */
126 printf("recognizing generic bridge chip\n");
127 }
128
129 return (0);
130 }
131
132
133 int
134 rppbprint(void *aux, const char *pnp)
135 {
136 struct pcibus_attach_args *pba = aux;
137
138 /* only PCIs can attach to PPBs; easy. */
139 if (pnp)
140 aprint_normal("pci at %s", pnp);
141 aprint_normal(" bus %d (rbus)", pba->pba_bus);
142 return (UNCONF);
143 }
144
145 int
146 rbus_intr_fixup(pci_chipset_tag_t pc,
147 int minbus,
148 int maxbus,
149 int line)
150 {
151 pci_device_foreach_min(pc, minbus,
152 maxbus, rbus_do_header_fixup, (void *)&line);
153 return 0;
154 }
155
156 void
157 rbus_do_header_fixup(pci_chipset_tag_t pc, pcitag_t tag, void *context)
158 {
159 int bus, device, function;
160 pcireg_t intr;
161 int *pline = (int *)context;
162 int line = *pline;
163
164 pci_decompose_tag(pc, tag, &bus, &device, &function);
165
166 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);
167
168 intr &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT);
169 intr |= (line << PCI_INTERRUPT_LINE_SHIFT);
170 pci_conf_write(pc, tag, PCI_INTERRUPT_REG, intr);
171
172 }
173
174 /*
175 * This function takes a range of PCI bus numbers and
176 * allocates space for all devices found in this space (the BARs) from
177 * the rbus space maps (I/O and memory).
178 *
179 * It assumes that "rbus" is defined. The whole concept does.
180 *
181 * It uses pci_device_foreach_min() to call rbus_pci_phys_allocate.
182 * This function is mostly stolen from
183 * pci_addr_fixup.c:pciaddr_resource_reserve.
184 *
185 */
186 struct rbus_pci_addr_fixup_context {
187 struct ppb_cardbus_softc *csc;
188 cardbus_chipset_tag_t ct;
189 struct cardbus_softc *sc;
190 struct cardbus_attach_args *caa;
191 int minbus;
192 int maxbus;
193 bus_size_t *bussize_ioreqs;
194 bus_size_t *bussize_memreqs;
195 rbus_tag_t *iobustags;
196 rbus_tag_t *membustags;
197 };
198
199 unsigned int
200 rbus_round_up(unsigned int size, unsigned int minval)
201 {
202 unsigned int power2;
203
204 if(size == 0) {
205 return 0;
206 }
207
208 power2=minval;
209
210 while(power2 < (1 << 31) &&
211 power2 < size) {
212 power2 = power2 << 1;
213 }
214
215 return power2;
216 }
217
218 static void
219 rbus_pci_addr_fixup(struct ppb_cardbus_softc *csc,
220 cardbus_chipset_tag_t ct,
221 struct cardbus_softc *sc,
222 pci_chipset_tag_t pc,
223 struct cardbus_attach_args *caa,
224 int minbus, const int maxbus)
225 {
226 struct rbus_pci_addr_fixup_context rct;
227 const size_t size = sizeof(bus_size_t[maxbus+1]);
228 int busnum;
229 bus_addr_t start;
230 bus_space_handle_t handle;
231 u_int32_t reg;
232
233 rct.csc=csc;
234 rct.ct=ct;
235 rct.sc=sc;
236 rct.caa=caa;
237 rct.minbus = minbus;
238 rct.maxbus = maxbus;
239 if ((rct.bussize_ioreqs = kmem_zalloc(size, KM_SLEEP)) == NULL ||
240 (rct.bussize_memreqs = kmem_zalloc(size, KM_SLEEP)) == NULL ||
241 (rct.iobustags =
242 kmem_zalloc(maxbus * sizeof(rbus_tag_t), KM_SLEEP)) == NULL ||
243 (rct.membustags =
244 kmem_zalloc(maxbus * sizeof(rbus_tag_t), KM_SLEEP)) == NULL)
245 panic("%s: memory allocation failed", __func__);
246
247 printf("%s: sizing buses %d-%d\n",
248 device_xname(rct.csc->sc_dev),
249 minbus, maxbus);
250
251 pci_device_foreach_min(pc, minbus, maxbus,
252 rbus_pci_phys_countspace, &rct);
253
254 /*
255 * we need to determine amount of address space for each
256 * bus. To do this, we have to roll up amounts and then
257 * we need to divide up the cardbus's extent to allocate
258 * some space to each bus.
259 */
260
261 for(busnum=maxbus; busnum > minbus; busnum--) {
262 if(pci_bus_parent[busnum] != 0) {
263 if(pci_bus_parent[busnum] < minbus ||
264 pci_bus_parent[busnum] >= maxbus) {
265 printf("%s: bus %d has illegal parent %d\n",
266 device_xname(rct.csc->sc_dev),
267 busnum, pci_bus_parent[busnum]);
268 continue;
269 }
270
271 /* first round amount of space up */
272 rct.bussize_ioreqs[busnum] =
273 rbus_round_up(rct.bussize_ioreqs[busnum], PPB_IO_MIN);
274 rct.bussize_ioreqs[pci_bus_parent[busnum]] +=
275 rct.bussize_ioreqs[busnum];
276
277 rct.bussize_memreqs[busnum] =
278 rbus_round_up(rct.bussize_memreqs[busnum], PPB_MEM_MIN);
279 rct.bussize_memreqs[pci_bus_parent[busnum]] +=
280 rct.bussize_memreqs[busnum];
281
282 }
283 }
284
285 rct.bussize_ioreqs[minbus] =
286 rbus_round_up(rct.bussize_ioreqs[minbus], 4096);
287 rct.bussize_memreqs[minbus] =
288 rbus_round_up(rct.bussize_memreqs[minbus], 8);
289
290 printf("%s: total needs IO %08zx and MEM %08zx\n",
291 device_xname(rct.csc->sc_dev),
292 rct.bussize_ioreqs[minbus], rct.bussize_memreqs[minbus]);
293
294 if(!caa->ca_rbus_iot) {
295 panic("no iot bus");
296 }
297
298 if(rct.bussize_ioreqs[minbus]) {
299 if(rbus_space_alloc(caa->ca_rbus_iot, 0,
300 rct.bussize_ioreqs[minbus],
301 rct.bussize_ioreqs[minbus]-1 /* mask */,
302 rct.bussize_ioreqs[minbus] /* align */,
303 /* flags */ 0,
304 &start,
305 &handle) != 0) {
306 panic("rbus_ppb: can not allocate %zu bytes in IO bus %d",
307 rct.bussize_ioreqs[minbus], minbus);
308 }
309 rct.iobustags[minbus]=rbus_new(caa->ca_rbus_iot,
310 start,
311 rct.bussize_ioreqs[minbus],
312 0 /* offset to add to physical address
313 to make processor address */,
314 RBUS_SPACE_DEDICATE);
315 }
316
317 if(rct.bussize_memreqs[minbus]) {
318 if(rbus_space_alloc(caa->ca_rbus_memt, 0,
319 rct.bussize_memreqs[minbus],
320 rct.bussize_memreqs[minbus]-1 /* mask */,
321 rct.bussize_memreqs[minbus] /* align */,
322 /* flags */ 0,
323 &start,
324 &handle) != 0) {
325 panic("%s: can not allocate %zu bytes in MEM bus %d",
326 device_xname(rct.csc->sc_dev),
327 rct.bussize_memreqs[minbus], minbus);
328 }
329 rct.membustags[minbus]=rbus_new(caa->ca_rbus_memt,
330 start,
331 rct.bussize_memreqs[minbus],
332 0 /* offset to add to physical
333 address to make processor
334 address */,
335 RBUS_SPACE_DEDICATE);
336 }
337
338 for(busnum=minbus+1; busnum <= maxbus; busnum++) {
339 int busparent;
340
341 busparent = pci_bus_parent[busnum];
342
343 printf("%s: bus %d (parent=%d) needs IO %08zx and MEM %08zx\n",
344 device_xname(rct.csc->sc_dev),
345 busnum,
346 busparent,
347 rct.bussize_ioreqs[busnum],
348 rct.bussize_memreqs[busnum]);
349
350 if(busparent > maxbus) {
351 panic("rbus_ppb: illegal parent");
352 }
353
354 if(rct.bussize_ioreqs[busnum]) {
355 if(rbus_space_alloc(rct.iobustags[busparent],
356 0,
357 rct.bussize_ioreqs[busnum],
358 rct.bussize_ioreqs[busnum]-1 /*mask */,
359 rct.bussize_ioreqs[busnum] /* align */,
360 /* flags */ 0,
361 &start,
362 &handle) != 0) {
363 panic("rbus_ppb: can not allocate %zu bytes in IO bus %d",
364 rct.bussize_ioreqs[busnum], busnum);
365 }
366 rct.iobustags[busnum]=rbus_new(rct.iobustags[busparent],
367 start,
368 rct.bussize_ioreqs[busnum],
369 0 /* offset to add to physical
370 address
371 to make processor address */,
372 RBUS_SPACE_DEDICATE);
373
374 /* program the bridge */
375
376 /* enable I/O space */
377 reg = pci_conf_read(pc, pci_bus_tag[busnum],
378 PCI_COMMAND_STATUS_REG);
379 reg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE;
380 pci_conf_write(pc, pci_bus_tag[busnum],
381 PCI_COMMAND_STATUS_REG, reg);
382
383 /* now init the limit register for I/O */
384 pci_conf_write(pc, pci_bus_tag[busnum], PPB_REG_IOSTATUS,
385 (((start & 0xf000) >> 8) << PPB_IOBASE_SHIFT) |
386 ((((start +
387 rct.bussize_ioreqs[busnum] +
388 4095) & 0xf000) >> 8) << PPB_IOLIMIT_SHIFT));
389 }
390
391 if(rct.bussize_memreqs[busnum]) {
392 if(rbus_space_alloc(rct.membustags[busparent],
393 0,
394 rct.bussize_memreqs[busnum] /* size */,
395 rct.bussize_memreqs[busnum]-1 /*mask */,
396 rct.bussize_memreqs[busnum] /* align */,
397 /* flags */ 0,
398 &start,
399 &handle) != 0) {
400 panic("rbus_ppb: can not allocate %zu bytes in MEM bus %d",
401 rct.bussize_memreqs[busnum], busnum);
402 }
403 rct.membustags[busnum]=rbus_new(rct.membustags[busparent],
404 start,
405 rct.bussize_memreqs[busnum],
406 0 /* offset to add to physical
407 address to make processor
408 address */,
409 RBUS_SPACE_DEDICATE);
410
411 /* program the bridge */
412 /* enable memory space */
413 reg = pci_conf_read(pc, pci_bus_tag[busnum],
414 PCI_COMMAND_STATUS_REG);
415 reg |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE;
416 pci_conf_write(pc, pci_bus_tag[busnum],
417 PCI_COMMAND_STATUS_REG, reg);
418
419 /* now init the limit register for memory */
420 pci_conf_write(pc, pci_bus_tag[busnum], PPB_REG_MEM,
421 ((start & PPB_MEM_MASK)
422 >> PPB_MEM_SHIFT) << PPB_MEMBASE_SHIFT |
423 (((start +
424 rct.bussize_memreqs[busnum] +
425 PPB_MEM_MIN-1) >> PPB_MEM_SHIFT)
426 << PPB_MEMLIMIT_SHIFT));
427
428 /* and set the prefetchable limits as well */
429 pci_conf_write(pc, pci_bus_tag[busnum], PPB_REG_PREFMEM,
430 ((start & PPB_MEM_MASK)
431 >> PPB_MEM_SHIFT) << PPB_MEMBASE_SHIFT |
432 (((start +
433 rct.bussize_memreqs[busnum] +
434 PPB_MEM_MIN-1) >> PPB_MEM_SHIFT)
435 << PPB_MEMLIMIT_SHIFT));
436
437 /* pci_conf_print(pc, pci_bus_tag[busnum], NULL); */
438 }
439 }
440
441 printf("%s: configuring buses %d-%d\n",
442 device_xname(rct.csc->sc_dev),
443 minbus, maxbus);
444 pci_device_foreach_min(pc, minbus, maxbus,
445 rbus_pci_phys_allocate, &rct);
446
447 kmem_free(rct.bussize_ioreqs, size);
448 kmem_free(rct.bussize_memreqs, size);
449 kmem_free(rct.iobustags, maxbus * sizeof(rbus_tag_t));
450 kmem_free(rct.membustags, maxbus * sizeof(rbus_tag_t));
451 }
452
453 static void
454 rbus_pci_phys_countspace(pci_chipset_tag_t pc, pcitag_t tag, void *context)
455 {
456 int bus, device, function;
457 struct rbus_pci_addr_fixup_context *rct =
458 (struct rbus_pci_addr_fixup_context *)context;
459
460 pci_decompose_tag(pc, tag, &bus, &device, &function);
461
462 printf("%s: configuring device %02x:%02x:%02x\n",
463 device_xname(rct->csc->sc_dev),
464 bus, device, function);
465
466 pciaddr_resource_manage(pc, tag,
467 rbus_do_phys_countspace, context);
468 }
469
470
471 int
472 rbus_do_phys_countspace(pci_chipset_tag_t pc, pcitag_t tag, int mapreg, void *ctx, int type, bus_addr_t *addr, bus_size_t size)
473 {
474 struct rbus_pci_addr_fixup_context *rct =
475 (struct rbus_pci_addr_fixup_context *)ctx;
476 int bus, device, function;
477
478 pci_decompose_tag(pc, tag, &bus, &device, &function);
479
480 if(size > (1<<24)) {
481 printf("%s: skipping huge space request of size=%08x\n",
482 device_xname(rct->csc->sc_dev), (unsigned int)size);
483 return 0;
484 }
485
486 if(PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_IO) {
487 rct->bussize_ioreqs[bus] += size;
488 } else {
489 rct->bussize_memreqs[bus]+= size;
490 }
491
492 return 0;
493 }
494
495 static void
496 rbus_pci_phys_allocate(pci_chipset_tag_t pc, pcitag_t tag, void *context)
497 {
498 int bus, device, function, command;
499 struct rbus_pci_addr_fixup_context *rct =
500 (struct rbus_pci_addr_fixup_context *)context;
501
502 pci_decompose_tag(pc, tag, &bus, &device, &function);
503
504 printf("%s: configuring device %02x:%02x:%02x\n",
505 device_xname(rct->csc->sc_dev),
506 bus, device, function);
507
508 pciaddr_resource_manage(pc, tag,
509 rbus_do_phys_allocate, context);
510
511 /* now turn the device's memory and I/O on */
512 command = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
513 command |= PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE;
514 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, command);
515 }
516
517 int
518 rbus_do_phys_allocate(pci_chipset_tag_t pc, pcitag_t tag, int mapreg, void *ctx, int type, bus_addr_t *addr, bus_size_t size)
519 {
520 struct rbus_pci_addr_fixup_context *rct =
521 (struct rbus_pci_addr_fixup_context *)ctx;
522 cardbus_chipset_tag_t ct = rct->ct;
523 struct cardbus_softc *sc = rct->sc;
524 cardbus_function_t *cf = sc->sc_cf;
525 rbus_tag_t rbustag;
526 bus_addr_t mask = size -1;
527 bus_addr_t base = 0;
528 bus_space_handle_t handle;
529 int busflags = 0;
530 int flags = 0;
531 const char *bustype;
532 int bus, device, function;
533
534 pci_decompose_tag(pc, tag, &bus, &device, &function);
535
536 /*
537 * some devices come up with garbage in them (Tulip?)
538 * we are in charge here, so give them address
539 * space anyway.
540 *
541 * XXX this may be due to no secondary PCI reset!!!
542 */
543 #if 0
544 if (*addr) {
545 printf("Already allocated space at %08x\n",
546 (unsigned int)*addr);
547 return (0);
548 }
549 #endif
550
551 if(size > (1<<24)) {
552 printf("%s: skipping huge space request of size=%08x\n",
553 device_xname(rct->csc->sc_dev), (unsigned int)size);
554 return 0;
555 }
556
557 if(PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_IO) {
558 rbustag = rct->iobustags[bus];
559 bustype = "io";
560 } else {
561 rbustag = rct->membustags[bus];
562 bustype = "mem";
563 }
564
565 if((*cf->cardbus_space_alloc)(ct, rbustag, base, size,
566 mask, size, busflags|flags,
567 addr, &handle)) {
568 printf("%s: no available resources (size=%08x) for bar %2d. fixup failed\n",
569 device_xname(rct->csc->sc_dev), (unsigned int)size, mapreg);
570
571 *addr = 0;
572 pci_conf_write(pc, tag, mapreg, *addr);
573 return (1);
574 }
575
576 printf("%s: alloc %s space of size %08x for %02d:%02d:%02d -> %08x\n",
577 device_xname(rct->csc->sc_dev),
578 bustype,
579 (unsigned int)size,
580 bus, device, function, (unsigned int)*addr);
581
582 /* write new address to PCI device configuration header */
583 pci_conf_write(pc, tag, mapreg, *addr);
584
585 /* check */
586 {
587 DPRINTF(("%s: pci_addr_fixup: ",
588 device_xname(rct->csc->sc_dev)));
589 #ifdef CBB_DEBUG
590 if(rbus_ppb_debug) { pciaddr_print_devid(pc, tag); }
591 #endif
592 }
593
594 /* double check that the value got inserted correctly */
595 if (pciaddr_ioaddr(pci_conf_read(pc, tag, mapreg)) != *addr) {
596 pci_conf_write(pc, tag, mapreg, 0); /* clear */
597 printf("%s: fixup failed. (new address=%#x)\n",
598 device_xname(rct->csc->sc_dev),
599 (unsigned)*addr);
600 return (1);
601 }
602
603 DPRINTF(("new address 0x%08x\n",
604 (unsigned)*addr));
605
606 return (0);
607 }
608
609 static void
610 ppb_cardbus_attach(device_t parent, device_t self, void *aux)
611 {
612 struct ppb_cardbus_softc *csc = device_private(self);
613 struct cardbus_softc *parent_sc = device_private(parent);
614 struct cardbus_attach_args *ca = aux;
615 cardbus_devfunc_t ct = ca->ca_ct;
616 cardbus_chipset_tag_t cc = ct->ct_cc;
617 struct pccbb_softc *psc = (struct pccbb_softc *)cc;
618 struct pcibus_attach_args pba;
619 char devinfo[256];
620 pcireg_t busdata;
621 int minbus, maxbus;
622
623 csc->sc_dev = self;
624
625 pci_devinfo(ca->ca_id, ca->ca_class, 0, devinfo, sizeof(devinfo));
626 printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(ca->ca_class));
627
628 csc->sc_tag = ca->ca_tag;
629
630 busdata = Cardbus_conf_read(ct, ca->ca_tag, PPB_REG_BUSINFO);
631 minbus = pcibios_max_bus;
632 maxbus = minbus; /* XXX; gcc */
633
634 if (PPB_BUSINFO_SECONDARY(busdata) == 0) {
635 aprint_error_dev(self, "not configured by system firmware calling pci_bus_fixup(%d)\n", 0);
636
637 /*
638 * first, pull the reset wire on the secondary bridge
639 * to clear all devices
640 */
641 busdata = Cardbus_conf_read(ct, ca->ca_tag,
642 PPB_REG_BRIDGECONTROL);
643 Cardbus_conf_write(ct, ca->ca_tag, PPB_REG_BRIDGECONTROL,
644 busdata | PPB_BC_SECONDARY_RESET);
645 delay(1);
646 Cardbus_conf_write(ct, ca->ca_tag, PPB_REG_BRIDGECONTROL,
647 busdata);
648
649 /* then go initialize the bridge control registers */
650 maxbus = pci_bus_fixup(psc->sc_pc, 0);
651 }
652
653 busdata = Cardbus_conf_read(ct, ca->ca_tag, PPB_REG_BUSINFO);
654 if(PPB_BUSINFO_SECONDARY(busdata) == 0) {
655 aprint_error_dev(self, "still not configured, not fixable.\n");
656 return;
657 }
658
659 #if 0
660 minbus = PPB_BUSINFO_SECONDARY(busdata);
661 maxbus = PPB_BUSINFO_SUBORDINATE(busdata);
662 #endif
663
664 /* now, go and assign addresses for the new devices */
665 rbus_pci_addr_fixup(csc, cc, parent_sc,
666 psc->sc_pc,
667 ca,
668 minbus, maxbus);
669
670 /*
671 * now configure all connected devices to the IRQ which
672 * was assigned to this slot, as they will all arrive from
673 * that IRQ.
674 */
675 rbus_intr_fixup(psc->sc_pc, minbus, maxbus, 0);
676
677 /*
678 * enable direct routing of interrupts. We do this because
679 * we can not manage to get pccb_intr_establish() called until
680 * PCI subsystem is merged with rbus. The major thing that this
681 * routine does is avoid calling the driver's interrupt routine
682 * when the card has been removed.
683 *
684 * The rbus_ppb.c can not cope with card desertions until the merging
685 * anyway.
686 */
687 pccbb_intr_route(psc);
688
689 /*
690 * Attach the PCI bus than hangs off of it.
691 *
692 * XXX Don't pass-through Memory Read Multiple. Should we?
693 * XXX Consult the spec...
694 */
695 pba.pba_iot = ca->ca_iot;
696 pba.pba_memt = ca->ca_memt;
697 pba.pba_dmat = ca->ca_dmat;
698 pba.pba_pc = psc->sc_pc;
699 pba.pba_flags = PCI_FLAGS_IO_OKAY|PCI_FLAGS_MEM_OKAY;
700 pba.pba_bus = PPB_BUSINFO_SECONDARY(busdata);
701 pba.pba_bridgetag = &csc->sc_tag;
702 /*pba.pba_intrswiz = parent_sc->sc_intrswiz; */
703 pba.pba_intrtag = psc->sc_pa.pa_intrtag;
704
705 config_found_ia(self, "pcibus", &pba, rppbprint);
706 }
707
708 int
709 ppb_activate(device_t self, enum devact act)
710 {
711 printf("ppb_activate called\n");
712 return 0;
713 }
714
715