Home | History | Annotate | Line # | Download | only in cardbus
rbus_ppb.c revision 1.44
      1 /*	$NetBSD: rbus_ppb.c,v 1.44 2015/04/13 16:33:24 riastradh Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 1999 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Michael Richardson <mcr (at) sandelman.ottawa.on.ca>
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  * POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 /*
     33  * CardBus front-end for the Intel/Digital DECchip 21152 PCI-PCI bridge
     34  */
     35 
     36 #include <sys/cdefs.h>
     37 __KERNEL_RCSID(0, "$NetBSD: rbus_ppb.c,v 1.44 2015/04/13 16:33:24 riastradh Exp $");
     38 
     39 #include <sys/param.h>
     40 #include <sys/systm.h>
     41 #include <sys/mbuf.h>
     42 #include <sys/malloc.h>
     43 #include <sys/kernel.h>
     44 #include <sys/socket.h>
     45 #include <sys/ioctl.h>
     46 #include <sys/errno.h>
     47 #include <sys/device.h>
     48 #include <sys/kmem.h>
     49 
     50 #include <machine/endian.h>
     51 
     52 #include <sys/bus.h>
     53 #include <sys/intr.h>
     54 
     55 #include <dev/pci/pcivar.h>
     56 #include <dev/pci/pcireg.h>
     57 #include <dev/pci/pcidevs.h>
     58 #include <dev/pci/ppbreg.h>
     59 
     60 #include <dev/ic/i82365reg.h>
     61 
     62 #include <dev/cardbus/rbus.h>
     63 #include <dev/pci/pccbbreg.h>
     64 #include <dev/pci/pccbbvar.h>
     65 
     66 #include <dev/cardbus/cardbusvar.h>
     67 #include <dev/pci/pcidevs.h>
     68 
     69 #include <x86/pci/pci_addr_fixup.h>
     70 #include <x86/pci/pci_bus_fixup.h>
     71 #include <i386/pci/pci_intr_fixup.h>
     72 #include <i386/pci/pcibios.h>
     73 
     74 struct ppb_softc;
     75 
     76 static int  ppb_cardbus_match(device_t, cfdata_t, void *);
     77 static void ppb_cardbus_attach(device_t, device_t, void *);
     78 static int  ppb_activate(device_t, enum devact);
     79 int rppbprint(void *, const char *);
     80 int rbus_intr_fixup(pci_chipset_tag_t, int, int, int);
     81 void rbus_do_header_fixup(pci_chipset_tag_t, pcitag_t, void *);
     82 
     83 static void rbus_pci_phys_allocate(pci_chipset_tag_t, pcitag_t, void *);
     84 
     85 static int rbus_do_phys_allocate(pci_chipset_tag_t, pcitag_t, int,
     86 				 void *, int, bus_addr_t *, bus_size_t);
     87 
     88 static void rbus_pci_phys_countspace(pci_chipset_tag_t, pcitag_t, void *);
     89 
     90 static int rbus_do_phys_countspace(pci_chipset_tag_t, pcitag_t, int,
     91 				   void *, int, bus_addr_t *, bus_size_t);
     92 
     93 unsigned int rbus_round_up(unsigned int, unsigned int);
     94 
     95 
     96 struct ppb_cardbus_softc {
     97   device_t sc_dev;
     98   pcitag_t sc_tag;
     99   int foo;
    100 };
    101 
    102 CFATTACH_DECL_NEW(rbus_ppb, sizeof(struct ppb_cardbus_softc),
    103     ppb_cardbus_match, ppb_cardbus_attach, NULL, ppb_activate);
    104 
    105 #ifdef  CBB_DEBUG
    106 int rbus_ppb_debug = 0;   /* hack with kdb */
    107 #define DPRINTF(X) if(rbus_ppb_debug) printf X
    108 #else
    109 #define DPRINTF(X)
    110 #endif
    111 
    112 static int
    113 ppb_cardbus_match(device_t parent, cfdata_t match, void *aux)
    114 {
    115 	struct cardbus_attach_args *ca = aux;
    116 
    117 	if (PCI_VENDOR(ca->ca_id) ==  PCI_VENDOR_DEC &&
    118 	    PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_DEC_21152)
    119 		return (1);
    120 
    121 	if(PCI_CLASS(ca->ca_class) == PCI_CLASS_BRIDGE &&
    122 	   PCI_SUBCLASS(ca->ca_class) == PCI_SUBCLASS_BRIDGE_PCI) {
    123 	  /* XXX */
    124 	  printf("recognizing generic bridge chip\n");
    125 	}
    126 
    127 	return (0);
    128 }
    129 
    130 
    131 int
    132 rppbprint(void *aux, const char *pnp)
    133 {
    134 	struct pcibus_attach_args *pba = aux;
    135 
    136 	/* only PCIs can attach to PPBs; easy. */
    137 	if (pnp)
    138 		aprint_normal("pci at %s", pnp);
    139 	aprint_normal(" bus %d (rbus)", pba->pba_bus);
    140 	return (UNCONF);
    141 }
    142 
    143 int
    144 rbus_intr_fixup(pci_chipset_tag_t pc,
    145 		int minbus,
    146 		int maxbus,
    147 		int line)
    148 {
    149   pci_device_foreach_min(pc, minbus,
    150 			 maxbus, rbus_do_header_fixup, (void *)&line);
    151   return 0;
    152 }
    153 
    154 void
    155 rbus_do_header_fixup(pci_chipset_tag_t pc, pcitag_t tag, void *context)
    156 {
    157   int bus, device, function;
    158   pcireg_t intr;
    159   int *pline = (int *)context;
    160   int line = *pline;
    161 
    162   pci_decompose_tag(pc, tag, &bus, &device, &function);
    163 
    164   intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);
    165 
    166   intr &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT);
    167   intr |= (line << PCI_INTERRUPT_LINE_SHIFT);
    168   pci_conf_write(pc, tag, PCI_INTERRUPT_REG, intr);
    169 
    170 }
    171 
    172 /*
    173  * This function takes a range of PCI bus numbers and
    174  * allocates space for all devices found in this space (the BARs) from
    175  * the rbus space maps (I/O and memory).
    176  *
    177  * It assumes that "rbus" is defined. The whole concept does.
    178  *
    179  * It uses pci_device_foreach_min() to call rbus_pci_phys_allocate.
    180  * This function is mostly stolen from
    181  *     pci_addr_fixup.c:pciaddr_resource_reserve.
    182  *
    183  */
    184 struct rbus_pci_addr_fixup_context {
    185   struct ppb_cardbus_softc *csc;
    186   cardbus_chipset_tag_t ct;
    187   struct cardbus_softc *sc;
    188   struct cardbus_attach_args *caa;
    189   int    minbus;
    190   int    maxbus;
    191   bus_size_t  *bussize_ioreqs;
    192   bus_size_t  *bussize_memreqs;
    193   rbus_tag_t   *iobustags;
    194   rbus_tag_t   *membustags;
    195 };
    196 
    197 unsigned int
    198 rbus_round_up(unsigned int size, unsigned int minval)
    199 {
    200   unsigned int power2;
    201 
    202   if(size == 0) {
    203     return 0;
    204   }
    205 
    206   power2=minval;
    207 
    208   while(power2 < (1 << 31) &&
    209 	power2 < size) {
    210     power2 = power2 << 1;
    211   }
    212 
    213   return power2;
    214 }
    215 
    216 static void
    217 rbus_pci_addr_fixup(struct ppb_cardbus_softc *csc,
    218 		    cardbus_chipset_tag_t ct,
    219 		    struct cardbus_softc *sc,
    220 		    pci_chipset_tag_t     pc,
    221 		    struct cardbus_attach_args *caa,
    222 		    int minbus, const int maxbus)
    223 {
    224 	struct rbus_pci_addr_fixup_context rct;
    225 	const size_t size = sizeof(bus_size_t[maxbus+1]);
    226 	int busnum;
    227 	bus_addr_t start;
    228 	bus_space_handle_t handle;
    229 	u_int32_t reg;
    230 
    231 	rct.csc=csc;
    232 	rct.ct=ct;
    233 	rct.sc=sc;
    234 	rct.caa=caa;
    235 	rct.minbus = minbus;
    236 	rct.maxbus = maxbus;
    237 	if ((rct.bussize_ioreqs  = kmem_zalloc(size, KM_SLEEP)) == NULL ||
    238 	    (rct.bussize_memreqs = kmem_zalloc(size, KM_SLEEP)) == NULL ||
    239 	    (rct.iobustags =
    240 	     kmem_zalloc(maxbus * sizeof(rbus_tag_t), KM_SLEEP)) == NULL ||
    241 	    (rct.membustags =
    242 	     kmem_zalloc(maxbus * sizeof(rbus_tag_t), KM_SLEEP)) == NULL)
    243 		panic("%s: memory allocation failed", __func__);
    244 
    245 	printf("%s: sizing buses %d-%d\n",
    246 	       device_xname(rct.csc->sc_dev),
    247 	       minbus, maxbus);
    248 
    249 	pci_device_foreach_min(pc, minbus, maxbus,
    250 			       rbus_pci_phys_countspace, &rct);
    251 
    252 	/*
    253 	 * we need to determine amount of address space for each
    254 	 * bus. To do this, we have to roll up amounts and then
    255 	 * we need to divide up the cardbus's extent to allocate
    256 	 * some space to each bus.
    257 	 */
    258 
    259 	for(busnum=maxbus; busnum > minbus; busnum--) {
    260 	  if(pci_bus_parent[busnum] != 0) {
    261 	    if(pci_bus_parent[busnum] < minbus ||
    262 	       pci_bus_parent[busnum] >= maxbus) {
    263 	      printf("%s: bus %d has illegal parent %d\n",
    264 		     device_xname(rct.csc->sc_dev),
    265 		     busnum, pci_bus_parent[busnum]);
    266 	      continue;
    267 	    }
    268 
    269 	    /* first round amount of space up */
    270 	    rct.bussize_ioreqs[busnum] =
    271 	      rbus_round_up(rct.bussize_ioreqs[busnum],  PPB_IO_MIN);
    272 	    rct.bussize_ioreqs[pci_bus_parent[busnum]] +=
    273 	      rct.bussize_ioreqs[busnum];
    274 
    275 	    rct.bussize_memreqs[busnum] =
    276 	      rbus_round_up(rct.bussize_memreqs[busnum], PPB_MEM_MIN);
    277 	    rct.bussize_memreqs[pci_bus_parent[busnum]] +=
    278 	      rct.bussize_memreqs[busnum];
    279 
    280 	  }
    281 	}
    282 
    283 	rct.bussize_ioreqs[minbus] =
    284 	  rbus_round_up(rct.bussize_ioreqs[minbus], 4096);
    285 	rct.bussize_memreqs[minbus] =
    286 	  rbus_round_up(rct.bussize_memreqs[minbus], 8);
    287 
    288 	printf("%s: total needs IO %08zx and MEM %08zx\n",
    289 	       device_xname(rct.csc->sc_dev),
    290 	       rct.bussize_ioreqs[minbus], rct.bussize_memreqs[minbus]);
    291 
    292 	if(!caa->ca_rbus_iot) {
    293 	  panic("no iot bus");
    294 	}
    295 
    296 	if(rct.bussize_ioreqs[minbus]) {
    297 	  if(rbus_space_alloc(caa->ca_rbus_iot, 0,
    298 			      rct.bussize_ioreqs[minbus],
    299 			      rct.bussize_ioreqs[minbus]-1 /* mask  */,
    300 			      rct.bussize_ioreqs[minbus] /* align */,
    301 			      /* flags */ 0,
    302 			      &start,
    303 			      &handle) != 0) {
    304 	    panic("rbus_ppb: can not allocate %zu bytes in IO bus %d",
    305 		  rct.bussize_ioreqs[minbus], minbus);
    306 	  }
    307 	  rct.iobustags[minbus]=rbus_new(caa->ca_rbus_iot,
    308 					 start,
    309 					 rct.bussize_ioreqs[minbus],
    310 					 0 /* offset to add to physical address
    311 					      to make processor address */,
    312 					 RBUS_SPACE_DEDICATE);
    313 	}
    314 
    315 	if(rct.bussize_memreqs[minbus]) {
    316 	  if(rbus_space_alloc(caa->ca_rbus_memt, 0,
    317 			      rct.bussize_memreqs[minbus],
    318 			      rct.bussize_memreqs[minbus]-1 /* mask */,
    319 			      rct.bussize_memreqs[minbus] /* align */,
    320 			      /* flags */ 0,
    321 			      &start,
    322 			      &handle) != 0) {
    323 	    panic("%s: can not allocate %zu bytes in MEM bus %d",
    324 		  device_xname(rct.csc->sc_dev),
    325 		  rct.bussize_memreqs[minbus], minbus);
    326 	  }
    327 	  rct.membustags[minbus]=rbus_new(caa->ca_rbus_memt,
    328 					  start,
    329 					  rct.bussize_memreqs[minbus],
    330 					  0 /* offset to add to physical
    331 					       address to make processor
    332 					       address */,
    333 					  RBUS_SPACE_DEDICATE);
    334 	}
    335 
    336 	for(busnum=minbus+1; busnum <= maxbus; busnum++) {
    337 	  int busparent;
    338 
    339 	  busparent = pci_bus_parent[busnum];
    340 
    341 	  printf("%s: bus %d (parent=%d) needs IO %08zx and MEM %08zx\n",
    342 		 device_xname(rct.csc->sc_dev),
    343 		 busnum,
    344 		 busparent,
    345 		 rct.bussize_ioreqs[busnum],
    346 		 rct.bussize_memreqs[busnum]);
    347 
    348 	  if(busparent > maxbus) {
    349 	    panic("rbus_ppb: illegal parent");
    350 	  }
    351 
    352 	  if(rct.bussize_ioreqs[busnum]) {
    353 	    if(rbus_space_alloc(rct.iobustags[busparent],
    354 				0,
    355 				rct.bussize_ioreqs[busnum],
    356 				rct.bussize_ioreqs[busnum]-1 /*mask */,
    357 				rct.bussize_ioreqs[busnum] /* align */,
    358 				/* flags */ 0,
    359 				&start,
    360 				&handle) != 0) {
    361 	      panic("rbus_ppb: can not allocate %zu bytes in IO bus %d",
    362 		    rct.bussize_ioreqs[busnum], busnum);
    363 	    }
    364 	    rct.iobustags[busnum]=rbus_new(rct.iobustags[busparent],
    365 					   start,
    366 					   rct.bussize_ioreqs[busnum],
    367 					   0 /* offset to add to physical
    368 						address
    369 						to make processor address */,
    370 					   RBUS_SPACE_DEDICATE);
    371 
    372 	    /* program the bridge */
    373 
    374 	    /* enable I/O space */
    375 	    reg = pci_conf_read(pc, pci_bus_tag[busnum],
    376 				PCI_COMMAND_STATUS_REG);
    377 	    reg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE;
    378 	    pci_conf_write(pc, pci_bus_tag[busnum],
    379 			   PCI_COMMAND_STATUS_REG, reg);
    380 
    381 	    /* now init the limit register for I/O */
    382 	    pci_conf_write(pc, pci_bus_tag[busnum], PPB_REG_IOSTATUS,
    383 			   (((start & 0xf000) >> 8) << PPB_IOBASE_SHIFT) |
    384 			   ((((start +
    385 			       rct.bussize_ioreqs[busnum] +
    386 			       4095) & 0xf000) >> 8) << PPB_IOLIMIT_SHIFT));
    387 	  }
    388 
    389 	  if(rct.bussize_memreqs[busnum]) {
    390 	    if(rbus_space_alloc(rct.membustags[busparent],
    391 				0,
    392 				rct.bussize_memreqs[busnum] /* size  */,
    393 				rct.bussize_memreqs[busnum]-1 /*mask */,
    394 				rct.bussize_memreqs[busnum] /* align */,
    395 				/* flags */ 0,
    396 				&start,
    397 				&handle) != 0) {
    398 	      panic("rbus_ppb: can not allocate %zu bytes in MEM bus %d",
    399 		    rct.bussize_memreqs[busnum], busnum);
    400 	    }
    401 	    rct.membustags[busnum]=rbus_new(rct.membustags[busparent],
    402 					    start,
    403 					    rct.bussize_memreqs[busnum],
    404 					    0 /* offset to add to physical
    405 						 address to make processor
    406 						 address */,
    407 					    RBUS_SPACE_DEDICATE);
    408 
    409 	    /* program the bridge */
    410 	    /* enable memory space */
    411 	    reg = pci_conf_read(pc, pci_bus_tag[busnum],
    412 				PCI_COMMAND_STATUS_REG);
    413 	    reg |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE;
    414 	    pci_conf_write(pc, pci_bus_tag[busnum],
    415 			   PCI_COMMAND_STATUS_REG, reg);
    416 
    417 	    /* now init the limit register for memory */
    418 	    pci_conf_write(pc, pci_bus_tag[busnum], PPB_REG_MEM,
    419 			   ((start & PPB_MEM_MASK)
    420 			    >> PPB_MEM_SHIFT) << PPB_MEMBASE_SHIFT |
    421 			   (((start +
    422 			     rct.bussize_memreqs[busnum] +
    423 			      PPB_MEM_MIN-1) >> PPB_MEM_SHIFT)
    424 			    << PPB_MEMLIMIT_SHIFT));
    425 
    426 	    /* and set the prefetchable limits as well */
    427 	    pci_conf_write(pc, pci_bus_tag[busnum], PPB_REG_PREFMEM,
    428 			   ((start & PPB_MEM_MASK)
    429 			    >> PPB_MEM_SHIFT) << PPB_MEMBASE_SHIFT |
    430 			   (((start +
    431 			     rct.bussize_memreqs[busnum] +
    432 			      PPB_MEM_MIN-1) >> PPB_MEM_SHIFT)
    433 			    << PPB_MEMLIMIT_SHIFT));
    434 
    435 	    /* pci_conf_print(pc, pci_bus_tag[busnum], NULL); */
    436 	  }
    437 	}
    438 
    439 	printf("%s: configuring buses %d-%d\n",
    440 		device_xname(rct.csc->sc_dev),
    441 	       minbus, maxbus);
    442 	pci_device_foreach_min(pc, minbus, maxbus,
    443 			       rbus_pci_phys_allocate, &rct);
    444 
    445 	kmem_free(rct.bussize_ioreqs, size);
    446 	kmem_free(rct.bussize_memreqs, size);
    447 	kmem_free(rct.iobustags, maxbus * sizeof(rbus_tag_t));
    448 	kmem_free(rct.membustags, maxbus * sizeof(rbus_tag_t));
    449 }
    450 
    451 static void
    452 rbus_pci_phys_countspace(pci_chipset_tag_t pc, pcitag_t tag, void *context)
    453 {
    454         int bus, device, function;
    455 	struct  rbus_pci_addr_fixup_context *rct =
    456 	  (struct  rbus_pci_addr_fixup_context *)context;
    457 
    458 	pci_decompose_tag(pc, tag, &bus, &device, &function);
    459 
    460 	printf("%s: configuring device %02x:%02x:%02x\n",
    461 	       device_xname(rct->csc->sc_dev),
    462 	       bus, device, function);
    463 
    464 	pciaddr_resource_manage(pc, tag,
    465 				rbus_do_phys_countspace, context);
    466 }
    467 
    468 
    469 int
    470 rbus_do_phys_countspace(pci_chipset_tag_t pc, pcitag_t tag, int mapreg, void *ctx, int type, bus_addr_t *addr, bus_size_t size)
    471 {
    472 	struct  rbus_pci_addr_fixup_context *rct =
    473 	  (struct  rbus_pci_addr_fixup_context *)ctx;
    474 	int bus, device, function;
    475 
    476 	pci_decompose_tag(pc, tag, &bus, &device, &function);
    477 
    478 	if(size > (1<<24)) {
    479 	  printf("%s: skipping huge space request of size=%08x\n",
    480 		 device_xname(rct->csc->sc_dev), (unsigned int)size);
    481 	  return 0;
    482 	}
    483 
    484 	if(PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_IO) {
    485 	  rct->bussize_ioreqs[bus] += size;
    486 	} else {
    487 	  rct->bussize_memreqs[bus]+= size;
    488 	}
    489 
    490 	return 0;
    491 }
    492 
    493 static void
    494 rbus_pci_phys_allocate(pci_chipset_tag_t pc, pcitag_t tag, void *context)
    495 {
    496         int bus, device, function, command;
    497 	struct rbus_pci_addr_fixup_context *rct =
    498 	  (struct rbus_pci_addr_fixup_context *)context;
    499 
    500 	pci_decompose_tag(pc, tag, &bus, &device, &function);
    501 
    502 	printf("%s: configuring device %02x:%02x:%02x\n",
    503 	       device_xname(rct->csc->sc_dev),
    504 	       bus, device, function);
    505 
    506 	pciaddr_resource_manage(pc, tag,
    507 				rbus_do_phys_allocate, context);
    508 
    509 	/* now turn the device's memory and I/O on */
    510 	command = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
    511 	command |= PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE;
    512 	pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, command);
    513 }
    514 
    515 int
    516 rbus_do_phys_allocate(pci_chipset_tag_t pc, pcitag_t tag, int mapreg, void *ctx, int type, bus_addr_t *addr, bus_size_t size)
    517 {
    518 	struct  rbus_pci_addr_fixup_context *rct =
    519 	  (struct  rbus_pci_addr_fixup_context *)ctx;
    520 	cardbus_chipset_tag_t ct     = rct->ct;
    521 	struct cardbus_softc *sc     = rct->sc;
    522 	cardbus_function_t       *cf = sc->sc_cf;
    523 	rbus_tag_t          rbustag;
    524 	bus_addr_t mask = size -1;
    525 	bus_addr_t base = 0;
    526 	bus_space_handle_t handle;
    527 	int busflags = 0;
    528 	int flags    = 0;
    529 	const char *bustype;
    530 	int bus, device, function;
    531 
    532 	pci_decompose_tag(pc, tag, &bus, &device, &function);
    533 
    534 	/*
    535 	 * some devices come up with garbage in them (Tulip?)
    536 	 * we are in charge here, so give them address
    537 	 * space anyway.
    538 	 *
    539 	 * XXX this may be due to no secondary PCI reset!!!
    540 	 */
    541 #if 0
    542 	if (*addr) {
    543 		printf("Already allocated space at %08x\n",
    544 		       (unsigned int)*addr);
    545 		return (0);
    546 	}
    547 #endif
    548 
    549 	if(size > (1<<24)) {
    550 	  printf("%s: skipping huge space request of size=%08x\n",
    551 		 device_xname(rct->csc->sc_dev), (unsigned int)size);
    552 	  return 0;
    553 	}
    554 
    555 	if(PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_IO) {
    556 	  rbustag = rct->iobustags[bus];
    557 	  bustype = "io";
    558 	} else {
    559 	  rbustag = rct->membustags[bus];
    560 	  bustype = "mem";
    561 	}
    562 
    563 	if((*cf->cardbus_space_alloc)(ct, rbustag, base, size,
    564 				      mask, size, busflags|flags,
    565 				      addr, &handle)) {
    566 	  printf("%s: no available resources (size=%08x) for bar %2d. fixup failed\n",
    567 		 device_xname(rct->csc->sc_dev), (unsigned int)size, mapreg);
    568 
    569 	  *addr = 0;
    570 	  pci_conf_write(pc, tag, mapreg, *addr);
    571 	  return (1);
    572 	}
    573 
    574 	printf("%s: alloc %s space of size %08x for %02d:%02d:%02d -> %08x\n",
    575 	       device_xname(rct->csc->sc_dev),
    576 	       bustype,
    577 	       (unsigned int)size,
    578 	       bus, device, function, (unsigned int)*addr);
    579 
    580 	/* write new address to PCI device configuration header */
    581 	pci_conf_write(pc, tag, mapreg, *addr);
    582 
    583 	/* check */
    584 	{
    585 		DPRINTF(("%s: pci_addr_fixup: ",
    586 			 device_xname(rct->csc->sc_dev)));
    587 #ifdef  CBB_DEBUG
    588 		if(rbus_ppb_debug) { pciaddr_print_devid(pc, tag); }
    589 #endif
    590 	}
    591 
    592 	/* double check that the value got inserted correctly */
    593 	if (pciaddr_ioaddr(pci_conf_read(pc, tag, mapreg)) != *addr) {
    594 		pci_conf_write(pc, tag, mapreg, 0); /* clear */
    595 		printf("%s: fixup failed. (new address=%#x)\n",
    596 		       device_xname(rct->csc->sc_dev),
    597 		       (unsigned)*addr);
    598 		return (1);
    599 	}
    600 
    601 	DPRINTF(("new address 0x%08x\n",
    602 		 (unsigned)*addr));
    603 
    604 	return (0);
    605 }
    606 
    607 static void
    608 ppb_cardbus_attach(device_t parent, device_t self, void *aux)
    609 {
    610 	struct ppb_cardbus_softc *csc = device_private(self);
    611 	struct cardbus_softc *parent_sc = device_private(parent);
    612 	struct cardbus_attach_args *ca = aux;
    613 	cardbus_devfunc_t ct = ca->ca_ct;
    614 	cardbus_chipset_tag_t cc = ct->ct_cc;
    615 	struct pccbb_softc *psc = (struct pccbb_softc *)cc;
    616 	struct pcibus_attach_args pba;
    617 	char devinfo[256];
    618 	pcireg_t busdata;
    619 	int minbus, maxbus;
    620 
    621 	csc->sc_dev = self;
    622 
    623 	pci_devinfo(ca->ca_id, ca->ca_class, 0, devinfo, sizeof(devinfo));
    624 	printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(ca->ca_class));
    625 
    626 	csc->sc_tag = ca->ca_tag;
    627 
    628 	busdata = Cardbus_conf_read(ct, ca->ca_tag, PPB_REG_BUSINFO);
    629 	minbus = pcibios_max_bus;
    630 	maxbus = minbus;		/* XXX; gcc */
    631 
    632 	if (PPB_BUSINFO_SECONDARY(busdata) == 0) {
    633 		aprint_error_dev(self, "not configured by system firmware calling pci_bus_fixup(%d)\n", 0);
    634 
    635 	  /*
    636 	   * first, pull the reset wire on the secondary bridge
    637 	   * to clear all devices
    638 	   */
    639 	  busdata = Cardbus_conf_read(ct, ca->ca_tag,
    640 				      PPB_REG_BRIDGECONTROL);
    641 	  Cardbus_conf_write(ct, ca->ca_tag, PPB_REG_BRIDGECONTROL,
    642 			     busdata | PPB_BC_SECONDARY_RESET);
    643 	  delay(1);
    644 	  Cardbus_conf_write(ct, ca->ca_tag, PPB_REG_BRIDGECONTROL,
    645 			     busdata);
    646 
    647 	  /* then go initialize the bridge control registers */
    648 	  maxbus = pci_bus_fixup(psc->sc_pc, 0);
    649 	}
    650 
    651 	busdata = Cardbus_conf_read(ct, ca->ca_tag, PPB_REG_BUSINFO);
    652 	if(PPB_BUSINFO_SECONDARY(busdata) == 0) {
    653 		aprint_error_dev(self, "still not configured, not fixable.\n");
    654 		return;
    655 	}
    656 
    657 #if 0
    658 	minbus = PPB_BUSINFO_SECONDARY(busdata);
    659 	maxbus = PPB_BUSINFO_SUBORDINATE(busdata);
    660 #endif
    661 
    662 	/* now, go and assign addresses for the new devices */
    663 	rbus_pci_addr_fixup(csc, cc, parent_sc,
    664 			    psc->sc_pc,
    665 			    ca,
    666 			    minbus, maxbus);
    667 
    668 	/*
    669 	 * now configure all connected devices to the IRQ which
    670 	 * was assigned to this slot, as they will all arrive from
    671 	 * that IRQ.
    672 	 */
    673 	rbus_intr_fixup(psc->sc_pc, minbus, maxbus, 0);
    674 
    675 	/*
    676 	 * enable direct routing of interrupts. We do this because
    677 	 * we can not manage to get pccb_intr_establish() called until
    678 	 * PCI subsystem is merged with rbus. The major thing that this
    679 	 * routine does is avoid calling the driver's interrupt routine
    680 	 * when the card has been removed.
    681 	 *
    682 	 * The rbus_ppb.c can not cope with card desertions until the merging
    683 	 * anyway.
    684 	 */
    685 	pccbb_intr_route(psc);
    686 
    687 	/*
    688 	 * Attach the PCI bus than hangs off of it.
    689 	 *
    690 	 * XXX Don't pass-through Memory Read Multiple.  Should we?
    691 	 * XXX Consult the spec...
    692 	 */
    693 	pba.pba_iot  = ca->ca_iot;
    694 	pba.pba_memt = ca->ca_memt;
    695 	pba.pba_dmat = ca->ca_dmat;
    696 	pba.pba_pc   = psc->sc_pc;
    697 	pba.pba_flags    = PCI_FLAGS_IO_OKAY|PCI_FLAGS_MEM_OKAY;
    698 	pba.pba_bus      = PPB_BUSINFO_SECONDARY(busdata);
    699 	pba.pba_bridgetag = &csc->sc_tag;
    700 	/*pba.pba_intrswiz = parent_sc->sc_intrswiz; */
    701 	pba.pba_intrtag  = psc->sc_pa.pa_intrtag;
    702 
    703 	config_found_ia(self, "pcibus", &pba, rppbprint);
    704 }
    705 
    706 int
    707 ppb_activate(device_t self, enum devact act)
    708 {
    709   printf("ppb_activate called\n");
    710   return 0;
    711 }
    712 
    713