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rbus_ppb.c revision 1.46
      1 /*	$NetBSD: rbus_ppb.c,v 1.46 2019/03/01 09:26:00 msaitoh Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 1999 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Michael Richardson <mcr (at) sandelman.ottawa.on.ca>
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  * POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 /*
     33  * CardBus front-end for the Intel/Digital DECchip 21152 PCI-PCI bridge
     34  */
     35 
     36 #include <sys/cdefs.h>
     37 __KERNEL_RCSID(0, "$NetBSD: rbus_ppb.c,v 1.46 2019/03/01 09:26:00 msaitoh Exp $");
     38 
     39 #include <sys/param.h>
     40 #include <sys/systm.h>
     41 #include <sys/mbuf.h>
     42 #include <sys/malloc.h>
     43 #include <sys/kernel.h>
     44 #include <sys/socket.h>
     45 #include <sys/ioctl.h>
     46 #include <sys/errno.h>
     47 #include <sys/device.h>
     48 #include <sys/kmem.h>
     49 
     50 #include <machine/endian.h>
     51 
     52 #include <sys/bus.h>
     53 #include <sys/intr.h>
     54 
     55 #include <dev/pci/pcivar.h>
     56 #include <dev/pci/pcireg.h>
     57 #include <dev/pci/pcidevs.h>
     58 #include <dev/pci/ppbreg.h>
     59 
     60 #include <dev/ic/i82365reg.h>
     61 
     62 #include <dev/cardbus/rbus.h>
     63 #include <dev/pci/pccbbreg.h>
     64 #include <dev/pci/pccbbvar.h>
     65 
     66 #include <dev/cardbus/cardbusvar.h>
     67 #include <dev/pci/pcidevs.h>
     68 
     69 #include <x86/pci/pci_addr_fixup.h>
     70 #include <x86/pci/pci_bus_fixup.h>
     71 #include <i386/pci/pci_intr_fixup.h>
     72 #include <i386/pci/pcibios.h>
     73 
     74 struct ppb_softc;
     75 
     76 static int  ppb_cardbus_match(device_t, cfdata_t, void *);
     77 static void ppb_cardbus_attach(device_t, device_t, void *);
     78 static int  ppb_activate(device_t, enum devact);
     79 int rppbprint(void *, const char *);
     80 int rbus_intr_fixup(pci_chipset_tag_t, int, int, int);
     81 void rbus_do_header_fixup(pci_chipset_tag_t, pcitag_t, void *);
     82 
     83 static void rbus_pci_phys_allocate(pci_chipset_tag_t, pcitag_t, void *);
     84 
     85 static int rbus_do_phys_allocate(pci_chipset_tag_t, pcitag_t, int,
     86 				 void *, int, bus_addr_t *, bus_size_t);
     87 
     88 static void rbus_pci_phys_countspace(pci_chipset_tag_t, pcitag_t, void *);
     89 
     90 static int rbus_do_phys_countspace(pci_chipset_tag_t, pcitag_t, int,
     91 				   void *, int, bus_addr_t *, bus_size_t);
     92 
     93 unsigned int rbus_round_up(unsigned int, unsigned int);
     94 
     95 
     96 struct ppb_cardbus_softc {
     97   device_t sc_dev;
     98   pcitag_t sc_tag;
     99   int foo;
    100 };
    101 
    102 CFATTACH_DECL_NEW(rbus_ppb, sizeof(struct ppb_cardbus_softc),
    103     ppb_cardbus_match, ppb_cardbus_attach, NULL, ppb_activate);
    104 
    105 #ifdef  CBB_DEBUG
    106 int rbus_ppb_debug = 0;   /* hack with kdb */
    107 #define DPRINTF(X) if(rbus_ppb_debug) printf X
    108 #else
    109 #define DPRINTF(X)
    110 #endif
    111 
    112 static int
    113 ppb_cardbus_match(device_t parent, cfdata_t match, void *aux)
    114 {
    115 	struct cardbus_attach_args *ca = aux;
    116 
    117 	if (PCI_VENDOR(ca->ca_id) ==  PCI_VENDOR_DEC &&
    118 	    PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_DEC_21152)
    119 		return (1);
    120 
    121 	if(PCI_CLASS(ca->ca_class) == PCI_CLASS_BRIDGE &&
    122 	   PCI_SUBCLASS(ca->ca_class) == PCI_SUBCLASS_BRIDGE_PCI) {
    123 	  /* XXX */
    124 	  printf("recognizing generic bridge chip\n");
    125 	}
    126 
    127 	return (0);
    128 }
    129 
    130 
    131 int
    132 rppbprint(void *aux, const char *pnp)
    133 {
    134 	struct pcibus_attach_args *pba = aux;
    135 
    136 	/* only PCIs can attach to PPBs; easy. */
    137 	if (pnp)
    138 		aprint_normal("pci at %s", pnp);
    139 	aprint_normal(" bus %d (rbus)", pba->pba_bus);
    140 	return (UNCONF);
    141 }
    142 
    143 int
    144 rbus_intr_fixup(pci_chipset_tag_t pc,
    145 		int minbus,
    146 		int maxbus,
    147 		int line)
    148 {
    149   pci_device_foreach_min(pc, minbus,
    150 			 maxbus, rbus_do_header_fixup, (void *)&line);
    151   return 0;
    152 }
    153 
    154 void
    155 rbus_do_header_fixup(pci_chipset_tag_t pc, pcitag_t tag, void *context)
    156 {
    157   int bus, device, function;
    158   pcireg_t intr;
    159   int *pline = (int *)context;
    160   int line = *pline;
    161 
    162   pci_decompose_tag(pc, tag, &bus, &device, &function);
    163 
    164   intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);
    165 
    166   intr &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT);
    167   intr |= (line << PCI_INTERRUPT_LINE_SHIFT);
    168   pci_conf_write(pc, tag, PCI_INTERRUPT_REG, intr);
    169 
    170 }
    171 
    172 /*
    173  * This function takes a range of PCI bus numbers and
    174  * allocates space for all devices found in this space (the BARs) from
    175  * the rbus space maps (I/O and memory).
    176  *
    177  * It assumes that "rbus" is defined. The whole concept does.
    178  *
    179  * It uses pci_device_foreach_min() to call rbus_pci_phys_allocate.
    180  * This function is mostly stolen from
    181  *     pci_addr_fixup.c:pciaddr_resource_reserve.
    182  *
    183  */
    184 struct rbus_pci_addr_fixup_context {
    185   struct ppb_cardbus_softc *csc;
    186   cardbus_chipset_tag_t ct;
    187   struct cardbus_softc *sc;
    188   struct cardbus_attach_args *caa;
    189   int    minbus;
    190   int    maxbus;
    191   bus_size_t  *bussize_ioreqs;
    192   bus_size_t  *bussize_memreqs;
    193   rbus_tag_t   *iobustags;
    194   rbus_tag_t   *membustags;
    195 };
    196 
    197 unsigned int
    198 rbus_round_up(unsigned int size, unsigned int minval)
    199 {
    200   unsigned int power2;
    201 
    202   if(size == 0) {
    203     return 0;
    204   }
    205 
    206   power2=minval;
    207 
    208   while(power2 < (1 << 31) &&
    209 	power2 < size) {
    210     power2 = power2 << 1;
    211   }
    212 
    213   return power2;
    214 }
    215 
    216 static void
    217 rbus_pci_addr_fixup(struct ppb_cardbus_softc *csc,
    218 		    cardbus_chipset_tag_t ct,
    219 		    struct cardbus_softc *sc,
    220 		    pci_chipset_tag_t     pc,
    221 		    struct cardbus_attach_args *caa,
    222 		    int minbus, const int maxbus)
    223 {
    224 	struct rbus_pci_addr_fixup_context rct;
    225 	const size_t size = sizeof(bus_size_t[maxbus+1]);
    226 	int busnum;
    227 	bus_addr_t start;
    228 	bus_space_handle_t handle;
    229 	u_int32_t reg;
    230 
    231 	rct.csc=csc;
    232 	rct.ct=ct;
    233 	rct.sc=sc;
    234 	rct.caa=caa;
    235 	rct.minbus = minbus;
    236 	rct.maxbus = maxbus;
    237 	rct.bussize_ioreqs = kmem_zalloc(size, KM_SLEEP);
    238 	rct.bussize_memreqs = kmem_zalloc(size, KM_SLEEP);
    239 	rct.iobustags = kmem_zalloc(maxbus * sizeof(rbus_tag_t), KM_SLEEP);
    240 	rct.membustags = kmem_zalloc(maxbus * sizeof(rbus_tag_t), KM_SLEEP);
    241 
    242 	printf("%s: sizing buses %d-%d\n",
    243 	       device_xname(rct.csc->sc_dev),
    244 	       minbus, maxbus);
    245 
    246 	pci_device_foreach_min(pc, minbus, maxbus,
    247 			       rbus_pci_phys_countspace, &rct);
    248 
    249 	/*
    250 	 * we need to determine amount of address space for each
    251 	 * bus. To do this, we have to roll up amounts and then
    252 	 * we need to divide up the cardbus's extent to allocate
    253 	 * some space to each bus.
    254 	 */
    255 
    256 	for(busnum=maxbus; busnum > minbus; busnum--) {
    257 	  if(pci_bus_parent[busnum] != 0) {
    258 	    if(pci_bus_parent[busnum] < minbus ||
    259 	       pci_bus_parent[busnum] >= maxbus) {
    260 	      printf("%s: bus %d has illegal parent %d\n",
    261 		     device_xname(rct.csc->sc_dev),
    262 		     busnum, pci_bus_parent[busnum]);
    263 	      continue;
    264 	    }
    265 
    266 	    /* first round amount of space up */
    267 	    rct.bussize_ioreqs[busnum] =
    268 	      rbus_round_up(rct.bussize_ioreqs[busnum],  PCI_BRIDGE_IO_MIN);
    269 	    rct.bussize_ioreqs[pci_bus_parent[busnum]] +=
    270 	      rct.bussize_ioreqs[busnum];
    271 
    272 	    rct.bussize_memreqs[busnum] =
    273 	      rbus_round_up(rct.bussize_memreqs[busnum], PCI_BRIDGE_MEM_MIN);
    274 	    rct.bussize_memreqs[pci_bus_parent[busnum]] +=
    275 	      rct.bussize_memreqs[busnum];
    276 
    277 	  }
    278 	}
    279 
    280 	rct.bussize_ioreqs[minbus] =
    281 	  rbus_round_up(rct.bussize_ioreqs[minbus], PCI_BRIDGE_IO_MIN);
    282 	rct.bussize_memreqs[minbus] =  /* XXX Not 8 but PCI_BRIDGE_MEM_MIN ? */
    283 	  rbus_round_up(rct.bussize_memreqs[minbus], 8);
    284 
    285 	printf("%s: total needs IO %08zx and MEM %08zx\n",
    286 	       device_xname(rct.csc->sc_dev),
    287 	       rct.bussize_ioreqs[minbus], rct.bussize_memreqs[minbus]);
    288 
    289 	if(!caa->ca_rbus_iot) {
    290 	  panic("no iot bus");
    291 	}
    292 
    293 	if(rct.bussize_ioreqs[minbus]) {
    294 	  if(rbus_space_alloc(caa->ca_rbus_iot, 0,
    295 			      rct.bussize_ioreqs[minbus],
    296 			      rct.bussize_ioreqs[minbus]-1 /* mask  */,
    297 			      rct.bussize_ioreqs[minbus] /* align */,
    298 			      /* flags */ 0,
    299 			      &start,
    300 			      &handle) != 0) {
    301 	    panic("rbus_ppb: can not allocate %zu bytes in IO bus %d",
    302 		  rct.bussize_ioreqs[minbus], minbus);
    303 	  }
    304 	  rct.iobustags[minbus]=rbus_new(caa->ca_rbus_iot,
    305 					 start,
    306 					 rct.bussize_ioreqs[minbus],
    307 					 0 /* offset to add to physical address
    308 					      to make processor address */,
    309 					 RBUS_SPACE_DEDICATE);
    310 	}
    311 
    312 	if(rct.bussize_memreqs[minbus]) {
    313 	  if(rbus_space_alloc(caa->ca_rbus_memt, 0,
    314 			      rct.bussize_memreqs[minbus],
    315 			      rct.bussize_memreqs[minbus]-1 /* mask */,
    316 			      rct.bussize_memreqs[minbus] /* align */,
    317 			      /* flags */ 0,
    318 			      &start,
    319 			      &handle) != 0) {
    320 	    panic("%s: can not allocate %zu bytes in MEM bus %d",
    321 		  device_xname(rct.csc->sc_dev),
    322 		  rct.bussize_memreqs[minbus], minbus);
    323 	  }
    324 	  rct.membustags[minbus]=rbus_new(caa->ca_rbus_memt,
    325 					  start,
    326 					  rct.bussize_memreqs[minbus],
    327 					  0 /* offset to add to physical
    328 					       address to make processor
    329 					       address */,
    330 					  RBUS_SPACE_DEDICATE);
    331 	}
    332 
    333 	for(busnum=minbus+1; busnum <= maxbus; busnum++) {
    334 	  int busparent;
    335 
    336 	  busparent = pci_bus_parent[busnum];
    337 
    338 	  printf("%s: bus %d (parent=%d) needs IO %08zx and MEM %08zx\n",
    339 		 device_xname(rct.csc->sc_dev),
    340 		 busnum,
    341 		 busparent,
    342 		 rct.bussize_ioreqs[busnum],
    343 		 rct.bussize_memreqs[busnum]);
    344 
    345 	  if(busparent > maxbus) {
    346 	    panic("rbus_ppb: illegal parent");
    347 	  }
    348 
    349 	  if(rct.bussize_ioreqs[busnum]) {
    350 	    if(rbus_space_alloc(rct.iobustags[busparent],
    351 				0,
    352 				rct.bussize_ioreqs[busnum],
    353 				rct.bussize_ioreqs[busnum]-1 /*mask */,
    354 				rct.bussize_ioreqs[busnum] /* align */,
    355 				/* flags */ 0,
    356 				&start,
    357 				&handle) != 0) {
    358 	      panic("rbus_ppb: can not allocate %zu bytes in IO bus %d",
    359 		    rct.bussize_ioreqs[busnum], busnum);
    360 	    }
    361 	    rct.iobustags[busnum]=rbus_new(rct.iobustags[busparent],
    362 					   start,
    363 					   rct.bussize_ioreqs[busnum],
    364 					   0 /* offset to add to physical
    365 						address
    366 						to make processor address */,
    367 					   RBUS_SPACE_DEDICATE);
    368 
    369 	    /* program the bridge */
    370 
    371 	    /* enable I/O space */
    372 	    reg = pci_conf_read(pc, pci_bus_tag[busnum],
    373 				PCI_COMMAND_STATUS_REG);
    374 	    reg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE;
    375 	    pci_conf_write(pc, pci_bus_tag[busnum],
    376 			   PCI_COMMAND_STATUS_REG, reg);
    377 
    378 	    /* now init the limit register for I/O */
    379 	    pci_conf_write(pc, pci_bus_tag[busnum], PCI_BRIDGE_STATIO_REG,
    380 		__SHIFTIN((start >> 8)
    381 		    & PCI_BRIDGE_STATIO_IOADDR, PCI_BRIDGE_STATIO_IOBASE) |
    382 		__SHIFTIN(((start + rct.bussize_ioreqs[busnum] + 4095) >> 8)
    383 		    & PCI_BRIDGE_STATIO_IOADDR, PCI_BRIDGE_STATIO_IOLIMIT));
    384 	  }
    385 
    386 	  if(rct.bussize_memreqs[busnum]) {
    387 	    if(rbus_space_alloc(rct.membustags[busparent],
    388 				0,
    389 				rct.bussize_memreqs[busnum] /* size  */,
    390 				rct.bussize_memreqs[busnum]-1 /*mask */,
    391 				rct.bussize_memreqs[busnum] /* align */,
    392 				/* flags */ 0,
    393 				&start,
    394 				&handle) != 0) {
    395 	      panic("rbus_ppb: can not allocate %zu bytes in MEM bus %d",
    396 		    rct.bussize_memreqs[busnum], busnum);
    397 	    }
    398 	    rct.membustags[busnum]=rbus_new(rct.membustags[busparent],
    399 					    start,
    400 					    rct.bussize_memreqs[busnum],
    401 					    0 /* offset to add to physical
    402 						 address to make processor
    403 						 address */,
    404 					    RBUS_SPACE_DEDICATE);
    405 
    406 	    /* program the bridge */
    407 	    /* enable memory space */
    408 	    reg = pci_conf_read(pc, pci_bus_tag[busnum],
    409 				PCI_COMMAND_STATUS_REG);
    410 	    reg |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE;
    411 	    pci_conf_write(pc, pci_bus_tag[busnum],
    412 			   PCI_COMMAND_STATUS_REG, reg);
    413 
    414 	    /* now init the limit register for memory */
    415 	    pci_conf_write(pc, pci_bus_tag[busnum], PCI_BRIDGE_MEMORY_REG,
    416 		__SHIFTIN((start >> 16) & PCI_BRIDGE_MEMORY_ADDR,
    417 		    PCI_BRIDGE_MEMORY_BASE) |
    418 		__SHIFTIN(((start + rct.bussize_memreqs[busnum] + PPB_MEM_MIN
    419 			    - 1) >> 16) & PCI_BRIDGE_MEMORY_ADDR,
    420 		    PCI_BRIDGE_MEMORY_LIMIT));
    421 
    422 	    /* and set the prefetchable limits as well */
    423 	    pci_conf_write(pc, pci_bus_tag[busnum], PCI_BRIDGE_PREFETCHMEM_REG,
    424 		__SHIFTIN((start >> 16) & PCI_BRIDGE_PREFETCHMEM_ADDR,
    425 		    PCI_BRIDGE_PREFETCHMEM_BASE) |
    426 		__SHIFTIN(((start + rct.bussize_memreqs[busnum] + PPB_MEM_MIN
    427 			    - 1) >> 16) & PCI_BRIDGE_PREFETCHMEM_ADDR,
    428 		    PCI_BRIDGE_PREFETCHMEM_LIMIT));
    429 
    430 	    /* pci_conf_print(pc, pci_bus_tag[busnum], NULL); */
    431 	  }
    432 	}
    433 
    434 	printf("%s: configuring buses %d-%d\n",
    435 		device_xname(rct.csc->sc_dev),
    436 	       minbus, maxbus);
    437 	pci_device_foreach_min(pc, minbus, maxbus,
    438 			       rbus_pci_phys_allocate, &rct);
    439 
    440 	kmem_free(rct.bussize_ioreqs, size);
    441 	kmem_free(rct.bussize_memreqs, size);
    442 	kmem_free(rct.iobustags, maxbus * sizeof(rbus_tag_t));
    443 	kmem_free(rct.membustags, maxbus * sizeof(rbus_tag_t));
    444 }
    445 
    446 static void
    447 rbus_pci_phys_countspace(pci_chipset_tag_t pc, pcitag_t tag, void *context)
    448 {
    449         int bus, device, function;
    450 	struct  rbus_pci_addr_fixup_context *rct =
    451 	  (struct  rbus_pci_addr_fixup_context *)context;
    452 
    453 	pci_decompose_tag(pc, tag, &bus, &device, &function);
    454 
    455 	printf("%s: configuring device %02x:%02x:%02x\n",
    456 	       device_xname(rct->csc->sc_dev),
    457 	       bus, device, function);
    458 
    459 	pciaddr_resource_manage(pc, tag,
    460 				rbus_do_phys_countspace, context);
    461 }
    462 
    463 
    464 int
    465 rbus_do_phys_countspace(pci_chipset_tag_t pc, pcitag_t tag, int mapreg, void *ctx, int type, bus_addr_t *addr, bus_size_t size)
    466 {
    467 	struct  rbus_pci_addr_fixup_context *rct =
    468 	  (struct  rbus_pci_addr_fixup_context *)ctx;
    469 	int bus, device, function;
    470 
    471 	pci_decompose_tag(pc, tag, &bus, &device, &function);
    472 
    473 	if(size > (1<<24)) {
    474 	  printf("%s: skipping huge space request of size=%08x\n",
    475 		 device_xname(rct->csc->sc_dev), (unsigned int)size);
    476 	  return 0;
    477 	}
    478 
    479 	if(PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_IO) {
    480 	  rct->bussize_ioreqs[bus] += size;
    481 	} else {
    482 	  rct->bussize_memreqs[bus]+= size;
    483 	}
    484 
    485 	return 0;
    486 }
    487 
    488 static void
    489 rbus_pci_phys_allocate(pci_chipset_tag_t pc, pcitag_t tag, void *context)
    490 {
    491         int bus, device, function, command;
    492 	struct rbus_pci_addr_fixup_context *rct =
    493 	  (struct rbus_pci_addr_fixup_context *)context;
    494 
    495 	pci_decompose_tag(pc, tag, &bus, &device, &function);
    496 
    497 	printf("%s: configuring device %02x:%02x:%02x\n",
    498 	       device_xname(rct->csc->sc_dev),
    499 	       bus, device, function);
    500 
    501 	pciaddr_resource_manage(pc, tag,
    502 				rbus_do_phys_allocate, context);
    503 
    504 	/* now turn the device's memory and I/O on */
    505 	command = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
    506 	command |= PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE;
    507 	pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, command);
    508 }
    509 
    510 int
    511 rbus_do_phys_allocate(pci_chipset_tag_t pc, pcitag_t tag, int mapreg, void *ctx, int type, bus_addr_t *addr, bus_size_t size)
    512 {
    513 	struct  rbus_pci_addr_fixup_context *rct =
    514 	  (struct  rbus_pci_addr_fixup_context *)ctx;
    515 	cardbus_chipset_tag_t ct     = rct->ct;
    516 	struct cardbus_softc *sc     = rct->sc;
    517 	cardbus_function_t       *cf = sc->sc_cf;
    518 	rbus_tag_t          rbustag;
    519 	bus_addr_t mask = size -1;
    520 	bus_addr_t base = 0;
    521 	bus_space_handle_t handle;
    522 	int busflags = 0;
    523 	int flags    = 0;
    524 	const char *bustype;
    525 	int bus, device, function;
    526 
    527 	pci_decompose_tag(pc, tag, &bus, &device, &function);
    528 
    529 	/*
    530 	 * some devices come up with garbage in them (Tulip?)
    531 	 * we are in charge here, so give them address
    532 	 * space anyway.
    533 	 *
    534 	 * XXX this may be due to no secondary PCI reset!!!
    535 	 */
    536 #if 0
    537 	if (*addr) {
    538 		printf("Already allocated space at %08x\n",
    539 		       (unsigned int)*addr);
    540 		return (0);
    541 	}
    542 #endif
    543 
    544 	if(size > (1<<24)) {
    545 	  printf("%s: skipping huge space request of size=%08x\n",
    546 		 device_xname(rct->csc->sc_dev), (unsigned int)size);
    547 	  return 0;
    548 	}
    549 
    550 	if(PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_IO) {
    551 	  rbustag = rct->iobustags[bus];
    552 	  bustype = "io";
    553 	} else {
    554 	  rbustag = rct->membustags[bus];
    555 	  bustype = "mem";
    556 	}
    557 
    558 	if((*cf->cardbus_space_alloc)(ct, rbustag, base, size,
    559 				      mask, size, busflags|flags,
    560 				      addr, &handle)) {
    561 	  printf("%s: no available resources (size=%08x) for bar %2d. fixup failed\n",
    562 		 device_xname(rct->csc->sc_dev), (unsigned int)size, mapreg);
    563 
    564 	  *addr = 0;
    565 	  pci_conf_write(pc, tag, mapreg, *addr);
    566 	  return (1);
    567 	}
    568 
    569 	printf("%s: alloc %s space of size %08x for %02d:%02d:%02d -> %08x\n",
    570 	       device_xname(rct->csc->sc_dev),
    571 	       bustype,
    572 	       (unsigned int)size,
    573 	       bus, device, function, (unsigned int)*addr);
    574 
    575 	/* write new address to PCI device configuration header */
    576 	pci_conf_write(pc, tag, mapreg, *addr);
    577 
    578 	/* check */
    579 	{
    580 		DPRINTF(("%s: pci_addr_fixup: ",
    581 			 device_xname(rct->csc->sc_dev)));
    582 #ifdef  CBB_DEBUG
    583 		if(rbus_ppb_debug) { pciaddr_print_devid(pc, tag); }
    584 #endif
    585 	}
    586 
    587 	/* double check that the value got inserted correctly */
    588 	if (pciaddr_ioaddr(pci_conf_read(pc, tag, mapreg)) != *addr) {
    589 		pci_conf_write(pc, tag, mapreg, 0); /* clear */
    590 		printf("%s: fixup failed. (new address=%#x)\n",
    591 		       device_xname(rct->csc->sc_dev),
    592 		       (unsigned)*addr);
    593 		return (1);
    594 	}
    595 
    596 	DPRINTF(("new address 0x%08x\n",
    597 		 (unsigned)*addr));
    598 
    599 	return (0);
    600 }
    601 
    602 static void
    603 ppb_cardbus_attach(device_t parent, device_t self, void *aux)
    604 {
    605 	struct ppb_cardbus_softc *csc = device_private(self);
    606 	struct cardbus_softc *parent_sc = device_private(parent);
    607 	struct cardbus_attach_args *ca = aux;
    608 	cardbus_devfunc_t ct = ca->ca_ct;
    609 	cardbus_chipset_tag_t cc = ct->ct_cc;
    610 	struct pccbb_softc *psc = (struct pccbb_softc *)cc;
    611 	struct pcibus_attach_args pba;
    612 	char devinfo[256];
    613 	pcireg_t busdata;
    614 	int minbus, maxbus;
    615 
    616 	csc->sc_dev = self;
    617 
    618 	pci_devinfo(ca->ca_id, ca->ca_class, 0, devinfo, sizeof(devinfo));
    619 	printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(ca->ca_class));
    620 
    621 	csc->sc_tag = ca->ca_tag;
    622 
    623 	busdata = Cardbus_conf_read(ct, ca->ca_tag, PCI_BRIDGE_BUS_REG);
    624 	minbus = pcibios_max_bus;
    625 	maxbus = minbus;		/* XXX; gcc */
    626 
    627 	if (PCI_BRIDGE_BUS_NUM_SECONDARY(busdata) == 0) {
    628 		aprint_error_dev(self, "not configured by system firmware calling pci_bus_fixup(%d)\n", 0);
    629 
    630 	  /*
    631 	   * first, pull the reset wire on the secondary bridge
    632 	   * to clear all devices
    633 	   */
    634 	  busdata = Cardbus_conf_read(ct, ca->ca_tag, PCI_BRIDGE_CONTROL_REG);
    635 	  Cardbus_conf_write(ct, ca->ca_tag, PCI_BRIDGE_CONTROL_REG,
    636 	      busdata | PCI_BRIDGE_CONTROL_SECBR);
    637 	  delay(1);
    638 	  Cardbus_conf_write(ct, ca->ca_tag, PCI_BRIDGE_CONTROL_REG,
    639 			     busdata);
    640 
    641 	  /* then go initialize the bridge control registers */
    642 	  maxbus = pci_bus_fixup(psc->sc_pc, 0);
    643 	}
    644 
    645 	busdata = Cardbus_conf_read(ct, ca->ca_tag, PCI_BRIDGE_BUS_REG);
    646 	if(PCI_BRIDGE_BUS_NUM_SECONDARY(busdata) == 0) {
    647 		aprint_error_dev(self, "still not configured, not fixable.\n");
    648 		return;
    649 	}
    650 
    651 #if 0
    652 	minbus = PCI_BRIDGE_BUS_NUM_SECONDARY(busdata);
    653 	maxbus = PCI_BRIDGE_BUS_NUM_SUBORDINATE(busdata);
    654 #endif
    655 
    656 	/* now, go and assign addresses for the new devices */
    657 	rbus_pci_addr_fixup(csc, cc, parent_sc,
    658 			    psc->sc_pc,
    659 			    ca,
    660 			    minbus, maxbus);
    661 
    662 	/*
    663 	 * now configure all connected devices to the IRQ which
    664 	 * was assigned to this slot, as they will all arrive from
    665 	 * that IRQ.
    666 	 */
    667 	rbus_intr_fixup(psc->sc_pc, minbus, maxbus, 0);
    668 
    669 	/*
    670 	 * enable direct routing of interrupts. We do this because
    671 	 * we can not manage to get pccb_intr_establish() called until
    672 	 * PCI subsystem is merged with rbus. The major thing that this
    673 	 * routine does is avoid calling the driver's interrupt routine
    674 	 * when the card has been removed.
    675 	 *
    676 	 * The rbus_ppb.c can not cope with card desertions until the merging
    677 	 * anyway.
    678 	 */
    679 	pccbb_intr_route(psc);
    680 
    681 	/*
    682 	 * Attach the PCI bus than hangs off of it.
    683 	 *
    684 	 * XXX Don't pass-through Memory Read Multiple.  Should we?
    685 	 * XXX Consult the spec...
    686 	 */
    687 	pba.pba_iot  = ca->ca_iot;
    688 	pba.pba_memt = ca->ca_memt;
    689 	pba.pba_dmat = ca->ca_dmat;
    690 	pba.pba_pc   = psc->sc_pc;
    691 	pba.pba_flags    = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY;
    692 	pba.pba_bus      = PCI_BRIDGE_BUS_NUM_SECONDARY(busdata);
    693 	pba.pba_bridgetag = &csc->sc_tag;
    694 	/*pba.pba_intrswiz = parent_sc->sc_intrswiz; */
    695 	pba.pba_intrtag  = psc->sc_pa.pa_intrtag;
    696 
    697 	config_found_ia(self, "pcibus", &pba, rppbprint);
    698 }
    699 
    700 int
    701 ppb_activate(device_t self, enum devact act)
    702 {
    703   printf("ppb_activate called\n");
    704   return 0;
    705 }
    706