cs4231_ebus.c revision 1.1 1 1.1 uwe /* $NetBSD: cs4231_ebus.c,v 1.1 2002/03/12 04:48:29 uwe Exp $ */
2 1.1 uwe
3 1.1 uwe /*
4 1.1 uwe * Copyright (c) 2002 Valeriy E. Ushakov
5 1.1 uwe * All rights reserved.
6 1.1 uwe *
7 1.1 uwe * Redistribution and use in source and binary forms, with or without
8 1.1 uwe * modification, are permitted provided that the following conditions
9 1.1 uwe * are met:
10 1.1 uwe * 1. Redistributions of source code must retain the above copyright
11 1.1 uwe * notice, this list of conditions and the following disclaimer.
12 1.1 uwe * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 uwe * notice, this list of conditions and the following disclaimer in the
14 1.1 uwe * documentation and/or other materials provided with the distribution.
15 1.1 uwe * 3. The name of the author may not be used to endorse or promote products
16 1.1 uwe * derived from this software without specific prior written permission
17 1.1 uwe *
18 1.1 uwe * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 1.1 uwe * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 1.1 uwe * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 1.1 uwe * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 1.1 uwe * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 1.1 uwe * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 1.1 uwe * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 1.1 uwe * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 1.1 uwe * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 1.1 uwe * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 1.1 uwe */
29 1.1 uwe
30 1.1 uwe #include <sys/param.h>
31 1.1 uwe #include <sys/systm.h>
32 1.1 uwe #include <sys/errno.h>
33 1.1 uwe #include <sys/device.h>
34 1.1 uwe #include <sys/malloc.h>
35 1.1 uwe
36 1.1 uwe #include <machine/autoconf.h>
37 1.1 uwe #include <machine/cpu.h>
38 1.1 uwe #include <dev/ebus/ebusreg.h>
39 1.1 uwe #include <dev/ebus/ebusvar.h>
40 1.1 uwe
41 1.1 uwe #include <sys/audioio.h>
42 1.1 uwe #include <dev/audio_if.h>
43 1.1 uwe
44 1.1 uwe #include <dev/ic/ad1848reg.h>
45 1.1 uwe #include <dev/ic/cs4231reg.h>
46 1.1 uwe #include <dev/ic/ad1848var.h>
47 1.1 uwe #include <dev/ic/cs4231var.h>
48 1.1 uwe
49 1.1 uwe #define AUDIO_ROM_NAME "sound"
50 1.1 uwe
51 1.1 uwe #ifdef AUDIO_DEBUG
52 1.1 uwe int cs4231_ebus_debug = 0;
53 1.1 uwe #define DPRINTF(x) if (cs4231_ebus_debug) printf x
54 1.1 uwe #else
55 1.1 uwe #define DPRINTF(x)
56 1.1 uwe #endif
57 1.1 uwe
58 1.1 uwe
59 1.1 uwe struct cs4231_ebus_softc {
60 1.1 uwe struct cs4231_softc sc_cs4231;
61 1.1 uwe
62 1.1 uwe volatile struct ebus_dmac_reg *sc_pdmareg; /* playback DMA */
63 1.1 uwe volatile struct ebus_dmac_reg *sc_rdmareg; /* record DMA */
64 1.1 uwe };
65 1.1 uwe
66 1.1 uwe
67 1.1 uwe void cs4231_ebus_attach(struct device *, struct device *, void *);
68 1.1 uwe int cs4231_ebus_match(struct device *, struct cfdata *, void *);
69 1.1 uwe
70 1.1 uwe struct cfattach audiocs_ebus_ca = {
71 1.1 uwe sizeof(struct cs4231_ebus_softc), cs4231_ebus_match, cs4231_ebus_attach
72 1.1 uwe };
73 1.1 uwe
74 1.1 uwe
75 1.1 uwe /* audio_hw_if methods specific to ebus dma */
76 1.1 uwe static int cs4231_ebus_trigger_output(void *, void *, void *, int,
77 1.1 uwe void (*)(void *), void *,
78 1.1 uwe struct audio_params *);
79 1.1 uwe static int cs4231_ebus_trigger_input(void *, void *, void *, int,
80 1.1 uwe void (*)(void *), void *,
81 1.1 uwe struct audio_params *);
82 1.1 uwe static int cs4231_ebus_halt_output(void *);
83 1.1 uwe static int cs4231_ebus_halt_input(void *);
84 1.1 uwe
85 1.1 uwe struct audio_hw_if audiocs_ebus_hw_if = {
86 1.1 uwe cs4231_open,
87 1.1 uwe cs4231_close,
88 1.1 uwe NULL, /* drain */
89 1.1 uwe ad1848_query_encoding,
90 1.1 uwe ad1848_set_params,
91 1.1 uwe cs4231_round_blocksize,
92 1.1 uwe ad1848_commit_settings,
93 1.1 uwe NULL, /* init_output */
94 1.1 uwe NULL, /* init_input */
95 1.1 uwe NULL, /* start_output */
96 1.1 uwe NULL, /* start_input */
97 1.1 uwe cs4231_ebus_halt_output,
98 1.1 uwe cs4231_ebus_halt_input,
99 1.1 uwe NULL, /* speaker_ctl */
100 1.1 uwe cs4231_getdev,
101 1.1 uwe NULL, /* setfd */
102 1.1 uwe cs4231_set_port,
103 1.1 uwe cs4231_get_port,
104 1.1 uwe cs4231_query_devinfo,
105 1.1 uwe cs4231_malloc,
106 1.1 uwe cs4231_free,
107 1.1 uwe cs4231_round_buffersize,
108 1.1 uwe NULL, /* mappage */
109 1.1 uwe cs4231_get_props,
110 1.1 uwe cs4231_ebus_trigger_output,
111 1.1 uwe cs4231_ebus_trigger_input,
112 1.1 uwe NULL, /* dev_ioctl */
113 1.1 uwe };
114 1.1 uwe
115 1.1 uwe #ifdef AUDIO_DEBUG
116 1.1 uwe static void cs4231_ebus_regdump(char *, struct cs4231_ebus_softc *);
117 1.1 uwe #endif
118 1.1 uwe
119 1.1 uwe static int cs4231_ebus_dma_reset(volatile struct ebus_dmac_reg *);
120 1.1 uwe static int cs4231_ebus_trigger_transfer(struct cs4231_softc *,
121 1.1 uwe struct cs_transfer *, volatile struct ebus_dmac_reg *,
122 1.1 uwe int, void *, void *, int, void (*)(void *), void *,
123 1.1 uwe struct audio_params *);
124 1.1 uwe static void cs4231_ebus_dma_advance(struct cs_transfer *,
125 1.1 uwe volatile struct ebus_dmac_reg *);
126 1.1 uwe static int cs4231_ebus_dma_intr(struct cs_transfer *,
127 1.1 uwe volatile struct ebus_dmac_reg *);
128 1.1 uwe static int cs4231_ebus_intr(void *);
129 1.1 uwe
130 1.1 uwe
131 1.1 uwe int
132 1.1 uwe cs4231_ebus_match(parent, cf, aux)
133 1.1 uwe struct device *parent;
134 1.1 uwe struct cfdata *cf;
135 1.1 uwe void *aux;
136 1.1 uwe {
137 1.1 uwe struct ebus_attach_args *ea = aux;
138 1.1 uwe
139 1.1 uwe if (strcmp(ea->ea_name, AUDIOCS_PROM_NAME) == 0)
140 1.1 uwe return (1);
141 1.1 uwe #ifdef __sparc__ /* XXX: Krups */
142 1.1 uwe if (strcmp(ea->ea_name, "sound") == 0)
143 1.1 uwe return (1);
144 1.1 uwe #endif
145 1.1 uwe
146 1.1 uwe return (0);
147 1.1 uwe }
148 1.1 uwe
149 1.1 uwe
150 1.1 uwe void
151 1.1 uwe cs4231_ebus_attach(parent, self, aux)
152 1.1 uwe struct device *parent, *self;
153 1.1 uwe void *aux;
154 1.1 uwe {
155 1.1 uwe struct cs4231_ebus_softc *ebsc = (struct cs4231_ebus_softc *)self;
156 1.1 uwe struct cs4231_softc *sc = &ebsc->sc_cs4231;
157 1.1 uwe struct ebus_attach_args *ea = aux;
158 1.1 uwe bus_space_handle_t bh;
159 1.1 uwe int i;
160 1.1 uwe
161 1.1 uwe sc->sc_bustag = ea->ea_bustag;
162 1.1 uwe sc->sc_dmatag = ea->ea_dmatag;
163 1.1 uwe
164 1.1 uwe /*
165 1.1 uwe * These are the register we get from the prom:
166 1.1 uwe * - CS4231 registers
167 1.1 uwe * - Playback EBus DMA controller
168 1.1 uwe * - Capture EBus DMA controller
169 1.1 uwe * - AUXIO audio register (codec powerdown)
170 1.1 uwe *
171 1.1 uwe * Map my registers in, if they aren't already in virtual
172 1.1 uwe * address space.
173 1.1 uwe */
174 1.1 uwe if (ea->ea_nvaddr) {
175 1.1 uwe bh = (bus_space_handle_t)ea->ea_vaddr[0];
176 1.1 uwe } else {
177 1.1 uwe if (bus_space_map(ea->ea_bustag,
178 1.1 uwe EBUS_ADDR_FROM_REG(&ea->ea_reg[0]),
179 1.1 uwe ea->ea_reg[0].size,
180 1.1 uwe BUS_SPACE_MAP_LINEAR,
181 1.1 uwe &bh) != 0)
182 1.1 uwe {
183 1.1 uwe printf("%s: unable to map registers\n",
184 1.1 uwe self->dv_xname);
185 1.1 uwe return;
186 1.1 uwe }
187 1.1 uwe }
188 1.1 uwe
189 1.1 uwe /* XXX: map playback DMA registers (we just know where they are) */
190 1.1 uwe if (bus_space_map(ea->ea_bustag,
191 1.1 uwe BUS_ADDR(0x14, 0x702000), /* XXX: magic num */
192 1.1 uwe sizeof(struct ebus_dmac_reg),
193 1.1 uwe BUS_SPACE_MAP_LINEAR,
194 1.1 uwe (bus_space_handle_t *)&ebsc->sc_pdmareg) != 0)
195 1.1 uwe {
196 1.1 uwe printf("%s: unable to map playback DMA registers\n",
197 1.1 uwe self->dv_xname);
198 1.1 uwe return;
199 1.1 uwe }
200 1.1 uwe
201 1.1 uwe /* XXX: map capture DMA registers (we just know where they are) */
202 1.1 uwe if (bus_space_map(ea->ea_bustag,
203 1.1 uwe BUS_ADDR(0x14, 0x704000), /* XXX: magic num */
204 1.1 uwe sizeof(struct ebus_dmac_reg),
205 1.1 uwe BUS_SPACE_MAP_LINEAR,
206 1.1 uwe (bus_space_handle_t *)&ebsc->sc_rdmareg) != 0)
207 1.1 uwe {
208 1.1 uwe printf("%s: unable to map capture DMA registers\n",
209 1.1 uwe self->dv_xname);
210 1.1 uwe return;
211 1.1 uwe }
212 1.1 uwe
213 1.1 uwe /* establish interrupt channels */
214 1.1 uwe for (i = 0; i < ea->ea_nintr; ++i)
215 1.1 uwe bus_intr_establish(ea->ea_bustag,
216 1.1 uwe ea->ea_intr[i], IPL_AUDIO, 0,
217 1.1 uwe cs4231_ebus_intr, ebsc);
218 1.1 uwe
219 1.1 uwe cs4231_common_attach(sc, bh);
220 1.1 uwe printf("\n");
221 1.1 uwe
222 1.1 uwe /* XXX: todo: move to cs4231_common_attach, pass hw_if as arg? */
223 1.1 uwe audio_attach_mi(&audiocs_ebus_hw_if, sc, &sc->sc_ad1848.sc_dev);
224 1.1 uwe }
225 1.1 uwe
226 1.1 uwe
227 1.1 uwe #ifdef AUDIO_DEBUG
228 1.1 uwe static void
229 1.1 uwe cs4231_ebus_regdump(label, ebsc)
230 1.1 uwe char *label;
231 1.1 uwe struct cs4231_ebus_softc *ebsc;
232 1.1 uwe {
233 1.1 uwe /* char bits[128]; */
234 1.1 uwe
235 1.1 uwe printf("cs4231regdump(%s): regs:", label);
236 1.1 uwe /* XXX: dump ebus dma and aux registers */
237 1.1 uwe ad1848_dump_regs(&ebsc->sc_cs4231.sc_ad1848);
238 1.1 uwe }
239 1.1 uwe #endif /* AUDIO_DEBUG */
240 1.1 uwe
241 1.1 uwe
242 1.1 uwe /* XXX: nothing CS4231-specific in this code... */
243 1.1 uwe static int
244 1.1 uwe cs4231_ebus_dma_reset(dmac)
245 1.1 uwe volatile struct ebus_dmac_reg *dmac;
246 1.1 uwe {
247 1.1 uwe int timo;
248 1.1 uwe
249 1.1 uwe dmac->dcsr = EBDMA_RESET | EBDMA_TC; /* also clear TC, just in case */
250 1.1 uwe
251 1.1 uwe for (timo = 50000; timo != 0; --timo)
252 1.1 uwe if ((dmac->dcsr & (EBDMA_CYC_PEND | EBDMA_DRAIN)) == 0)
253 1.1 uwe break;
254 1.1 uwe
255 1.1 uwe if (timo == 0) {
256 1.1 uwe printf("cs4231_ebus_dma_reset: dcsr = %x, reset timed out\n",
257 1.1 uwe dmac->dcsr);
258 1.1 uwe return (ETIMEDOUT);
259 1.1 uwe }
260 1.1 uwe
261 1.1 uwe dmac->dcsr &= ~EBDMA_RESET;
262 1.1 uwe return (0);
263 1.1 uwe }
264 1.1 uwe
265 1.1 uwe
266 1.1 uwe static void
267 1.1 uwe cs4231_ebus_dma_advance(t, dmac)
268 1.1 uwe struct cs_transfer *t;
269 1.1 uwe volatile struct ebus_dmac_reg *dmac;
270 1.1 uwe {
271 1.1 uwe bus_addr_t dmaaddr;
272 1.1 uwe bus_size_t dmasize;
273 1.1 uwe
274 1.1 uwe cs4231_transfer_advance(t, &dmaaddr, &dmasize);
275 1.1 uwe dmac->dbcr = (u_int32_t)dmasize;
276 1.1 uwe dmac->dacr = (u_int32_t)dmaaddr;
277 1.1 uwe }
278 1.1 uwe
279 1.1 uwe
280 1.1 uwe /*
281 1.1 uwe * Trigger transfer "t" using DMA controller "dmac".
282 1.1 uwe * "iswrite" defines direction of the transfer.
283 1.1 uwe */
284 1.1 uwe static int
285 1.1 uwe cs4231_ebus_trigger_transfer(sc, t, dmac, iswrite,
286 1.1 uwe start, end, blksize,
287 1.1 uwe intr, arg, param)
288 1.1 uwe struct cs4231_softc *sc;
289 1.1 uwe struct cs_transfer *t;
290 1.1 uwe volatile struct ebus_dmac_reg *dmac;
291 1.1 uwe int iswrite;
292 1.1 uwe void *start, *end;
293 1.1 uwe int blksize;
294 1.1 uwe void (*intr)(void *);
295 1.1 uwe void *arg;
296 1.1 uwe struct audio_params *param;
297 1.1 uwe {
298 1.1 uwe bus_addr_t dmaaddr;
299 1.1 uwe bus_size_t dmasize;
300 1.1 uwe int ret;
301 1.1 uwe
302 1.1 uwe ret = cs4231_transfer_init(sc, t, &dmaaddr, &dmasize,
303 1.1 uwe start, end, blksize, intr, arg);
304 1.1 uwe if (ret != 0)
305 1.1 uwe return (ret);
306 1.1 uwe
307 1.1 uwe ret = cs4231_ebus_dma_reset(dmac);
308 1.1 uwe if (ret != 0)
309 1.1 uwe return (ret);
310 1.1 uwe
311 1.1 uwe dmac->dcsr |= EBDMA_EN_NEXT | (iswrite ? EBDMA_WRITE : 0)
312 1.1 uwe | EBDMA_EN_DMA | EBDMA_EN_CNT | EBDMA_INT_EN;
313 1.1 uwe
314 1.1 uwe /* first load: goes to DACR/DBCR */
315 1.1 uwe dmac->dbcr = (u_int32_t)dmasize;
316 1.1 uwe dmac->dacr = (u_int32_t)dmaaddr;
317 1.1 uwe
318 1.1 uwe /* next load: goes to DNAR/DNBR */
319 1.1 uwe cs4231_ebus_dma_advance(t, dmac);
320 1.1 uwe
321 1.1 uwe return (0);
322 1.1 uwe }
323 1.1 uwe
324 1.1 uwe
325 1.1 uwe static int
326 1.1 uwe cs4231_ebus_trigger_output(addr, start, end, blksize, intr, arg, param)
327 1.1 uwe void *addr;
328 1.1 uwe void *start, *end;
329 1.1 uwe int blksize;
330 1.1 uwe void (*intr)(void *);
331 1.1 uwe void *arg;
332 1.1 uwe struct audio_params *param;
333 1.1 uwe {
334 1.1 uwe struct cs4231_ebus_softc *ebsc = addr;
335 1.1 uwe struct cs4231_softc *sc = &ebsc->sc_cs4231;
336 1.1 uwe struct cs_transfer *t = &sc->sc_playback;
337 1.1 uwe volatile struct ebus_dmac_reg *dma = ebsc->sc_pdmareg;
338 1.1 uwe int cfg;
339 1.1 uwe int ret;
340 1.1 uwe
341 1.1 uwe ret = cs4231_ebus_trigger_transfer(sc, t, dma, 0,
342 1.1 uwe start, end, blksize,
343 1.1 uwe intr, arg,
344 1.1 uwe param);
345 1.1 uwe if (ret != 0)
346 1.1 uwe return (ret);
347 1.1 uwe
348 1.1 uwe ad_write(&sc->sc_ad1848, SP_LOWER_BASE_COUNT, 0xff);
349 1.1 uwe ad_write(&sc->sc_ad1848, SP_UPPER_BASE_COUNT, 0xff);
350 1.1 uwe
351 1.1 uwe cfg = ad_read(&sc->sc_ad1848, SP_INTERFACE_CONFIG);
352 1.1 uwe ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG, (cfg | PLAYBACK_ENABLE));
353 1.1 uwe
354 1.1 uwe return (0);
355 1.1 uwe }
356 1.1 uwe
357 1.1 uwe
358 1.1 uwe static int
359 1.1 uwe cs4231_ebus_trigger_input(addr, start, end, blksize, intr, arg, param)
360 1.1 uwe void *addr;
361 1.1 uwe void *start, *end;
362 1.1 uwe int blksize;
363 1.1 uwe void (*intr)(void *);
364 1.1 uwe void *arg;
365 1.1 uwe struct audio_params *param;
366 1.1 uwe {
367 1.1 uwe struct cs4231_ebus_softc *ebsc = addr;
368 1.1 uwe struct cs4231_softc *sc = &ebsc->sc_cs4231;
369 1.1 uwe struct cs_transfer *t = &sc->sc_capture;
370 1.1 uwe volatile struct ebus_dmac_reg *dmac = ebsc->sc_rdmareg;
371 1.1 uwe int cfg;
372 1.1 uwe int ret;
373 1.1 uwe
374 1.1 uwe ret = cs4231_ebus_trigger_transfer(sc, t, dmac, 1,
375 1.1 uwe start, end, blksize,
376 1.1 uwe intr, arg,
377 1.1 uwe param);
378 1.1 uwe if (ret != 0)
379 1.1 uwe return (ret);
380 1.1 uwe
381 1.1 uwe ad_write(&sc->sc_ad1848, CS_LOWER_REC_CNT, 0xff);
382 1.1 uwe ad_write(&sc->sc_ad1848, CS_UPPER_REC_CNT, 0xff);
383 1.1 uwe
384 1.1 uwe cfg = ad_read(&sc->sc_ad1848, SP_INTERFACE_CONFIG);
385 1.1 uwe ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG, (cfg | CAPTURE_ENABLE));
386 1.1 uwe
387 1.1 uwe return (0);
388 1.1 uwe }
389 1.1 uwe
390 1.1 uwe
391 1.1 uwe static int
392 1.1 uwe cs4231_ebus_halt_output(addr)
393 1.1 uwe void *addr;
394 1.1 uwe {
395 1.1 uwe struct cs4231_ebus_softc *ebsc = (struct cs4231_ebus_softc *)addr;
396 1.1 uwe struct cs4231_softc *sc = &ebsc->sc_cs4231;
397 1.1 uwe int cfg;
398 1.1 uwe
399 1.1 uwe sc->sc_playback.t_active = 0;
400 1.1 uwe ebsc->sc_pdmareg->dcsr &= ~EBDMA_EN_DMA;
401 1.1 uwe
402 1.1 uwe cfg = ad_read(&sc->sc_ad1848, SP_INTERFACE_CONFIG);
403 1.1 uwe ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG,(cfg & ~PLAYBACK_ENABLE));
404 1.1 uwe
405 1.1 uwe return (0);
406 1.1 uwe }
407 1.1 uwe
408 1.1 uwe
409 1.1 uwe static int
410 1.1 uwe cs4231_ebus_halt_input(addr)
411 1.1 uwe void *addr;
412 1.1 uwe {
413 1.1 uwe struct cs4231_ebus_softc *ebsc = (struct cs4231_ebus_softc *)addr;
414 1.1 uwe struct cs4231_softc *sc = &ebsc->sc_cs4231;
415 1.1 uwe int cfg;
416 1.1 uwe
417 1.1 uwe sc->sc_capture.t_active = 0;
418 1.1 uwe ebsc->sc_pdmareg->dcsr &= ~EBDMA_EN_DMA;
419 1.1 uwe
420 1.1 uwe cfg = ad_read(&sc->sc_ad1848, SP_INTERFACE_CONFIG);
421 1.1 uwe ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG, (cfg & ~CAPTURE_ENABLE));
422 1.1 uwe
423 1.1 uwe return (0);
424 1.1 uwe }
425 1.1 uwe
426 1.1 uwe
427 1.1 uwe static int
428 1.1 uwe cs4231_ebus_dma_intr(t, dmac)
429 1.1 uwe struct cs_transfer *t;
430 1.1 uwe volatile struct ebus_dmac_reg *dmac;
431 1.1 uwe {
432 1.1 uwe u_int32_t csr;
433 1.1 uwe #ifdef AUDIO_DEBUG
434 1.1 uwe char bits[128];
435 1.1 uwe #endif
436 1.1 uwe
437 1.1 uwe /* read DMA status, clear TC bit by writing it back */
438 1.1 uwe csr = dmac->dcsr;
439 1.1 uwe dmac->dcsr = csr;
440 1.1 uwe DPRINTF(("audiocs: %s dcsr=%s\n", t->t_name,
441 1.1 uwe bitmask_snprintf(csr, EBUS_DCSR_BITS, bits, sizeof(bits))));
442 1.1 uwe
443 1.1 uwe if (csr & EBDMA_ERR_PEND) {
444 1.1 uwe ++t->t_ierrcnt.ev_count;
445 1.1 uwe printf("audiocs: %s DMA error, resetting\n", t->t_name);
446 1.1 uwe cs4231_ebus_dma_reset(dmac);
447 1.1 uwe /* how to notify audio(9)??? */
448 1.1 uwe return (1);
449 1.1 uwe }
450 1.1 uwe
451 1.1 uwe if ((csr & EBDMA_INT_PEND) == 0)
452 1.1 uwe return (0);
453 1.1 uwe
454 1.1 uwe ++t->t_intrcnt.ev_count;
455 1.1 uwe
456 1.1 uwe if ((csr & EBDMA_TC) == 0) { /* can this happen? */
457 1.1 uwe printf("audiocs: %s INT_PEND but !TC\n", t->t_name);
458 1.1 uwe return (1);
459 1.1 uwe }
460 1.1 uwe
461 1.1 uwe if (!t->t_active)
462 1.1 uwe return (1);
463 1.1 uwe
464 1.1 uwe cs4231_ebus_dma_advance(t, dmac);
465 1.1 uwe
466 1.1 uwe /* call audio(9) framework while dma is chugging along */
467 1.1 uwe if (t->t_intr != NULL)
468 1.1 uwe (*t->t_intr)(t->t_arg);
469 1.1 uwe return (1);
470 1.1 uwe }
471 1.1 uwe
472 1.1 uwe
473 1.1 uwe static int
474 1.1 uwe cs4231_ebus_intr(arg)
475 1.1 uwe void *arg;
476 1.1 uwe {
477 1.1 uwe struct cs4231_ebus_softc *ebsc = (struct cs4231_ebus_softc *)arg;
478 1.1 uwe struct cs4231_softc *sc = &ebsc->sc_cs4231;
479 1.1 uwe int status;
480 1.1 uwe int ret;
481 1.1 uwe #ifdef AUDIO_DEBUG
482 1.1 uwe char bits[128];
483 1.1 uwe #endif
484 1.1 uwe
485 1.1 uwe status = ADREAD(&sc->sc_ad1848, AD1848_STATUS);
486 1.1 uwe
487 1.1 uwe #ifdef AUDIO_DEBUG
488 1.1 uwe if (cs4231_ebus_debug > 1)
489 1.1 uwe cs4231_ebus_regdump("audiointr", ebsc);
490 1.1 uwe
491 1.1 uwe DPRINTF(("%s: status: %s\n", sc->sc_ad1848.sc_dev.dv_xname,
492 1.1 uwe bitmask_snprintf(status, AD_R2_BITS, bits, sizeof(bits))));
493 1.1 uwe #endif
494 1.1 uwe
495 1.1 uwe if (status & INTERRUPT_STATUS) {
496 1.1 uwe #ifdef AUDIO_DEBUG
497 1.1 uwe int reason;
498 1.1 uwe
499 1.1 uwe reason = ad_read(&sc->sc_ad1848, CS_IRQ_STATUS);
500 1.1 uwe DPRINTF(("%s: i24: %s\n", sc->sc_ad1848.sc_dev.dv_xname,
501 1.1 uwe bitmask_snprintf(reason, CS_I24_BITS, bits, sizeof(bits))));
502 1.1 uwe #endif
503 1.1 uwe /* clear interrupt from ad1848 */
504 1.1 uwe ADWRITE(&sc->sc_ad1848, AD1848_STATUS, 0);
505 1.1 uwe }
506 1.1 uwe
507 1.1 uwe ret = 0;
508 1.1 uwe
509 1.1 uwe if (cs4231_ebus_dma_intr(&sc->sc_capture, ebsc->sc_rdmareg)) {
510 1.1 uwe ++sc->sc_intrcnt.ev_count;
511 1.1 uwe ret = 1;
512 1.1 uwe }
513 1.1 uwe
514 1.1 uwe if (cs4231_ebus_dma_intr(&sc->sc_playback, ebsc->sc_pdmareg)) {
515 1.1 uwe ++sc->sc_intrcnt.ev_count;
516 1.1 uwe ret = 1;
517 1.1 uwe }
518 1.1 uwe
519 1.1 uwe return (ret);
520 1.1 uwe }
521