cs4231_ebus.c revision 1.14 1 1.14 yamt /* $NetBSD: cs4231_ebus.c,v 1.14 2004/10/29 12:57:17 yamt Exp $ */
2 1.1 uwe
3 1.1 uwe /*
4 1.1 uwe * Copyright (c) 2002 Valeriy E. Ushakov
5 1.1 uwe * All rights reserved.
6 1.1 uwe *
7 1.1 uwe * Redistribution and use in source and binary forms, with or without
8 1.1 uwe * modification, are permitted provided that the following conditions
9 1.1 uwe * are met:
10 1.1 uwe * 1. Redistributions of source code must retain the above copyright
11 1.1 uwe * notice, this list of conditions and the following disclaimer.
12 1.1 uwe * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 uwe * notice, this list of conditions and the following disclaimer in the
14 1.1 uwe * documentation and/or other materials provided with the distribution.
15 1.1 uwe * 3. The name of the author may not be used to endorse or promote products
16 1.1 uwe * derived from this software without specific prior written permission
17 1.1 uwe *
18 1.1 uwe * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 1.1 uwe * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 1.1 uwe * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 1.1 uwe * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 1.1 uwe * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 1.1 uwe * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 1.1 uwe * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 1.1 uwe * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 1.1 uwe * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 1.1 uwe * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 1.1 uwe */
29 1.12 lukem
30 1.12 lukem #include <sys/cdefs.h>
31 1.14 yamt __KERNEL_RCSID(0, "$NetBSD: cs4231_ebus.c,v 1.14 2004/10/29 12:57:17 yamt Exp $");
32 1.1 uwe
33 1.1 uwe #include <sys/param.h>
34 1.1 uwe #include <sys/systm.h>
35 1.1 uwe #include <sys/errno.h>
36 1.1 uwe #include <sys/device.h>
37 1.1 uwe #include <sys/malloc.h>
38 1.1 uwe
39 1.1 uwe #include <machine/autoconf.h>
40 1.1 uwe #include <machine/cpu.h>
41 1.1 uwe #include <dev/ebus/ebusreg.h>
42 1.1 uwe #include <dev/ebus/ebusvar.h>
43 1.1 uwe
44 1.1 uwe #include <sys/audioio.h>
45 1.1 uwe #include <dev/audio_if.h>
46 1.1 uwe
47 1.1 uwe #include <dev/ic/ad1848reg.h>
48 1.1 uwe #include <dev/ic/cs4231reg.h>
49 1.1 uwe #include <dev/ic/ad1848var.h>
50 1.1 uwe #include <dev/ic/cs4231var.h>
51 1.1 uwe
52 1.1 uwe #ifdef AUDIO_DEBUG
53 1.1 uwe int cs4231_ebus_debug = 0;
54 1.2 uwe #define DPRINTF(x) if (cs4231_ebus_debug) printf x
55 1.1 uwe #else
56 1.1 uwe #define DPRINTF(x)
57 1.1 uwe #endif
58 1.1 uwe
59 1.1 uwe
60 1.1 uwe struct cs4231_ebus_softc {
61 1.1 uwe struct cs4231_softc sc_cs4231;
62 1.1 uwe
63 1.3 uwe bus_space_tag_t sc_bt;
64 1.3 uwe bus_space_handle_t sc_pdmareg; /* playback DMA */
65 1.3 uwe bus_space_handle_t sc_cdmareg; /* record DMA */
66 1.1 uwe };
67 1.1 uwe
68 1.1 uwe
69 1.1 uwe void cs4231_ebus_attach(struct device *, struct device *, void *);
70 1.1 uwe int cs4231_ebus_match(struct device *, struct cfdata *, void *);
71 1.1 uwe
72 1.8 thorpej CFATTACH_DECL(audiocs_ebus, sizeof(struct cs4231_ebus_softc),
73 1.9 thorpej cs4231_ebus_match, cs4231_ebus_attach, NULL, NULL);
74 1.1 uwe
75 1.11 wiz /* audio_hw_if methods specific to ebus DMA */
76 1.13 uwe static int cs4231_ebus_round_blocksize(void *, int);
77 1.1 uwe static int cs4231_ebus_trigger_output(void *, void *, void *, int,
78 1.1 uwe void (*)(void *), void *,
79 1.1 uwe struct audio_params *);
80 1.1 uwe static int cs4231_ebus_trigger_input(void *, void *, void *, int,
81 1.1 uwe void (*)(void *), void *,
82 1.1 uwe struct audio_params *);
83 1.1 uwe static int cs4231_ebus_halt_output(void *);
84 1.1 uwe static int cs4231_ebus_halt_input(void *);
85 1.1 uwe
86 1.14 yamt const struct audio_hw_if audiocs_ebus_hw_if = {
87 1.1 uwe cs4231_open,
88 1.1 uwe cs4231_close,
89 1.1 uwe NULL, /* drain */
90 1.1 uwe ad1848_query_encoding,
91 1.1 uwe ad1848_set_params,
92 1.13 uwe cs4231_ebus_round_blocksize,
93 1.1 uwe ad1848_commit_settings,
94 1.1 uwe NULL, /* init_output */
95 1.1 uwe NULL, /* init_input */
96 1.1 uwe NULL, /* start_output */
97 1.1 uwe NULL, /* start_input */
98 1.1 uwe cs4231_ebus_halt_output,
99 1.1 uwe cs4231_ebus_halt_input,
100 1.1 uwe NULL, /* speaker_ctl */
101 1.1 uwe cs4231_getdev,
102 1.1 uwe NULL, /* setfd */
103 1.1 uwe cs4231_set_port,
104 1.1 uwe cs4231_get_port,
105 1.1 uwe cs4231_query_devinfo,
106 1.1 uwe cs4231_malloc,
107 1.1 uwe cs4231_free,
108 1.13 uwe NULL, /* round_buffersize */
109 1.2 uwe NULL, /* mappage */
110 1.1 uwe cs4231_get_props,
111 1.1 uwe cs4231_ebus_trigger_output,
112 1.1 uwe cs4231_ebus_trigger_input,
113 1.1 uwe NULL, /* dev_ioctl */
114 1.1 uwe };
115 1.1 uwe
116 1.1 uwe #ifdef AUDIO_DEBUG
117 1.1 uwe static void cs4231_ebus_regdump(char *, struct cs4231_ebus_softc *);
118 1.1 uwe #endif
119 1.1 uwe
120 1.3 uwe static int cs4231_ebus_dma_reset(bus_space_tag_t, bus_space_handle_t);
121 1.1 uwe static int cs4231_ebus_trigger_transfer(struct cs4231_softc *,
122 1.3 uwe struct cs_transfer *,
123 1.3 uwe bus_space_tag_t, bus_space_handle_t,
124 1.1 uwe int, void *, void *, int, void (*)(void *), void *,
125 1.1 uwe struct audio_params *);
126 1.1 uwe static void cs4231_ebus_dma_advance(struct cs_transfer *,
127 1.3 uwe bus_space_tag_t, bus_space_handle_t);
128 1.1 uwe static int cs4231_ebus_dma_intr(struct cs_transfer *,
129 1.3 uwe bus_space_tag_t, bus_space_handle_t);
130 1.1 uwe static int cs4231_ebus_intr(void *);
131 1.1 uwe
132 1.1 uwe
133 1.1 uwe int
134 1.1 uwe cs4231_ebus_match(parent, cf, aux)
135 1.1 uwe struct device *parent;
136 1.1 uwe struct cfdata *cf;
137 1.1 uwe void *aux;
138 1.1 uwe {
139 1.1 uwe struct ebus_attach_args *ea = aux;
140 1.1 uwe
141 1.1 uwe if (strcmp(ea->ea_name, AUDIOCS_PROM_NAME) == 0)
142 1.1 uwe return (1);
143 1.1 uwe #ifdef __sparc__ /* XXX: Krups */
144 1.1 uwe if (strcmp(ea->ea_name, "sound") == 0)
145 1.1 uwe return (1);
146 1.1 uwe #endif
147 1.1 uwe
148 1.1 uwe return (0);
149 1.1 uwe }
150 1.1 uwe
151 1.1 uwe
152 1.1 uwe void
153 1.1 uwe cs4231_ebus_attach(parent, self, aux)
154 1.1 uwe struct device *parent, *self;
155 1.1 uwe void *aux;
156 1.1 uwe {
157 1.1 uwe struct cs4231_ebus_softc *ebsc = (struct cs4231_ebus_softc *)self;
158 1.1 uwe struct cs4231_softc *sc = &ebsc->sc_cs4231;
159 1.1 uwe struct ebus_attach_args *ea = aux;
160 1.1 uwe bus_space_handle_t bh;
161 1.1 uwe int i;
162 1.1 uwe
163 1.3 uwe sc->sc_bustag = ebsc->sc_bt = ea->ea_bustag;
164 1.1 uwe sc->sc_dmatag = ea->ea_dmatag;
165 1.1 uwe
166 1.1 uwe /*
167 1.1 uwe * These are the register we get from the prom:
168 1.1 uwe * - CS4231 registers
169 1.1 uwe * - Playback EBus DMA controller
170 1.1 uwe * - Capture EBus DMA controller
171 1.1 uwe * - AUXIO audio register (codec powerdown)
172 1.1 uwe *
173 1.1 uwe * Map my registers in, if they aren't already in virtual
174 1.1 uwe * address space.
175 1.1 uwe */
176 1.4 eeh if (bus_space_map(ea->ea_bustag, EBUS_ADDR_FROM_REG(&ea->ea_reg[0]),
177 1.4 eeh ea->ea_reg[0].size, 0, &bh) != 0) {
178 1.6 uwe printf(": unable to map registers\n");
179 1.4 eeh return;
180 1.1 uwe }
181 1.4 eeh
182 1.1 uwe /* XXX: map playback DMA registers (we just know where they are) */
183 1.1 uwe if (bus_space_map(ea->ea_bustag,
184 1.1 uwe BUS_ADDR(0x14, 0x702000), /* XXX: magic num */
185 1.3 uwe EBUS_DMAC_SIZE,
186 1.3 uwe 0, &ebsc->sc_pdmareg) != 0)
187 1.1 uwe {
188 1.6 uwe printf(": unable to map playback DMA registers\n");
189 1.2 uwe return;
190 1.1 uwe }
191 1.1 uwe
192 1.1 uwe /* XXX: map capture DMA registers (we just know where they are) */
193 1.1 uwe if (bus_space_map(ea->ea_bustag,
194 1.1 uwe BUS_ADDR(0x14, 0x704000), /* XXX: magic num */
195 1.3 uwe EBUS_DMAC_SIZE,
196 1.3 uwe 0, &ebsc->sc_cdmareg) != 0)
197 1.1 uwe {
198 1.6 uwe printf(": unable to map capture DMA registers\n");
199 1.2 uwe return;
200 1.1 uwe }
201 1.1 uwe
202 1.1 uwe /* establish interrupt channels */
203 1.1 uwe for (i = 0; i < ea->ea_nintr; ++i)
204 1.1 uwe bus_intr_establish(ea->ea_bustag,
205 1.10 pk ea->ea_intr[i], IPL_AUDIO,
206 1.1 uwe cs4231_ebus_intr, ebsc);
207 1.1 uwe
208 1.1 uwe cs4231_common_attach(sc, bh);
209 1.1 uwe printf("\n");
210 1.1 uwe
211 1.1 uwe /* XXX: todo: move to cs4231_common_attach, pass hw_if as arg? */
212 1.1 uwe audio_attach_mi(&audiocs_ebus_hw_if, sc, &sc->sc_ad1848.sc_dev);
213 1.1 uwe }
214 1.1 uwe
215 1.1 uwe
216 1.13 uwe static int
217 1.13 uwe cs4231_ebus_round_blocksize(addr, blk)
218 1.13 uwe void *addr;
219 1.13 uwe int blk;
220 1.13 uwe {
221 1.13 uwe
222 1.13 uwe /* we want to use DMA burst size of 16 words */
223 1.13 uwe return (blk & -64);
224 1.13 uwe }
225 1.13 uwe
226 1.13 uwe
227 1.1 uwe #ifdef AUDIO_DEBUG
228 1.1 uwe static void
229 1.1 uwe cs4231_ebus_regdump(label, ebsc)
230 1.1 uwe char *label;
231 1.1 uwe struct cs4231_ebus_softc *ebsc;
232 1.1 uwe {
233 1.1 uwe /* char bits[128]; */
234 1.1 uwe
235 1.1 uwe printf("cs4231regdump(%s): regs:", label);
236 1.11 wiz /* XXX: dump ebus DMA and aux registers */
237 1.1 uwe ad1848_dump_regs(&ebsc->sc_cs4231.sc_ad1848);
238 1.1 uwe }
239 1.1 uwe #endif /* AUDIO_DEBUG */
240 1.1 uwe
241 1.1 uwe
242 1.1 uwe /* XXX: nothing CS4231-specific in this code... */
243 1.1 uwe static int
244 1.3 uwe cs4231_ebus_dma_reset(dt, dh)
245 1.3 uwe bus_space_tag_t dt;
246 1.3 uwe bus_space_handle_t dh;
247 1.1 uwe {
248 1.3 uwe u_int32_t csr;
249 1.1 uwe int timo;
250 1.1 uwe
251 1.3 uwe /* reset, also clear TC, just in case */
252 1.3 uwe bus_space_write_4(dt, dh, EBUS_DMAC_DCSR, EBDMA_RESET | EBDMA_TC);
253 1.1 uwe
254 1.3 uwe for (timo = 50000; timo != 0; --timo) {
255 1.3 uwe csr = bus_space_read_4(dt, dh, EBUS_DMAC_DCSR);
256 1.3 uwe if ((csr & (EBDMA_CYC_PEND | EBDMA_DRAIN)) == 0)
257 1.1 uwe break;
258 1.3 uwe }
259 1.1 uwe
260 1.1 uwe if (timo == 0) {
261 1.3 uwe char bits[128];
262 1.3 uwe
263 1.3 uwe printf("cs4231_ebus_dma_reset: timed out: csr=%s\n",
264 1.3 uwe bitmask_snprintf(csr, EBUS_DCSR_BITS,
265 1.3 uwe bits, sizeof(bits)));
266 1.1 uwe return (ETIMEDOUT);
267 1.1 uwe }
268 1.1 uwe
269 1.3 uwe bus_space_write_4(dt, dh, EBUS_DMAC_DCSR, csr & ~EBDMA_RESET);
270 1.1 uwe return (0);
271 1.1 uwe }
272 1.1 uwe
273 1.1 uwe
274 1.1 uwe static void
275 1.3 uwe cs4231_ebus_dma_advance(t, dt, dh)
276 1.1 uwe struct cs_transfer *t;
277 1.3 uwe bus_space_tag_t dt;
278 1.3 uwe bus_space_handle_t dh;
279 1.1 uwe {
280 1.1 uwe bus_addr_t dmaaddr;
281 1.1 uwe bus_size_t dmasize;
282 1.1 uwe
283 1.1 uwe cs4231_transfer_advance(t, &dmaaddr, &dmasize);
284 1.3 uwe
285 1.3 uwe bus_space_write_4(dt, dh, EBUS_DMAC_DNBR, (u_int32_t)dmasize);
286 1.3 uwe bus_space_write_4(dt, dh, EBUS_DMAC_DNAR, (u_int32_t)dmaaddr);
287 1.1 uwe }
288 1.1 uwe
289 1.1 uwe
290 1.1 uwe /*
291 1.13 uwe * Trigger transfer "t" using DMA controller at "dt"/"dh".
292 1.1 uwe * "iswrite" defines direction of the transfer.
293 1.1 uwe */
294 1.1 uwe static int
295 1.3 uwe cs4231_ebus_trigger_transfer(sc, t, dt, dh, iswrite,
296 1.1 uwe start, end, blksize,
297 1.1 uwe intr, arg, param)
298 1.1 uwe struct cs4231_softc *sc;
299 1.1 uwe struct cs_transfer *t;
300 1.3 uwe bus_space_tag_t dt;
301 1.3 uwe bus_space_handle_t dh;
302 1.1 uwe int iswrite;
303 1.1 uwe void *start, *end;
304 1.1 uwe int blksize;
305 1.1 uwe void (*intr)(void *);
306 1.1 uwe void *arg;
307 1.1 uwe struct audio_params *param;
308 1.1 uwe {
309 1.3 uwe u_int32_t csr;
310 1.1 uwe bus_addr_t dmaaddr;
311 1.1 uwe bus_size_t dmasize;
312 1.1 uwe int ret;
313 1.1 uwe
314 1.1 uwe ret = cs4231_transfer_init(sc, t, &dmaaddr, &dmasize,
315 1.1 uwe start, end, blksize, intr, arg);
316 1.1 uwe if (ret != 0)
317 1.1 uwe return (ret);
318 1.1 uwe
319 1.3 uwe ret = cs4231_ebus_dma_reset(dt, dh);
320 1.1 uwe if (ret != 0)
321 1.1 uwe return (ret);
322 1.1 uwe
323 1.5 martin csr = bus_space_read_4(dt, dh, EBUS_DMAC_DCSR);
324 1.5 martin bus_space_write_4(dt, dh, EBUS_DMAC_DCSR,
325 1.3 uwe csr | EBDMA_EN_NEXT | (iswrite ? EBDMA_WRITE : 0)
326 1.13 uwe | EBDMA_EN_DMA | EBDMA_EN_CNT | EBDMA_INT_EN
327 1.13 uwe | EBDMA_BURST_SIZE_16);
328 1.3 uwe
329 1.3 uwe /* first load: propagated to DACR/DBCR */
330 1.3 uwe bus_space_write_4(dt, dh, EBUS_DMAC_DNBR, (u_int32_t)dmasize);
331 1.3 uwe bus_space_write_4(dt, dh, EBUS_DMAC_DNAR, (u_int32_t)dmaaddr);
332 1.1 uwe
333 1.1 uwe /* next load: goes to DNAR/DNBR */
334 1.3 uwe cs4231_ebus_dma_advance(t, dt, dh);
335 1.1 uwe
336 1.1 uwe return (0);
337 1.1 uwe }
338 1.1 uwe
339 1.1 uwe
340 1.1 uwe static int
341 1.1 uwe cs4231_ebus_trigger_output(addr, start, end, blksize, intr, arg, param)
342 1.1 uwe void *addr;
343 1.1 uwe void *start, *end;
344 1.1 uwe int blksize;
345 1.1 uwe void (*intr)(void *);
346 1.1 uwe void *arg;
347 1.1 uwe struct audio_params *param;
348 1.1 uwe {
349 1.1 uwe struct cs4231_ebus_softc *ebsc = addr;
350 1.1 uwe struct cs4231_softc *sc = &ebsc->sc_cs4231;
351 1.3 uwe int cfg, ret;
352 1.1 uwe
353 1.3 uwe ret = cs4231_ebus_trigger_transfer(sc, &sc->sc_playback,
354 1.3 uwe ebsc->sc_bt, ebsc->sc_pdmareg,
355 1.3 uwe 0, /* iswrite */
356 1.1 uwe start, end, blksize,
357 1.3 uwe intr, arg, param);
358 1.1 uwe if (ret != 0)
359 1.1 uwe return (ret);
360 1.1 uwe
361 1.1 uwe ad_write(&sc->sc_ad1848, SP_LOWER_BASE_COUNT, 0xff);
362 1.1 uwe ad_write(&sc->sc_ad1848, SP_UPPER_BASE_COUNT, 0xff);
363 1.1 uwe
364 1.1 uwe cfg = ad_read(&sc->sc_ad1848, SP_INTERFACE_CONFIG);
365 1.3 uwe ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG, cfg | PLAYBACK_ENABLE);
366 1.1 uwe
367 1.1 uwe return (0);
368 1.1 uwe }
369 1.1 uwe
370 1.1 uwe
371 1.1 uwe static int
372 1.1 uwe cs4231_ebus_trigger_input(addr, start, end, blksize, intr, arg, param)
373 1.1 uwe void *addr;
374 1.1 uwe void *start, *end;
375 1.1 uwe int blksize;
376 1.1 uwe void (*intr)(void *);
377 1.1 uwe void *arg;
378 1.1 uwe struct audio_params *param;
379 1.1 uwe {
380 1.1 uwe struct cs4231_ebus_softc *ebsc = addr;
381 1.1 uwe struct cs4231_softc *sc = &ebsc->sc_cs4231;
382 1.3 uwe int cfg, ret;
383 1.1 uwe
384 1.3 uwe ret = cs4231_ebus_trigger_transfer(sc, &sc->sc_capture,
385 1.3 uwe ebsc->sc_bt, ebsc->sc_cdmareg,
386 1.3 uwe 1, /* iswrite */
387 1.1 uwe start, end, blksize,
388 1.3 uwe intr, arg, param);
389 1.1 uwe if (ret != 0)
390 1.1 uwe return (ret);
391 1.1 uwe
392 1.1 uwe ad_write(&sc->sc_ad1848, CS_LOWER_REC_CNT, 0xff);
393 1.1 uwe ad_write(&sc->sc_ad1848, CS_UPPER_REC_CNT, 0xff);
394 1.1 uwe
395 1.1 uwe cfg = ad_read(&sc->sc_ad1848, SP_INTERFACE_CONFIG);
396 1.3 uwe ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG, cfg | CAPTURE_ENABLE);
397 1.1 uwe
398 1.1 uwe return (0);
399 1.1 uwe }
400 1.1 uwe
401 1.1 uwe
402 1.1 uwe static int
403 1.1 uwe cs4231_ebus_halt_output(addr)
404 1.1 uwe void *addr;
405 1.1 uwe {
406 1.3 uwe struct cs4231_ebus_softc *ebsc = addr;
407 1.1 uwe struct cs4231_softc *sc = &ebsc->sc_cs4231;
408 1.3 uwe u_int32_t csr;
409 1.1 uwe int cfg;
410 1.1 uwe
411 1.1 uwe sc->sc_playback.t_active = 0;
412 1.3 uwe
413 1.3 uwe csr = bus_space_read_4(ebsc->sc_bt, ebsc->sc_pdmareg, EBUS_DMAC_DCSR);
414 1.3 uwe bus_space_write_4(ebsc->sc_bt, ebsc->sc_pdmareg, EBUS_DMAC_DCSR,
415 1.3 uwe csr & ~EBDMA_EN_DMA);
416 1.1 uwe
417 1.1 uwe cfg = ad_read(&sc->sc_ad1848, SP_INTERFACE_CONFIG);
418 1.3 uwe ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG,
419 1.3 uwe cfg & ~PLAYBACK_ENABLE);
420 1.1 uwe
421 1.1 uwe return (0);
422 1.1 uwe }
423 1.1 uwe
424 1.1 uwe
425 1.1 uwe static int
426 1.1 uwe cs4231_ebus_halt_input(addr)
427 1.1 uwe void *addr;
428 1.1 uwe {
429 1.3 uwe struct cs4231_ebus_softc *ebsc = addr;
430 1.1 uwe struct cs4231_softc *sc = &ebsc->sc_cs4231;
431 1.3 uwe u_int32_t csr;
432 1.1 uwe int cfg;
433 1.1 uwe
434 1.1 uwe sc->sc_capture.t_active = 0;
435 1.3 uwe
436 1.3 uwe csr = bus_space_read_4(ebsc->sc_bt, ebsc->sc_cdmareg, EBUS_DMAC_DCSR);
437 1.3 uwe bus_space_write_4(ebsc->sc_bt, ebsc->sc_cdmareg, EBUS_DMAC_DCSR,
438 1.3 uwe csr & ~EBDMA_EN_DMA);
439 1.1 uwe
440 1.1 uwe cfg = ad_read(&sc->sc_ad1848, SP_INTERFACE_CONFIG);
441 1.3 uwe ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG,
442 1.3 uwe cfg & ~CAPTURE_ENABLE);
443 1.1 uwe
444 1.1 uwe return (0);
445 1.1 uwe }
446 1.1 uwe
447 1.1 uwe
448 1.1 uwe static int
449 1.3 uwe cs4231_ebus_dma_intr(t, dt, dh)
450 1.1 uwe struct cs_transfer *t;
451 1.3 uwe bus_space_tag_t dt;
452 1.3 uwe bus_space_handle_t dh;
453 1.1 uwe {
454 1.1 uwe u_int32_t csr;
455 1.1 uwe #ifdef AUDIO_DEBUG
456 1.1 uwe char bits[128];
457 1.1 uwe #endif
458 1.1 uwe
459 1.1 uwe /* read DMA status, clear TC bit by writing it back */
460 1.3 uwe csr = bus_space_read_4(dt, dh, EBUS_DMAC_DCSR);
461 1.3 uwe bus_space_write_4(dt, dh, EBUS_DMAC_DCSR, csr);
462 1.1 uwe DPRINTF(("audiocs: %s dcsr=%s\n", t->t_name,
463 1.1 uwe bitmask_snprintf(csr, EBUS_DCSR_BITS, bits, sizeof(bits))));
464 1.1 uwe
465 1.1 uwe if (csr & EBDMA_ERR_PEND) {
466 1.1 uwe ++t->t_ierrcnt.ev_count;
467 1.1 uwe printf("audiocs: %s DMA error, resetting\n", t->t_name);
468 1.3 uwe cs4231_ebus_dma_reset(dt, dh);
469 1.1 uwe /* how to notify audio(9)??? */
470 1.1 uwe return (1);
471 1.1 uwe }
472 1.1 uwe
473 1.1 uwe if ((csr & EBDMA_INT_PEND) == 0)
474 1.1 uwe return (0);
475 1.1 uwe
476 1.1 uwe ++t->t_intrcnt.ev_count;
477 1.1 uwe
478 1.1 uwe if ((csr & EBDMA_TC) == 0) { /* can this happen? */
479 1.1 uwe printf("audiocs: %s INT_PEND but !TC\n", t->t_name);
480 1.1 uwe return (1);
481 1.1 uwe }
482 1.1 uwe
483 1.1 uwe if (!t->t_active)
484 1.1 uwe return (1);
485 1.1 uwe
486 1.3 uwe cs4231_ebus_dma_advance(t, dt, dh);
487 1.1 uwe
488 1.11 wiz /* call audio(9) framework while DMA is chugging along */
489 1.1 uwe if (t->t_intr != NULL)
490 1.1 uwe (*t->t_intr)(t->t_arg);
491 1.1 uwe return (1);
492 1.1 uwe }
493 1.1 uwe
494 1.1 uwe
495 1.1 uwe static int
496 1.1 uwe cs4231_ebus_intr(arg)
497 1.1 uwe void *arg;
498 1.1 uwe {
499 1.3 uwe struct cs4231_ebus_softc *ebsc = arg;
500 1.1 uwe struct cs4231_softc *sc = &ebsc->sc_cs4231;
501 1.1 uwe int status;
502 1.1 uwe int ret;
503 1.1 uwe #ifdef AUDIO_DEBUG
504 1.1 uwe char bits[128];
505 1.1 uwe #endif
506 1.1 uwe
507 1.1 uwe status = ADREAD(&sc->sc_ad1848, AD1848_STATUS);
508 1.1 uwe
509 1.1 uwe #ifdef AUDIO_DEBUG
510 1.1 uwe if (cs4231_ebus_debug > 1)
511 1.1 uwe cs4231_ebus_regdump("audiointr", ebsc);
512 1.1 uwe
513 1.1 uwe DPRINTF(("%s: status: %s\n", sc->sc_ad1848.sc_dev.dv_xname,
514 1.1 uwe bitmask_snprintf(status, AD_R2_BITS, bits, sizeof(bits))));
515 1.1 uwe #endif
516 1.1 uwe
517 1.1 uwe if (status & INTERRUPT_STATUS) {
518 1.1 uwe #ifdef AUDIO_DEBUG
519 1.2 uwe int reason;
520 1.1 uwe
521 1.1 uwe reason = ad_read(&sc->sc_ad1848, CS_IRQ_STATUS);
522 1.1 uwe DPRINTF(("%s: i24: %s\n", sc->sc_ad1848.sc_dev.dv_xname,
523 1.1 uwe bitmask_snprintf(reason, CS_I24_BITS, bits, sizeof(bits))));
524 1.1 uwe #endif
525 1.1 uwe /* clear interrupt from ad1848 */
526 1.1 uwe ADWRITE(&sc->sc_ad1848, AD1848_STATUS, 0);
527 1.1 uwe }
528 1.1 uwe
529 1.1 uwe ret = 0;
530 1.1 uwe
531 1.3 uwe if (cs4231_ebus_dma_intr(&sc->sc_capture,
532 1.3 uwe ebsc->sc_bt, ebsc->sc_cdmareg) != 0)
533 1.3 uwe {
534 1.2 uwe ++sc->sc_intrcnt.ev_count;
535 1.2 uwe ret = 1;
536 1.1 uwe }
537 1.1 uwe
538 1.3 uwe if (cs4231_ebus_dma_intr(&sc->sc_playback,
539 1.3 uwe ebsc->sc_bt, ebsc->sc_pdmareg) != 0)
540 1.3 uwe {
541 1.2 uwe ++sc->sc_intrcnt.ev_count;
542 1.2 uwe ret = 1;
543 1.1 uwe }
544 1.1 uwe
545 1.1 uwe return (ret);
546 1.1 uwe }
547