cs4231_ebus.c revision 1.16 1 1.16 kent /* $NetBSD: cs4231_ebus.c,v 1.16 2005/01/11 03:45:17 kent Exp $ */
2 1.1 uwe
3 1.1 uwe /*
4 1.1 uwe * Copyright (c) 2002 Valeriy E. Ushakov
5 1.1 uwe * All rights reserved.
6 1.1 uwe *
7 1.1 uwe * Redistribution and use in source and binary forms, with or without
8 1.1 uwe * modification, are permitted provided that the following conditions
9 1.1 uwe * are met:
10 1.1 uwe * 1. Redistributions of source code must retain the above copyright
11 1.1 uwe * notice, this list of conditions and the following disclaimer.
12 1.1 uwe * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 uwe * notice, this list of conditions and the following disclaimer in the
14 1.1 uwe * documentation and/or other materials provided with the distribution.
15 1.1 uwe * 3. The name of the author may not be used to endorse or promote products
16 1.1 uwe * derived from this software without specific prior written permission
17 1.1 uwe *
18 1.1 uwe * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 1.1 uwe * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 1.1 uwe * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 1.1 uwe * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 1.1 uwe * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 1.1 uwe * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 1.1 uwe * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 1.1 uwe * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 1.1 uwe * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 1.1 uwe * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 1.1 uwe */
29 1.12 lukem
30 1.12 lukem #include <sys/cdefs.h>
31 1.16 kent __KERNEL_RCSID(0, "$NetBSD: cs4231_ebus.c,v 1.16 2005/01/11 03:45:17 kent Exp $");
32 1.1 uwe
33 1.1 uwe #include <sys/param.h>
34 1.1 uwe #include <sys/systm.h>
35 1.1 uwe #include <sys/errno.h>
36 1.1 uwe #include <sys/device.h>
37 1.1 uwe #include <sys/malloc.h>
38 1.1 uwe
39 1.1 uwe #include <machine/autoconf.h>
40 1.1 uwe #include <machine/cpu.h>
41 1.1 uwe #include <dev/ebus/ebusreg.h>
42 1.1 uwe #include <dev/ebus/ebusvar.h>
43 1.1 uwe
44 1.1 uwe #include <sys/audioio.h>
45 1.1 uwe #include <dev/audio_if.h>
46 1.1 uwe
47 1.1 uwe #include <dev/ic/ad1848reg.h>
48 1.1 uwe #include <dev/ic/cs4231reg.h>
49 1.1 uwe #include <dev/ic/ad1848var.h>
50 1.1 uwe #include <dev/ic/cs4231var.h>
51 1.1 uwe
52 1.1 uwe #ifdef AUDIO_DEBUG
53 1.1 uwe int cs4231_ebus_debug = 0;
54 1.2 uwe #define DPRINTF(x) if (cs4231_ebus_debug) printf x
55 1.1 uwe #else
56 1.1 uwe #define DPRINTF(x)
57 1.1 uwe #endif
58 1.1 uwe
59 1.1 uwe
60 1.1 uwe struct cs4231_ebus_softc {
61 1.1 uwe struct cs4231_softc sc_cs4231;
62 1.1 uwe
63 1.3 uwe bus_space_tag_t sc_bt;
64 1.3 uwe bus_space_handle_t sc_pdmareg; /* playback DMA */
65 1.3 uwe bus_space_handle_t sc_cdmareg; /* record DMA */
66 1.1 uwe };
67 1.1 uwe
68 1.1 uwe
69 1.1 uwe void cs4231_ebus_attach(struct device *, struct device *, void *);
70 1.1 uwe int cs4231_ebus_match(struct device *, struct cfdata *, void *);
71 1.1 uwe
72 1.8 thorpej CFATTACH_DECL(audiocs_ebus, sizeof(struct cs4231_ebus_softc),
73 1.9 thorpej cs4231_ebus_match, cs4231_ebus_attach, NULL, NULL);
74 1.1 uwe
75 1.11 wiz /* audio_hw_if methods specific to ebus DMA */
76 1.15 kent static int cs4231_ebus_round_blocksize(void *, int, int,
77 1.15 kent const audio_params_t *);
78 1.1 uwe static int cs4231_ebus_trigger_output(void *, void *, void *, int,
79 1.1 uwe void (*)(void *), void *,
80 1.16 kent const audio_params_t *);
81 1.1 uwe static int cs4231_ebus_trigger_input(void *, void *, void *, int,
82 1.1 uwe void (*)(void *), void *,
83 1.16 kent const audio_params_t *);
84 1.1 uwe static int cs4231_ebus_halt_output(void *);
85 1.1 uwe static int cs4231_ebus_halt_input(void *);
86 1.1 uwe
87 1.14 yamt const struct audio_hw_if audiocs_ebus_hw_if = {
88 1.1 uwe cs4231_open,
89 1.1 uwe cs4231_close,
90 1.1 uwe NULL, /* drain */
91 1.1 uwe ad1848_query_encoding,
92 1.1 uwe ad1848_set_params,
93 1.13 uwe cs4231_ebus_round_blocksize,
94 1.1 uwe ad1848_commit_settings,
95 1.1 uwe NULL, /* init_output */
96 1.1 uwe NULL, /* init_input */
97 1.1 uwe NULL, /* start_output */
98 1.1 uwe NULL, /* start_input */
99 1.1 uwe cs4231_ebus_halt_output,
100 1.1 uwe cs4231_ebus_halt_input,
101 1.1 uwe NULL, /* speaker_ctl */
102 1.1 uwe cs4231_getdev,
103 1.1 uwe NULL, /* setfd */
104 1.1 uwe cs4231_set_port,
105 1.1 uwe cs4231_get_port,
106 1.1 uwe cs4231_query_devinfo,
107 1.1 uwe cs4231_malloc,
108 1.1 uwe cs4231_free,
109 1.13 uwe NULL, /* round_buffersize */
110 1.2 uwe NULL, /* mappage */
111 1.1 uwe cs4231_get_props,
112 1.1 uwe cs4231_ebus_trigger_output,
113 1.1 uwe cs4231_ebus_trigger_input,
114 1.1 uwe NULL, /* dev_ioctl */
115 1.1 uwe };
116 1.1 uwe
117 1.1 uwe #ifdef AUDIO_DEBUG
118 1.1 uwe static void cs4231_ebus_regdump(char *, struct cs4231_ebus_softc *);
119 1.1 uwe #endif
120 1.1 uwe
121 1.3 uwe static int cs4231_ebus_dma_reset(bus_space_tag_t, bus_space_handle_t);
122 1.1 uwe static int cs4231_ebus_trigger_transfer(struct cs4231_softc *,
123 1.3 uwe struct cs_transfer *,
124 1.3 uwe bus_space_tag_t, bus_space_handle_t,
125 1.1 uwe int, void *, void *, int, void (*)(void *), void *,
126 1.16 kent const audio_params_t *);
127 1.1 uwe static void cs4231_ebus_dma_advance(struct cs_transfer *,
128 1.3 uwe bus_space_tag_t, bus_space_handle_t);
129 1.1 uwe static int cs4231_ebus_dma_intr(struct cs_transfer *,
130 1.3 uwe bus_space_tag_t, bus_space_handle_t);
131 1.1 uwe static int cs4231_ebus_intr(void *);
132 1.1 uwe
133 1.1 uwe
134 1.1 uwe int
135 1.1 uwe cs4231_ebus_match(parent, cf, aux)
136 1.1 uwe struct device *parent;
137 1.1 uwe struct cfdata *cf;
138 1.1 uwe void *aux;
139 1.1 uwe {
140 1.1 uwe struct ebus_attach_args *ea = aux;
141 1.1 uwe
142 1.1 uwe if (strcmp(ea->ea_name, AUDIOCS_PROM_NAME) == 0)
143 1.1 uwe return (1);
144 1.1 uwe #ifdef __sparc__ /* XXX: Krups */
145 1.1 uwe if (strcmp(ea->ea_name, "sound") == 0)
146 1.1 uwe return (1);
147 1.1 uwe #endif
148 1.1 uwe
149 1.1 uwe return (0);
150 1.1 uwe }
151 1.1 uwe
152 1.1 uwe
153 1.1 uwe void
154 1.1 uwe cs4231_ebus_attach(parent, self, aux)
155 1.1 uwe struct device *parent, *self;
156 1.1 uwe void *aux;
157 1.1 uwe {
158 1.1 uwe struct cs4231_ebus_softc *ebsc = (struct cs4231_ebus_softc *)self;
159 1.1 uwe struct cs4231_softc *sc = &ebsc->sc_cs4231;
160 1.1 uwe struct ebus_attach_args *ea = aux;
161 1.1 uwe bus_space_handle_t bh;
162 1.1 uwe int i;
163 1.1 uwe
164 1.3 uwe sc->sc_bustag = ebsc->sc_bt = ea->ea_bustag;
165 1.1 uwe sc->sc_dmatag = ea->ea_dmatag;
166 1.1 uwe
167 1.1 uwe /*
168 1.1 uwe * These are the register we get from the prom:
169 1.1 uwe * - CS4231 registers
170 1.1 uwe * - Playback EBus DMA controller
171 1.1 uwe * - Capture EBus DMA controller
172 1.1 uwe * - AUXIO audio register (codec powerdown)
173 1.1 uwe *
174 1.1 uwe * Map my registers in, if they aren't already in virtual
175 1.1 uwe * address space.
176 1.1 uwe */
177 1.4 eeh if (bus_space_map(ea->ea_bustag, EBUS_ADDR_FROM_REG(&ea->ea_reg[0]),
178 1.4 eeh ea->ea_reg[0].size, 0, &bh) != 0) {
179 1.6 uwe printf(": unable to map registers\n");
180 1.4 eeh return;
181 1.1 uwe }
182 1.4 eeh
183 1.1 uwe /* XXX: map playback DMA registers (we just know where they are) */
184 1.1 uwe if (bus_space_map(ea->ea_bustag,
185 1.1 uwe BUS_ADDR(0x14, 0x702000), /* XXX: magic num */
186 1.3 uwe EBUS_DMAC_SIZE,
187 1.3 uwe 0, &ebsc->sc_pdmareg) != 0)
188 1.1 uwe {
189 1.6 uwe printf(": unable to map playback DMA registers\n");
190 1.2 uwe return;
191 1.1 uwe }
192 1.1 uwe
193 1.1 uwe /* XXX: map capture DMA registers (we just know where they are) */
194 1.1 uwe if (bus_space_map(ea->ea_bustag,
195 1.1 uwe BUS_ADDR(0x14, 0x704000), /* XXX: magic num */
196 1.3 uwe EBUS_DMAC_SIZE,
197 1.3 uwe 0, &ebsc->sc_cdmareg) != 0)
198 1.1 uwe {
199 1.6 uwe printf(": unable to map capture DMA registers\n");
200 1.2 uwe return;
201 1.1 uwe }
202 1.1 uwe
203 1.1 uwe /* establish interrupt channels */
204 1.1 uwe for (i = 0; i < ea->ea_nintr; ++i)
205 1.1 uwe bus_intr_establish(ea->ea_bustag,
206 1.10 pk ea->ea_intr[i], IPL_AUDIO,
207 1.1 uwe cs4231_ebus_intr, ebsc);
208 1.1 uwe
209 1.1 uwe cs4231_common_attach(sc, bh);
210 1.1 uwe printf("\n");
211 1.1 uwe
212 1.1 uwe /* XXX: todo: move to cs4231_common_attach, pass hw_if as arg? */
213 1.1 uwe audio_attach_mi(&audiocs_ebus_hw_if, sc, &sc->sc_ad1848.sc_dev);
214 1.1 uwe }
215 1.1 uwe
216 1.1 uwe
217 1.13 uwe static int
218 1.15 kent cs4231_ebus_round_blocksize(addr, blk, mode, param)
219 1.13 uwe void *addr;
220 1.13 uwe int blk;
221 1.15 kent int mode;
222 1.15 kent const audio_params_t *param;
223 1.13 uwe {
224 1.13 uwe
225 1.13 uwe /* we want to use DMA burst size of 16 words */
226 1.13 uwe return (blk & -64);
227 1.13 uwe }
228 1.13 uwe
229 1.13 uwe
230 1.1 uwe #ifdef AUDIO_DEBUG
231 1.1 uwe static void
232 1.1 uwe cs4231_ebus_regdump(label, ebsc)
233 1.1 uwe char *label;
234 1.1 uwe struct cs4231_ebus_softc *ebsc;
235 1.1 uwe {
236 1.1 uwe /* char bits[128]; */
237 1.1 uwe
238 1.1 uwe printf("cs4231regdump(%s): regs:", label);
239 1.11 wiz /* XXX: dump ebus DMA and aux registers */
240 1.1 uwe ad1848_dump_regs(&ebsc->sc_cs4231.sc_ad1848);
241 1.1 uwe }
242 1.1 uwe #endif /* AUDIO_DEBUG */
243 1.1 uwe
244 1.1 uwe
245 1.1 uwe /* XXX: nothing CS4231-specific in this code... */
246 1.1 uwe static int
247 1.3 uwe cs4231_ebus_dma_reset(dt, dh)
248 1.3 uwe bus_space_tag_t dt;
249 1.3 uwe bus_space_handle_t dh;
250 1.1 uwe {
251 1.3 uwe u_int32_t csr;
252 1.1 uwe int timo;
253 1.1 uwe
254 1.3 uwe /* reset, also clear TC, just in case */
255 1.3 uwe bus_space_write_4(dt, dh, EBUS_DMAC_DCSR, EBDMA_RESET | EBDMA_TC);
256 1.1 uwe
257 1.3 uwe for (timo = 50000; timo != 0; --timo) {
258 1.3 uwe csr = bus_space_read_4(dt, dh, EBUS_DMAC_DCSR);
259 1.3 uwe if ((csr & (EBDMA_CYC_PEND | EBDMA_DRAIN)) == 0)
260 1.1 uwe break;
261 1.3 uwe }
262 1.1 uwe
263 1.1 uwe if (timo == 0) {
264 1.3 uwe char bits[128];
265 1.3 uwe
266 1.3 uwe printf("cs4231_ebus_dma_reset: timed out: csr=%s\n",
267 1.3 uwe bitmask_snprintf(csr, EBUS_DCSR_BITS,
268 1.3 uwe bits, sizeof(bits)));
269 1.1 uwe return (ETIMEDOUT);
270 1.1 uwe }
271 1.1 uwe
272 1.3 uwe bus_space_write_4(dt, dh, EBUS_DMAC_DCSR, csr & ~EBDMA_RESET);
273 1.1 uwe return (0);
274 1.1 uwe }
275 1.1 uwe
276 1.1 uwe
277 1.1 uwe static void
278 1.3 uwe cs4231_ebus_dma_advance(t, dt, dh)
279 1.1 uwe struct cs_transfer *t;
280 1.3 uwe bus_space_tag_t dt;
281 1.3 uwe bus_space_handle_t dh;
282 1.1 uwe {
283 1.1 uwe bus_addr_t dmaaddr;
284 1.1 uwe bus_size_t dmasize;
285 1.1 uwe
286 1.1 uwe cs4231_transfer_advance(t, &dmaaddr, &dmasize);
287 1.3 uwe
288 1.3 uwe bus_space_write_4(dt, dh, EBUS_DMAC_DNBR, (u_int32_t)dmasize);
289 1.3 uwe bus_space_write_4(dt, dh, EBUS_DMAC_DNAR, (u_int32_t)dmaaddr);
290 1.1 uwe }
291 1.1 uwe
292 1.1 uwe
293 1.1 uwe /*
294 1.13 uwe * Trigger transfer "t" using DMA controller at "dt"/"dh".
295 1.1 uwe * "iswrite" defines direction of the transfer.
296 1.1 uwe */
297 1.1 uwe static int
298 1.3 uwe cs4231_ebus_trigger_transfer(sc, t, dt, dh, iswrite,
299 1.1 uwe start, end, blksize,
300 1.1 uwe intr, arg, param)
301 1.1 uwe struct cs4231_softc *sc;
302 1.1 uwe struct cs_transfer *t;
303 1.3 uwe bus_space_tag_t dt;
304 1.3 uwe bus_space_handle_t dh;
305 1.1 uwe int iswrite;
306 1.1 uwe void *start, *end;
307 1.1 uwe int blksize;
308 1.1 uwe void (*intr)(void *);
309 1.1 uwe void *arg;
310 1.16 kent const audio_params_t *param;
311 1.1 uwe {
312 1.3 uwe u_int32_t csr;
313 1.1 uwe bus_addr_t dmaaddr;
314 1.1 uwe bus_size_t dmasize;
315 1.1 uwe int ret;
316 1.1 uwe
317 1.1 uwe ret = cs4231_transfer_init(sc, t, &dmaaddr, &dmasize,
318 1.1 uwe start, end, blksize, intr, arg);
319 1.1 uwe if (ret != 0)
320 1.1 uwe return (ret);
321 1.1 uwe
322 1.3 uwe ret = cs4231_ebus_dma_reset(dt, dh);
323 1.1 uwe if (ret != 0)
324 1.1 uwe return (ret);
325 1.1 uwe
326 1.5 martin csr = bus_space_read_4(dt, dh, EBUS_DMAC_DCSR);
327 1.5 martin bus_space_write_4(dt, dh, EBUS_DMAC_DCSR,
328 1.3 uwe csr | EBDMA_EN_NEXT | (iswrite ? EBDMA_WRITE : 0)
329 1.13 uwe | EBDMA_EN_DMA | EBDMA_EN_CNT | EBDMA_INT_EN
330 1.13 uwe | EBDMA_BURST_SIZE_16);
331 1.3 uwe
332 1.3 uwe /* first load: propagated to DACR/DBCR */
333 1.3 uwe bus_space_write_4(dt, dh, EBUS_DMAC_DNBR, (u_int32_t)dmasize);
334 1.3 uwe bus_space_write_4(dt, dh, EBUS_DMAC_DNAR, (u_int32_t)dmaaddr);
335 1.1 uwe
336 1.1 uwe /* next load: goes to DNAR/DNBR */
337 1.3 uwe cs4231_ebus_dma_advance(t, dt, dh);
338 1.1 uwe
339 1.1 uwe return (0);
340 1.1 uwe }
341 1.1 uwe
342 1.1 uwe
343 1.1 uwe static int
344 1.1 uwe cs4231_ebus_trigger_output(addr, start, end, blksize, intr, arg, param)
345 1.1 uwe void *addr;
346 1.1 uwe void *start, *end;
347 1.1 uwe int blksize;
348 1.1 uwe void (*intr)(void *);
349 1.1 uwe void *arg;
350 1.16 kent const audio_params_t *param;
351 1.1 uwe {
352 1.1 uwe struct cs4231_ebus_softc *ebsc = addr;
353 1.1 uwe struct cs4231_softc *sc = &ebsc->sc_cs4231;
354 1.3 uwe int cfg, ret;
355 1.1 uwe
356 1.3 uwe ret = cs4231_ebus_trigger_transfer(sc, &sc->sc_playback,
357 1.3 uwe ebsc->sc_bt, ebsc->sc_pdmareg,
358 1.3 uwe 0, /* iswrite */
359 1.1 uwe start, end, blksize,
360 1.3 uwe intr, arg, param);
361 1.1 uwe if (ret != 0)
362 1.1 uwe return (ret);
363 1.1 uwe
364 1.1 uwe ad_write(&sc->sc_ad1848, SP_LOWER_BASE_COUNT, 0xff);
365 1.1 uwe ad_write(&sc->sc_ad1848, SP_UPPER_BASE_COUNT, 0xff);
366 1.1 uwe
367 1.1 uwe cfg = ad_read(&sc->sc_ad1848, SP_INTERFACE_CONFIG);
368 1.3 uwe ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG, cfg | PLAYBACK_ENABLE);
369 1.1 uwe
370 1.1 uwe return (0);
371 1.1 uwe }
372 1.1 uwe
373 1.1 uwe
374 1.1 uwe static int
375 1.1 uwe cs4231_ebus_trigger_input(addr, start, end, blksize, intr, arg, param)
376 1.1 uwe void *addr;
377 1.1 uwe void *start, *end;
378 1.1 uwe int blksize;
379 1.1 uwe void (*intr)(void *);
380 1.1 uwe void *arg;
381 1.16 kent const audio_params_t *param;
382 1.1 uwe {
383 1.1 uwe struct cs4231_ebus_softc *ebsc = addr;
384 1.1 uwe struct cs4231_softc *sc = &ebsc->sc_cs4231;
385 1.3 uwe int cfg, ret;
386 1.1 uwe
387 1.3 uwe ret = cs4231_ebus_trigger_transfer(sc, &sc->sc_capture,
388 1.3 uwe ebsc->sc_bt, ebsc->sc_cdmareg,
389 1.3 uwe 1, /* iswrite */
390 1.1 uwe start, end, blksize,
391 1.3 uwe intr, arg, param);
392 1.1 uwe if (ret != 0)
393 1.1 uwe return (ret);
394 1.1 uwe
395 1.1 uwe ad_write(&sc->sc_ad1848, CS_LOWER_REC_CNT, 0xff);
396 1.1 uwe ad_write(&sc->sc_ad1848, CS_UPPER_REC_CNT, 0xff);
397 1.1 uwe
398 1.1 uwe cfg = ad_read(&sc->sc_ad1848, SP_INTERFACE_CONFIG);
399 1.3 uwe ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG, cfg | CAPTURE_ENABLE);
400 1.1 uwe
401 1.1 uwe return (0);
402 1.1 uwe }
403 1.1 uwe
404 1.1 uwe
405 1.1 uwe static int
406 1.1 uwe cs4231_ebus_halt_output(addr)
407 1.1 uwe void *addr;
408 1.1 uwe {
409 1.3 uwe struct cs4231_ebus_softc *ebsc = addr;
410 1.1 uwe struct cs4231_softc *sc = &ebsc->sc_cs4231;
411 1.3 uwe u_int32_t csr;
412 1.1 uwe int cfg;
413 1.1 uwe
414 1.1 uwe sc->sc_playback.t_active = 0;
415 1.3 uwe
416 1.3 uwe csr = bus_space_read_4(ebsc->sc_bt, ebsc->sc_pdmareg, EBUS_DMAC_DCSR);
417 1.3 uwe bus_space_write_4(ebsc->sc_bt, ebsc->sc_pdmareg, EBUS_DMAC_DCSR,
418 1.3 uwe csr & ~EBDMA_EN_DMA);
419 1.1 uwe
420 1.1 uwe cfg = ad_read(&sc->sc_ad1848, SP_INTERFACE_CONFIG);
421 1.3 uwe ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG,
422 1.3 uwe cfg & ~PLAYBACK_ENABLE);
423 1.1 uwe
424 1.1 uwe return (0);
425 1.1 uwe }
426 1.1 uwe
427 1.1 uwe
428 1.1 uwe static int
429 1.1 uwe cs4231_ebus_halt_input(addr)
430 1.1 uwe void *addr;
431 1.1 uwe {
432 1.3 uwe struct cs4231_ebus_softc *ebsc = addr;
433 1.1 uwe struct cs4231_softc *sc = &ebsc->sc_cs4231;
434 1.3 uwe u_int32_t csr;
435 1.1 uwe int cfg;
436 1.1 uwe
437 1.1 uwe sc->sc_capture.t_active = 0;
438 1.3 uwe
439 1.3 uwe csr = bus_space_read_4(ebsc->sc_bt, ebsc->sc_cdmareg, EBUS_DMAC_DCSR);
440 1.3 uwe bus_space_write_4(ebsc->sc_bt, ebsc->sc_cdmareg, EBUS_DMAC_DCSR,
441 1.3 uwe csr & ~EBDMA_EN_DMA);
442 1.1 uwe
443 1.1 uwe cfg = ad_read(&sc->sc_ad1848, SP_INTERFACE_CONFIG);
444 1.3 uwe ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG,
445 1.3 uwe cfg & ~CAPTURE_ENABLE);
446 1.1 uwe
447 1.1 uwe return (0);
448 1.1 uwe }
449 1.1 uwe
450 1.1 uwe
451 1.1 uwe static int
452 1.3 uwe cs4231_ebus_dma_intr(t, dt, dh)
453 1.1 uwe struct cs_transfer *t;
454 1.3 uwe bus_space_tag_t dt;
455 1.3 uwe bus_space_handle_t dh;
456 1.1 uwe {
457 1.1 uwe u_int32_t csr;
458 1.1 uwe #ifdef AUDIO_DEBUG
459 1.1 uwe char bits[128];
460 1.1 uwe #endif
461 1.1 uwe
462 1.1 uwe /* read DMA status, clear TC bit by writing it back */
463 1.3 uwe csr = bus_space_read_4(dt, dh, EBUS_DMAC_DCSR);
464 1.3 uwe bus_space_write_4(dt, dh, EBUS_DMAC_DCSR, csr);
465 1.1 uwe DPRINTF(("audiocs: %s dcsr=%s\n", t->t_name,
466 1.1 uwe bitmask_snprintf(csr, EBUS_DCSR_BITS, bits, sizeof(bits))));
467 1.1 uwe
468 1.1 uwe if (csr & EBDMA_ERR_PEND) {
469 1.1 uwe ++t->t_ierrcnt.ev_count;
470 1.1 uwe printf("audiocs: %s DMA error, resetting\n", t->t_name);
471 1.3 uwe cs4231_ebus_dma_reset(dt, dh);
472 1.1 uwe /* how to notify audio(9)??? */
473 1.1 uwe return (1);
474 1.1 uwe }
475 1.1 uwe
476 1.1 uwe if ((csr & EBDMA_INT_PEND) == 0)
477 1.1 uwe return (0);
478 1.1 uwe
479 1.1 uwe ++t->t_intrcnt.ev_count;
480 1.1 uwe
481 1.1 uwe if ((csr & EBDMA_TC) == 0) { /* can this happen? */
482 1.1 uwe printf("audiocs: %s INT_PEND but !TC\n", t->t_name);
483 1.1 uwe return (1);
484 1.1 uwe }
485 1.1 uwe
486 1.1 uwe if (!t->t_active)
487 1.1 uwe return (1);
488 1.1 uwe
489 1.3 uwe cs4231_ebus_dma_advance(t, dt, dh);
490 1.1 uwe
491 1.11 wiz /* call audio(9) framework while DMA is chugging along */
492 1.1 uwe if (t->t_intr != NULL)
493 1.1 uwe (*t->t_intr)(t->t_arg);
494 1.1 uwe return (1);
495 1.1 uwe }
496 1.1 uwe
497 1.1 uwe
498 1.1 uwe static int
499 1.1 uwe cs4231_ebus_intr(arg)
500 1.1 uwe void *arg;
501 1.1 uwe {
502 1.3 uwe struct cs4231_ebus_softc *ebsc = arg;
503 1.1 uwe struct cs4231_softc *sc = &ebsc->sc_cs4231;
504 1.1 uwe int status;
505 1.1 uwe int ret;
506 1.1 uwe #ifdef AUDIO_DEBUG
507 1.1 uwe char bits[128];
508 1.1 uwe #endif
509 1.1 uwe
510 1.1 uwe status = ADREAD(&sc->sc_ad1848, AD1848_STATUS);
511 1.1 uwe
512 1.1 uwe #ifdef AUDIO_DEBUG
513 1.1 uwe if (cs4231_ebus_debug > 1)
514 1.1 uwe cs4231_ebus_regdump("audiointr", ebsc);
515 1.1 uwe
516 1.1 uwe DPRINTF(("%s: status: %s\n", sc->sc_ad1848.sc_dev.dv_xname,
517 1.1 uwe bitmask_snprintf(status, AD_R2_BITS, bits, sizeof(bits))));
518 1.1 uwe #endif
519 1.1 uwe
520 1.1 uwe if (status & INTERRUPT_STATUS) {
521 1.1 uwe #ifdef AUDIO_DEBUG
522 1.2 uwe int reason;
523 1.1 uwe
524 1.1 uwe reason = ad_read(&sc->sc_ad1848, CS_IRQ_STATUS);
525 1.1 uwe DPRINTF(("%s: i24: %s\n", sc->sc_ad1848.sc_dev.dv_xname,
526 1.1 uwe bitmask_snprintf(reason, CS_I24_BITS, bits, sizeof(bits))));
527 1.1 uwe #endif
528 1.1 uwe /* clear interrupt from ad1848 */
529 1.1 uwe ADWRITE(&sc->sc_ad1848, AD1848_STATUS, 0);
530 1.1 uwe }
531 1.1 uwe
532 1.1 uwe ret = 0;
533 1.1 uwe
534 1.3 uwe if (cs4231_ebus_dma_intr(&sc->sc_capture,
535 1.3 uwe ebsc->sc_bt, ebsc->sc_cdmareg) != 0)
536 1.3 uwe {
537 1.2 uwe ++sc->sc_intrcnt.ev_count;
538 1.2 uwe ret = 1;
539 1.1 uwe }
540 1.1 uwe
541 1.3 uwe if (cs4231_ebus_dma_intr(&sc->sc_playback,
542 1.3 uwe ebsc->sc_bt, ebsc->sc_pdmareg) != 0)
543 1.3 uwe {
544 1.2 uwe ++sc->sc_intrcnt.ev_count;
545 1.2 uwe ret = 1;
546 1.1 uwe }
547 1.1 uwe
548 1.1 uwe return (ret);
549 1.1 uwe }
550