cs4231_ebus.c revision 1.22 1 1.22 martin /* $NetBSD: cs4231_ebus.c,v 1.22 2006/10/15 19:43:45 martin Exp $ */
2 1.1 uwe
3 1.1 uwe /*
4 1.1 uwe * Copyright (c) 2002 Valeriy E. Ushakov
5 1.1 uwe * All rights reserved.
6 1.1 uwe *
7 1.1 uwe * Redistribution and use in source and binary forms, with or without
8 1.1 uwe * modification, are permitted provided that the following conditions
9 1.1 uwe * are met:
10 1.1 uwe * 1. Redistributions of source code must retain the above copyright
11 1.1 uwe * notice, this list of conditions and the following disclaimer.
12 1.1 uwe * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 uwe * notice, this list of conditions and the following disclaimer in the
14 1.1 uwe * documentation and/or other materials provided with the distribution.
15 1.1 uwe * 3. The name of the author may not be used to endorse or promote products
16 1.1 uwe * derived from this software without specific prior written permission
17 1.1 uwe *
18 1.1 uwe * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 1.1 uwe * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 1.1 uwe * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 1.1 uwe * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 1.1 uwe * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 1.1 uwe * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 1.1 uwe * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 1.1 uwe * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 1.1 uwe * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 1.1 uwe * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 1.1 uwe */
29 1.12 lukem
30 1.12 lukem #include <sys/cdefs.h>
31 1.22 martin __KERNEL_RCSID(0, "$NetBSD: cs4231_ebus.c,v 1.22 2006/10/15 19:43:45 martin Exp $");
32 1.1 uwe
33 1.1 uwe #include <sys/param.h>
34 1.1 uwe #include <sys/systm.h>
35 1.1 uwe #include <sys/errno.h>
36 1.1 uwe #include <sys/device.h>
37 1.1 uwe #include <sys/malloc.h>
38 1.1 uwe
39 1.1 uwe #include <machine/autoconf.h>
40 1.1 uwe #include <machine/cpu.h>
41 1.1 uwe #include <dev/ebus/ebusreg.h>
42 1.1 uwe #include <dev/ebus/ebusvar.h>
43 1.1 uwe
44 1.1 uwe #include <sys/audioio.h>
45 1.1 uwe #include <dev/audio_if.h>
46 1.1 uwe
47 1.1 uwe #include <dev/ic/ad1848reg.h>
48 1.1 uwe #include <dev/ic/cs4231reg.h>
49 1.1 uwe #include <dev/ic/ad1848var.h>
50 1.1 uwe #include <dev/ic/cs4231var.h>
51 1.1 uwe
52 1.1 uwe #ifdef AUDIO_DEBUG
53 1.1 uwe int cs4231_ebus_debug = 0;
54 1.2 uwe #define DPRINTF(x) if (cs4231_ebus_debug) printf x
55 1.1 uwe #else
56 1.1 uwe #define DPRINTF(x)
57 1.1 uwe #endif
58 1.1 uwe
59 1.1 uwe
60 1.1 uwe struct cs4231_ebus_softc {
61 1.1 uwe struct cs4231_softc sc_cs4231;
62 1.1 uwe
63 1.3 uwe bus_space_tag_t sc_bt;
64 1.3 uwe bus_space_handle_t sc_pdmareg; /* playback DMA */
65 1.3 uwe bus_space_handle_t sc_cdmareg; /* record DMA */
66 1.1 uwe };
67 1.1 uwe
68 1.1 uwe
69 1.1 uwe void cs4231_ebus_attach(struct device *, struct device *, void *);
70 1.1 uwe int cs4231_ebus_match(struct device *, struct cfdata *, void *);
71 1.1 uwe
72 1.8 thorpej CFATTACH_DECL(audiocs_ebus, sizeof(struct cs4231_ebus_softc),
73 1.9 thorpej cs4231_ebus_match, cs4231_ebus_attach, NULL, NULL);
74 1.1 uwe
75 1.11 wiz /* audio_hw_if methods specific to ebus DMA */
76 1.15 kent static int cs4231_ebus_round_blocksize(void *, int, int,
77 1.15 kent const audio_params_t *);
78 1.1 uwe static int cs4231_ebus_trigger_output(void *, void *, void *, int,
79 1.1 uwe void (*)(void *), void *,
80 1.16 kent const audio_params_t *);
81 1.1 uwe static int cs4231_ebus_trigger_input(void *, void *, void *, int,
82 1.1 uwe void (*)(void *), void *,
83 1.16 kent const audio_params_t *);
84 1.1 uwe static int cs4231_ebus_halt_output(void *);
85 1.1 uwe static int cs4231_ebus_halt_input(void *);
86 1.1 uwe
87 1.14 yamt const struct audio_hw_if audiocs_ebus_hw_if = {
88 1.1 uwe cs4231_open,
89 1.1 uwe cs4231_close,
90 1.1 uwe NULL, /* drain */
91 1.1 uwe ad1848_query_encoding,
92 1.1 uwe ad1848_set_params,
93 1.13 uwe cs4231_ebus_round_blocksize,
94 1.1 uwe ad1848_commit_settings,
95 1.1 uwe NULL, /* init_output */
96 1.1 uwe NULL, /* init_input */
97 1.1 uwe NULL, /* start_output */
98 1.1 uwe NULL, /* start_input */
99 1.1 uwe cs4231_ebus_halt_output,
100 1.1 uwe cs4231_ebus_halt_input,
101 1.1 uwe NULL, /* speaker_ctl */
102 1.1 uwe cs4231_getdev,
103 1.1 uwe NULL, /* setfd */
104 1.1 uwe cs4231_set_port,
105 1.1 uwe cs4231_get_port,
106 1.1 uwe cs4231_query_devinfo,
107 1.1 uwe cs4231_malloc,
108 1.1 uwe cs4231_free,
109 1.13 uwe NULL, /* round_buffersize */
110 1.2 uwe NULL, /* mappage */
111 1.1 uwe cs4231_get_props,
112 1.1 uwe cs4231_ebus_trigger_output,
113 1.1 uwe cs4231_ebus_trigger_input,
114 1.1 uwe NULL, /* dev_ioctl */
115 1.22 martin NULL, /* powerstate */
116 1.1 uwe };
117 1.1 uwe
118 1.1 uwe #ifdef AUDIO_DEBUG
119 1.1 uwe static void cs4231_ebus_regdump(char *, struct cs4231_ebus_softc *);
120 1.1 uwe #endif
121 1.1 uwe
122 1.3 uwe static int cs4231_ebus_dma_reset(bus_space_tag_t, bus_space_handle_t);
123 1.1 uwe static int cs4231_ebus_trigger_transfer(struct cs4231_softc *,
124 1.3 uwe struct cs_transfer *,
125 1.3 uwe bus_space_tag_t, bus_space_handle_t,
126 1.1 uwe int, void *, void *, int, void (*)(void *), void *,
127 1.16 kent const audio_params_t *);
128 1.1 uwe static void cs4231_ebus_dma_advance(struct cs_transfer *,
129 1.3 uwe bus_space_tag_t, bus_space_handle_t);
130 1.1 uwe static int cs4231_ebus_dma_intr(struct cs_transfer *,
131 1.3 uwe bus_space_tag_t, bus_space_handle_t);
132 1.1 uwe static int cs4231_ebus_intr(void *);
133 1.1 uwe
134 1.1 uwe
135 1.1 uwe int
136 1.17 kent cs4231_ebus_match(struct device *parent, struct cfdata *cf, void *aux)
137 1.1 uwe {
138 1.17 kent struct ebus_attach_args *ea;
139 1.1 uwe
140 1.17 kent ea = aux;
141 1.1 uwe if (strcmp(ea->ea_name, AUDIOCS_PROM_NAME) == 0)
142 1.17 kent return 1;
143 1.1 uwe #ifdef __sparc__ /* XXX: Krups */
144 1.1 uwe if (strcmp(ea->ea_name, "sound") == 0)
145 1.17 kent return 1;
146 1.1 uwe #endif
147 1.1 uwe
148 1.17 kent return 0;
149 1.1 uwe }
150 1.1 uwe
151 1.1 uwe
152 1.1 uwe void
153 1.17 kent cs4231_ebus_attach(struct device *parent, struct device *self, void *aux)
154 1.17 kent {
155 1.17 kent struct cs4231_ebus_softc *ebsc;
156 1.17 kent struct cs4231_softc *sc;
157 1.17 kent struct ebus_attach_args *ea;
158 1.1 uwe bus_space_handle_t bh;
159 1.1 uwe int i;
160 1.1 uwe
161 1.20 thorpej ebsc = device_private(self);
162 1.17 kent sc = &ebsc->sc_cs4231;
163 1.17 kent ea = aux;
164 1.3 uwe sc->sc_bustag = ebsc->sc_bt = ea->ea_bustag;
165 1.1 uwe sc->sc_dmatag = ea->ea_dmatag;
166 1.1 uwe
167 1.1 uwe /*
168 1.1 uwe * These are the register we get from the prom:
169 1.1 uwe * - CS4231 registers
170 1.1 uwe * - Playback EBus DMA controller
171 1.1 uwe * - Capture EBus DMA controller
172 1.1 uwe * - AUXIO audio register (codec powerdown)
173 1.1 uwe *
174 1.1 uwe * Map my registers in, if they aren't already in virtual
175 1.1 uwe * address space.
176 1.1 uwe */
177 1.4 eeh if (bus_space_map(ea->ea_bustag, EBUS_ADDR_FROM_REG(&ea->ea_reg[0]),
178 1.4 eeh ea->ea_reg[0].size, 0, &bh) != 0) {
179 1.6 uwe printf(": unable to map registers\n");
180 1.4 eeh return;
181 1.1 uwe }
182 1.18 perry
183 1.1 uwe /* XXX: map playback DMA registers (we just know where they are) */
184 1.1 uwe if (bus_space_map(ea->ea_bustag,
185 1.1 uwe BUS_ADDR(0x14, 0x702000), /* XXX: magic num */
186 1.3 uwe EBUS_DMAC_SIZE,
187 1.3 uwe 0, &ebsc->sc_pdmareg) != 0)
188 1.1 uwe {
189 1.6 uwe printf(": unable to map playback DMA registers\n");
190 1.2 uwe return;
191 1.1 uwe }
192 1.1 uwe
193 1.1 uwe /* XXX: map capture DMA registers (we just know where they are) */
194 1.1 uwe if (bus_space_map(ea->ea_bustag,
195 1.1 uwe BUS_ADDR(0x14, 0x704000), /* XXX: magic num */
196 1.3 uwe EBUS_DMAC_SIZE,
197 1.3 uwe 0, &ebsc->sc_cdmareg) != 0)
198 1.1 uwe {
199 1.6 uwe printf(": unable to map capture DMA registers\n");
200 1.2 uwe return;
201 1.1 uwe }
202 1.1 uwe
203 1.1 uwe /* establish interrupt channels */
204 1.1 uwe for (i = 0; i < ea->ea_nintr; ++i)
205 1.1 uwe bus_intr_establish(ea->ea_bustag,
206 1.10 pk ea->ea_intr[i], IPL_AUDIO,
207 1.1 uwe cs4231_ebus_intr, ebsc);
208 1.1 uwe
209 1.1 uwe cs4231_common_attach(sc, bh);
210 1.1 uwe printf("\n");
211 1.1 uwe
212 1.1 uwe /* XXX: todo: move to cs4231_common_attach, pass hw_if as arg? */
213 1.1 uwe audio_attach_mi(&audiocs_ebus_hw_if, sc, &sc->sc_ad1848.sc_dev);
214 1.1 uwe }
215 1.1 uwe
216 1.1 uwe
217 1.13 uwe static int
218 1.17 kent cs4231_ebus_round_blocksize(void *addr, int blk, int mode,
219 1.17 kent const audio_params_t *param)
220 1.13 uwe {
221 1.13 uwe
222 1.13 uwe /* we want to use DMA burst size of 16 words */
223 1.17 kent return blk & -64;
224 1.13 uwe }
225 1.13 uwe
226 1.13 uwe
227 1.1 uwe #ifdef AUDIO_DEBUG
228 1.1 uwe static void
229 1.17 kent cs4231_ebus_regdump(char *label, struct cs4231_ebus_softc *ebsc)
230 1.1 uwe {
231 1.1 uwe /* char bits[128]; */
232 1.1 uwe
233 1.1 uwe printf("cs4231regdump(%s): regs:", label);
234 1.11 wiz /* XXX: dump ebus DMA and aux registers */
235 1.1 uwe ad1848_dump_regs(&ebsc->sc_cs4231.sc_ad1848);
236 1.1 uwe }
237 1.1 uwe #endif /* AUDIO_DEBUG */
238 1.1 uwe
239 1.1 uwe
240 1.1 uwe /* XXX: nothing CS4231-specific in this code... */
241 1.1 uwe static int
242 1.17 kent cs4231_ebus_dma_reset(bus_space_tag_t dt, bus_space_handle_t dh)
243 1.1 uwe {
244 1.3 uwe u_int32_t csr;
245 1.1 uwe int timo;
246 1.1 uwe
247 1.3 uwe /* reset, also clear TC, just in case */
248 1.3 uwe bus_space_write_4(dt, dh, EBUS_DMAC_DCSR, EBDMA_RESET | EBDMA_TC);
249 1.1 uwe
250 1.3 uwe for (timo = 50000; timo != 0; --timo) {
251 1.3 uwe csr = bus_space_read_4(dt, dh, EBUS_DMAC_DCSR);
252 1.3 uwe if ((csr & (EBDMA_CYC_PEND | EBDMA_DRAIN)) == 0)
253 1.1 uwe break;
254 1.3 uwe }
255 1.1 uwe
256 1.1 uwe if (timo == 0) {
257 1.3 uwe char bits[128];
258 1.3 uwe
259 1.3 uwe printf("cs4231_ebus_dma_reset: timed out: csr=%s\n",
260 1.3 uwe bitmask_snprintf(csr, EBUS_DCSR_BITS,
261 1.3 uwe bits, sizeof(bits)));
262 1.17 kent return ETIMEDOUT;
263 1.1 uwe }
264 1.1 uwe
265 1.3 uwe bus_space_write_4(dt, dh, EBUS_DMAC_DCSR, csr & ~EBDMA_RESET);
266 1.17 kent return 0;
267 1.1 uwe }
268 1.1 uwe
269 1.1 uwe
270 1.1 uwe static void
271 1.17 kent cs4231_ebus_dma_advance(struct cs_transfer *t, bus_space_tag_t dt,
272 1.17 kent bus_space_handle_t dh)
273 1.1 uwe {
274 1.1 uwe bus_addr_t dmaaddr;
275 1.1 uwe bus_size_t dmasize;
276 1.1 uwe
277 1.1 uwe cs4231_transfer_advance(t, &dmaaddr, &dmasize);
278 1.3 uwe
279 1.3 uwe bus_space_write_4(dt, dh, EBUS_DMAC_DNBR, (u_int32_t)dmasize);
280 1.3 uwe bus_space_write_4(dt, dh, EBUS_DMAC_DNAR, (u_int32_t)dmaaddr);
281 1.1 uwe }
282 1.1 uwe
283 1.1 uwe
284 1.1 uwe /*
285 1.13 uwe * Trigger transfer "t" using DMA controller at "dt"/"dh".
286 1.1 uwe * "iswrite" defines direction of the transfer.
287 1.1 uwe */
288 1.1 uwe static int
289 1.17 kent cs4231_ebus_trigger_transfer(
290 1.17 kent struct cs4231_softc *sc,
291 1.17 kent struct cs_transfer *t,
292 1.17 kent bus_space_tag_t dt,
293 1.17 kent bus_space_handle_t dh,
294 1.17 kent int iswrite,
295 1.17 kent void *start, void *end,
296 1.17 kent int blksize,
297 1.17 kent void (*intr)(void *),
298 1.17 kent void *arg,
299 1.17 kent const audio_params_t *param)
300 1.1 uwe {
301 1.17 kent uint32_t csr;
302 1.1 uwe bus_addr_t dmaaddr;
303 1.1 uwe bus_size_t dmasize;
304 1.1 uwe int ret;
305 1.1 uwe
306 1.1 uwe ret = cs4231_transfer_init(sc, t, &dmaaddr, &dmasize,
307 1.1 uwe start, end, blksize, intr, arg);
308 1.1 uwe if (ret != 0)
309 1.17 kent return ret;
310 1.1 uwe
311 1.3 uwe ret = cs4231_ebus_dma_reset(dt, dh);
312 1.1 uwe if (ret != 0)
313 1.17 kent return ret;
314 1.1 uwe
315 1.5 martin csr = bus_space_read_4(dt, dh, EBUS_DMAC_DCSR);
316 1.5 martin bus_space_write_4(dt, dh, EBUS_DMAC_DCSR,
317 1.3 uwe csr | EBDMA_EN_NEXT | (iswrite ? EBDMA_WRITE : 0)
318 1.13 uwe | EBDMA_EN_DMA | EBDMA_EN_CNT | EBDMA_INT_EN
319 1.13 uwe | EBDMA_BURST_SIZE_16);
320 1.3 uwe
321 1.3 uwe /* first load: propagated to DACR/DBCR */
322 1.17 kent bus_space_write_4(dt, dh, EBUS_DMAC_DNBR, (uint32_t)dmasize);
323 1.17 kent bus_space_write_4(dt, dh, EBUS_DMAC_DNAR, (uint32_t)dmaaddr);
324 1.1 uwe
325 1.1 uwe /* next load: goes to DNAR/DNBR */
326 1.3 uwe cs4231_ebus_dma_advance(t, dt, dh);
327 1.1 uwe
328 1.17 kent return 0;
329 1.1 uwe }
330 1.1 uwe
331 1.1 uwe
332 1.1 uwe static int
333 1.17 kent cs4231_ebus_trigger_output(void *addr, void *start, void *end, int blksize,
334 1.17 kent void (*intr)(void *), void *arg,
335 1.17 kent const audio_params_t *param)
336 1.1 uwe {
337 1.17 kent struct cs4231_ebus_softc *ebsc;
338 1.17 kent struct cs4231_softc *sc;
339 1.3 uwe int cfg, ret;
340 1.1 uwe
341 1.17 kent ebsc = addr;
342 1.17 kent sc = &ebsc->sc_cs4231;
343 1.3 uwe ret = cs4231_ebus_trigger_transfer(sc, &sc->sc_playback,
344 1.3 uwe ebsc->sc_bt, ebsc->sc_pdmareg,
345 1.3 uwe 0, /* iswrite */
346 1.1 uwe start, end, blksize,
347 1.3 uwe intr, arg, param);
348 1.1 uwe if (ret != 0)
349 1.17 kent return ret;
350 1.1 uwe
351 1.1 uwe ad_write(&sc->sc_ad1848, SP_LOWER_BASE_COUNT, 0xff);
352 1.1 uwe ad_write(&sc->sc_ad1848, SP_UPPER_BASE_COUNT, 0xff);
353 1.1 uwe
354 1.1 uwe cfg = ad_read(&sc->sc_ad1848, SP_INTERFACE_CONFIG);
355 1.3 uwe ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG, cfg | PLAYBACK_ENABLE);
356 1.1 uwe
357 1.17 kent return 0;
358 1.1 uwe }
359 1.1 uwe
360 1.1 uwe
361 1.1 uwe static int
362 1.17 kent cs4231_ebus_trigger_input(void *addr, void *start, void *end, int blksize,
363 1.17 kent void (*intr)(void *), void *arg,
364 1.17 kent const audio_params_t *param)
365 1.1 uwe {
366 1.17 kent struct cs4231_ebus_softc *ebsc;
367 1.17 kent struct cs4231_softc *sc;
368 1.3 uwe int cfg, ret;
369 1.1 uwe
370 1.17 kent ebsc = addr;
371 1.17 kent sc = &ebsc->sc_cs4231;
372 1.3 uwe ret = cs4231_ebus_trigger_transfer(sc, &sc->sc_capture,
373 1.3 uwe ebsc->sc_bt, ebsc->sc_cdmareg,
374 1.3 uwe 1, /* iswrite */
375 1.1 uwe start, end, blksize,
376 1.3 uwe intr, arg, param);
377 1.1 uwe if (ret != 0)
378 1.17 kent return ret;
379 1.1 uwe
380 1.1 uwe ad_write(&sc->sc_ad1848, CS_LOWER_REC_CNT, 0xff);
381 1.1 uwe ad_write(&sc->sc_ad1848, CS_UPPER_REC_CNT, 0xff);
382 1.1 uwe
383 1.1 uwe cfg = ad_read(&sc->sc_ad1848, SP_INTERFACE_CONFIG);
384 1.3 uwe ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG, cfg | CAPTURE_ENABLE);
385 1.1 uwe
386 1.17 kent return 0;
387 1.1 uwe }
388 1.1 uwe
389 1.1 uwe
390 1.1 uwe static int
391 1.17 kent cs4231_ebus_halt_output(void *addr)
392 1.1 uwe {
393 1.17 kent struct cs4231_ebus_softc *ebsc;
394 1.17 kent struct cs4231_softc *sc;
395 1.3 uwe u_int32_t csr;
396 1.1 uwe int cfg;
397 1.1 uwe
398 1.17 kent ebsc = addr;
399 1.17 kent sc = &ebsc->sc_cs4231;
400 1.1 uwe sc->sc_playback.t_active = 0;
401 1.3 uwe
402 1.3 uwe csr = bus_space_read_4(ebsc->sc_bt, ebsc->sc_pdmareg, EBUS_DMAC_DCSR);
403 1.3 uwe bus_space_write_4(ebsc->sc_bt, ebsc->sc_pdmareg, EBUS_DMAC_DCSR,
404 1.3 uwe csr & ~EBDMA_EN_DMA);
405 1.1 uwe
406 1.1 uwe cfg = ad_read(&sc->sc_ad1848, SP_INTERFACE_CONFIG);
407 1.3 uwe ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG,
408 1.3 uwe cfg & ~PLAYBACK_ENABLE);
409 1.1 uwe
410 1.17 kent return 0;
411 1.1 uwe }
412 1.1 uwe
413 1.1 uwe
414 1.1 uwe static int
415 1.17 kent cs4231_ebus_halt_input(void *addr)
416 1.1 uwe {
417 1.17 kent struct cs4231_ebus_softc *ebsc;
418 1.17 kent struct cs4231_softc *sc;
419 1.17 kent uint32_t csr;
420 1.1 uwe int cfg;
421 1.1 uwe
422 1.17 kent ebsc = addr;
423 1.17 kent sc = &ebsc->sc_cs4231;
424 1.1 uwe sc->sc_capture.t_active = 0;
425 1.3 uwe
426 1.3 uwe csr = bus_space_read_4(ebsc->sc_bt, ebsc->sc_cdmareg, EBUS_DMAC_DCSR);
427 1.3 uwe bus_space_write_4(ebsc->sc_bt, ebsc->sc_cdmareg, EBUS_DMAC_DCSR,
428 1.3 uwe csr & ~EBDMA_EN_DMA);
429 1.1 uwe
430 1.1 uwe cfg = ad_read(&sc->sc_ad1848, SP_INTERFACE_CONFIG);
431 1.3 uwe ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG,
432 1.3 uwe cfg & ~CAPTURE_ENABLE);
433 1.1 uwe
434 1.17 kent return 0;
435 1.1 uwe }
436 1.1 uwe
437 1.1 uwe
438 1.1 uwe static int
439 1.17 kent cs4231_ebus_dma_intr(struct cs_transfer *t, bus_space_tag_t dt,
440 1.17 kent bus_space_handle_t dh)
441 1.1 uwe {
442 1.17 kent uint32_t csr;
443 1.1 uwe #ifdef AUDIO_DEBUG
444 1.1 uwe char bits[128];
445 1.1 uwe #endif
446 1.1 uwe
447 1.1 uwe /* read DMA status, clear TC bit by writing it back */
448 1.3 uwe csr = bus_space_read_4(dt, dh, EBUS_DMAC_DCSR);
449 1.3 uwe bus_space_write_4(dt, dh, EBUS_DMAC_DCSR, csr);
450 1.1 uwe DPRINTF(("audiocs: %s dcsr=%s\n", t->t_name,
451 1.1 uwe bitmask_snprintf(csr, EBUS_DCSR_BITS, bits, sizeof(bits))));
452 1.1 uwe
453 1.1 uwe if (csr & EBDMA_ERR_PEND) {
454 1.1 uwe ++t->t_ierrcnt.ev_count;
455 1.1 uwe printf("audiocs: %s DMA error, resetting\n", t->t_name);
456 1.3 uwe cs4231_ebus_dma_reset(dt, dh);
457 1.1 uwe /* how to notify audio(9)??? */
458 1.17 kent return 1;
459 1.1 uwe }
460 1.1 uwe
461 1.1 uwe if ((csr & EBDMA_INT_PEND) == 0)
462 1.17 kent return 0;
463 1.1 uwe
464 1.1 uwe ++t->t_intrcnt.ev_count;
465 1.1 uwe
466 1.1 uwe if ((csr & EBDMA_TC) == 0) { /* can this happen? */
467 1.1 uwe printf("audiocs: %s INT_PEND but !TC\n", t->t_name);
468 1.17 kent return 1;
469 1.1 uwe }
470 1.1 uwe
471 1.1 uwe if (!t->t_active)
472 1.17 kent return 1;
473 1.1 uwe
474 1.3 uwe cs4231_ebus_dma_advance(t, dt, dh);
475 1.1 uwe
476 1.11 wiz /* call audio(9) framework while DMA is chugging along */
477 1.1 uwe if (t->t_intr != NULL)
478 1.1 uwe (*t->t_intr)(t->t_arg);
479 1.17 kent return 1;
480 1.1 uwe }
481 1.1 uwe
482 1.1 uwe
483 1.1 uwe static int
484 1.17 kent cs4231_ebus_intr(void *arg)
485 1.1 uwe {
486 1.17 kent struct cs4231_ebus_softc *ebsc;
487 1.17 kent struct cs4231_softc *sc;
488 1.1 uwe int status;
489 1.1 uwe int ret;
490 1.1 uwe #ifdef AUDIO_DEBUG
491 1.1 uwe char bits[128];
492 1.1 uwe #endif
493 1.1 uwe
494 1.17 kent ebsc = arg;
495 1.17 kent sc = &ebsc->sc_cs4231;
496 1.1 uwe status = ADREAD(&sc->sc_ad1848, AD1848_STATUS);
497 1.1 uwe
498 1.1 uwe #ifdef AUDIO_DEBUG
499 1.1 uwe if (cs4231_ebus_debug > 1)
500 1.1 uwe cs4231_ebus_regdump("audiointr", ebsc);
501 1.1 uwe
502 1.1 uwe DPRINTF(("%s: status: %s\n", sc->sc_ad1848.sc_dev.dv_xname,
503 1.1 uwe bitmask_snprintf(status, AD_R2_BITS, bits, sizeof(bits))));
504 1.1 uwe #endif
505 1.1 uwe
506 1.1 uwe if (status & INTERRUPT_STATUS) {
507 1.1 uwe #ifdef AUDIO_DEBUG
508 1.2 uwe int reason;
509 1.1 uwe
510 1.1 uwe reason = ad_read(&sc->sc_ad1848, CS_IRQ_STATUS);
511 1.1 uwe DPRINTF(("%s: i24: %s\n", sc->sc_ad1848.sc_dev.dv_xname,
512 1.1 uwe bitmask_snprintf(reason, CS_I24_BITS, bits, sizeof(bits))));
513 1.1 uwe #endif
514 1.1 uwe /* clear interrupt from ad1848 */
515 1.1 uwe ADWRITE(&sc->sc_ad1848, AD1848_STATUS, 0);
516 1.1 uwe }
517 1.1 uwe
518 1.1 uwe ret = 0;
519 1.1 uwe
520 1.3 uwe if (cs4231_ebus_dma_intr(&sc->sc_capture,
521 1.3 uwe ebsc->sc_bt, ebsc->sc_cdmareg) != 0)
522 1.3 uwe {
523 1.2 uwe ++sc->sc_intrcnt.ev_count;
524 1.2 uwe ret = 1;
525 1.1 uwe }
526 1.1 uwe
527 1.3 uwe if (cs4231_ebus_dma_intr(&sc->sc_playback,
528 1.3 uwe ebsc->sc_bt, ebsc->sc_pdmareg) != 0)
529 1.3 uwe {
530 1.2 uwe ++sc->sc_intrcnt.ev_count;
531 1.2 uwe ret = 1;
532 1.1 uwe }
533 1.1 uwe
534 1.17 kent return ret;
535 1.1 uwe }
536