cs4231_ebus.c revision 1.24 1 1.24 ad /* $NetBSD: cs4231_ebus.c,v 1.24 2007/12/03 15:34:32 ad Exp $ */
2 1.1 uwe
3 1.1 uwe /*
4 1.1 uwe * Copyright (c) 2002 Valeriy E. Ushakov
5 1.1 uwe * All rights reserved.
6 1.1 uwe *
7 1.1 uwe * Redistribution and use in source and binary forms, with or without
8 1.1 uwe * modification, are permitted provided that the following conditions
9 1.1 uwe * are met:
10 1.1 uwe * 1. Redistributions of source code must retain the above copyright
11 1.1 uwe * notice, this list of conditions and the following disclaimer.
12 1.1 uwe * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 uwe * notice, this list of conditions and the following disclaimer in the
14 1.1 uwe * documentation and/or other materials provided with the distribution.
15 1.1 uwe * 3. The name of the author may not be used to endorse or promote products
16 1.1 uwe * derived from this software without specific prior written permission
17 1.1 uwe *
18 1.1 uwe * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 1.1 uwe * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 1.1 uwe * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 1.1 uwe * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 1.1 uwe * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 1.1 uwe * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 1.1 uwe * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 1.1 uwe * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 1.1 uwe * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 1.1 uwe * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 1.1 uwe */
29 1.12 lukem
30 1.12 lukem #include <sys/cdefs.h>
31 1.24 ad __KERNEL_RCSID(0, "$NetBSD: cs4231_ebus.c,v 1.24 2007/12/03 15:34:32 ad Exp $");
32 1.1 uwe
33 1.1 uwe #include <sys/param.h>
34 1.1 uwe #include <sys/systm.h>
35 1.1 uwe #include <sys/errno.h>
36 1.1 uwe #include <sys/device.h>
37 1.1 uwe #include <sys/malloc.h>
38 1.24 ad #include <sys/cpu.h>
39 1.1 uwe
40 1.1 uwe #include <machine/autoconf.h>
41 1.24 ad
42 1.1 uwe #include <dev/ebus/ebusreg.h>
43 1.1 uwe #include <dev/ebus/ebusvar.h>
44 1.1 uwe
45 1.1 uwe #include <sys/audioio.h>
46 1.1 uwe #include <dev/audio_if.h>
47 1.1 uwe
48 1.1 uwe #include <dev/ic/ad1848reg.h>
49 1.1 uwe #include <dev/ic/cs4231reg.h>
50 1.1 uwe #include <dev/ic/ad1848var.h>
51 1.1 uwe #include <dev/ic/cs4231var.h>
52 1.1 uwe
53 1.1 uwe #ifdef AUDIO_DEBUG
54 1.1 uwe int cs4231_ebus_debug = 0;
55 1.2 uwe #define DPRINTF(x) if (cs4231_ebus_debug) printf x
56 1.1 uwe #else
57 1.1 uwe #define DPRINTF(x)
58 1.1 uwe #endif
59 1.1 uwe
60 1.1 uwe
61 1.1 uwe struct cs4231_ebus_softc {
62 1.1 uwe struct cs4231_softc sc_cs4231;
63 1.1 uwe
64 1.24 ad void *sc_pint;
65 1.24 ad void *sc_rint;
66 1.3 uwe bus_space_tag_t sc_bt;
67 1.3 uwe bus_space_handle_t sc_pdmareg; /* playback DMA */
68 1.3 uwe bus_space_handle_t sc_cdmareg; /* record DMA */
69 1.1 uwe };
70 1.1 uwe
71 1.1 uwe
72 1.1 uwe void cs4231_ebus_attach(struct device *, struct device *, void *);
73 1.1 uwe int cs4231_ebus_match(struct device *, struct cfdata *, void *);
74 1.1 uwe
75 1.24 ad static void cs4231_ebus_pint(void *);
76 1.24 ad static void cs4231_ebus_rint(void *);
77 1.24 ad
78 1.8 thorpej CFATTACH_DECL(audiocs_ebus, sizeof(struct cs4231_ebus_softc),
79 1.9 thorpej cs4231_ebus_match, cs4231_ebus_attach, NULL, NULL);
80 1.1 uwe
81 1.11 wiz /* audio_hw_if methods specific to ebus DMA */
82 1.15 kent static int cs4231_ebus_round_blocksize(void *, int, int,
83 1.15 kent const audio_params_t *);
84 1.1 uwe static int cs4231_ebus_trigger_output(void *, void *, void *, int,
85 1.1 uwe void (*)(void *), void *,
86 1.16 kent const audio_params_t *);
87 1.1 uwe static int cs4231_ebus_trigger_input(void *, void *, void *, int,
88 1.1 uwe void (*)(void *), void *,
89 1.16 kent const audio_params_t *);
90 1.1 uwe static int cs4231_ebus_halt_output(void *);
91 1.1 uwe static int cs4231_ebus_halt_input(void *);
92 1.1 uwe
93 1.14 yamt const struct audio_hw_if audiocs_ebus_hw_if = {
94 1.1 uwe cs4231_open,
95 1.1 uwe cs4231_close,
96 1.1 uwe NULL, /* drain */
97 1.1 uwe ad1848_query_encoding,
98 1.1 uwe ad1848_set_params,
99 1.13 uwe cs4231_ebus_round_blocksize,
100 1.1 uwe ad1848_commit_settings,
101 1.1 uwe NULL, /* init_output */
102 1.1 uwe NULL, /* init_input */
103 1.1 uwe NULL, /* start_output */
104 1.1 uwe NULL, /* start_input */
105 1.1 uwe cs4231_ebus_halt_output,
106 1.1 uwe cs4231_ebus_halt_input,
107 1.1 uwe NULL, /* speaker_ctl */
108 1.1 uwe cs4231_getdev,
109 1.1 uwe NULL, /* setfd */
110 1.1 uwe cs4231_set_port,
111 1.1 uwe cs4231_get_port,
112 1.1 uwe cs4231_query_devinfo,
113 1.1 uwe cs4231_malloc,
114 1.1 uwe cs4231_free,
115 1.13 uwe NULL, /* round_buffersize */
116 1.2 uwe NULL, /* mappage */
117 1.1 uwe cs4231_get_props,
118 1.1 uwe cs4231_ebus_trigger_output,
119 1.1 uwe cs4231_ebus_trigger_input,
120 1.1 uwe NULL, /* dev_ioctl */
121 1.22 martin NULL, /* powerstate */
122 1.1 uwe };
123 1.1 uwe
124 1.1 uwe #ifdef AUDIO_DEBUG
125 1.1 uwe static void cs4231_ebus_regdump(char *, struct cs4231_ebus_softc *);
126 1.1 uwe #endif
127 1.1 uwe
128 1.3 uwe static int cs4231_ebus_dma_reset(bus_space_tag_t, bus_space_handle_t);
129 1.1 uwe static int cs4231_ebus_trigger_transfer(struct cs4231_softc *,
130 1.3 uwe struct cs_transfer *,
131 1.3 uwe bus_space_tag_t, bus_space_handle_t,
132 1.1 uwe int, void *, void *, int, void (*)(void *), void *,
133 1.16 kent const audio_params_t *);
134 1.1 uwe static void cs4231_ebus_dma_advance(struct cs_transfer *,
135 1.3 uwe bus_space_tag_t, bus_space_handle_t);
136 1.1 uwe static int cs4231_ebus_dma_intr(struct cs_transfer *,
137 1.24 ad bus_space_tag_t, bus_space_handle_t,
138 1.24 ad void *);
139 1.1 uwe static int cs4231_ebus_intr(void *);
140 1.1 uwe
141 1.1 uwe
142 1.1 uwe int
143 1.17 kent cs4231_ebus_match(struct device *parent, struct cfdata *cf, void *aux)
144 1.1 uwe {
145 1.17 kent struct ebus_attach_args *ea;
146 1.1 uwe
147 1.17 kent ea = aux;
148 1.1 uwe if (strcmp(ea->ea_name, AUDIOCS_PROM_NAME) == 0)
149 1.17 kent return 1;
150 1.1 uwe #ifdef __sparc__ /* XXX: Krups */
151 1.1 uwe if (strcmp(ea->ea_name, "sound") == 0)
152 1.17 kent return 1;
153 1.1 uwe #endif
154 1.1 uwe
155 1.17 kent return 0;
156 1.1 uwe }
157 1.1 uwe
158 1.1 uwe
159 1.1 uwe void
160 1.17 kent cs4231_ebus_attach(struct device *parent, struct device *self, void *aux)
161 1.17 kent {
162 1.17 kent struct cs4231_ebus_softc *ebsc;
163 1.17 kent struct cs4231_softc *sc;
164 1.17 kent struct ebus_attach_args *ea;
165 1.1 uwe bus_space_handle_t bh;
166 1.1 uwe int i;
167 1.1 uwe
168 1.20 thorpej ebsc = device_private(self);
169 1.17 kent sc = &ebsc->sc_cs4231;
170 1.17 kent ea = aux;
171 1.3 uwe sc->sc_bustag = ebsc->sc_bt = ea->ea_bustag;
172 1.1 uwe sc->sc_dmatag = ea->ea_dmatag;
173 1.1 uwe
174 1.24 ad ebsc->sc_pint = softint_establish(SOFTINT_SERIAL,
175 1.24 ad cs4231_ebus_pint, ebsc);
176 1.24 ad ebsc->sc_rint = softint_establish(SOFTINT_SERIAL,
177 1.24 ad cs4231_ebus_rint, ebsc);
178 1.24 ad
179 1.1 uwe /*
180 1.1 uwe * These are the register we get from the prom:
181 1.1 uwe * - CS4231 registers
182 1.1 uwe * - Playback EBus DMA controller
183 1.1 uwe * - Capture EBus DMA controller
184 1.1 uwe * - AUXIO audio register (codec powerdown)
185 1.1 uwe *
186 1.1 uwe * Map my registers in, if they aren't already in virtual
187 1.1 uwe * address space.
188 1.1 uwe */
189 1.4 eeh if (bus_space_map(ea->ea_bustag, EBUS_ADDR_FROM_REG(&ea->ea_reg[0]),
190 1.4 eeh ea->ea_reg[0].size, 0, &bh) != 0) {
191 1.6 uwe printf(": unable to map registers\n");
192 1.4 eeh return;
193 1.1 uwe }
194 1.18 perry
195 1.1 uwe /* XXX: map playback DMA registers (we just know where they are) */
196 1.1 uwe if (bus_space_map(ea->ea_bustag,
197 1.1 uwe BUS_ADDR(0x14, 0x702000), /* XXX: magic num */
198 1.3 uwe EBUS_DMAC_SIZE,
199 1.3 uwe 0, &ebsc->sc_pdmareg) != 0)
200 1.1 uwe {
201 1.6 uwe printf(": unable to map playback DMA registers\n");
202 1.2 uwe return;
203 1.1 uwe }
204 1.1 uwe
205 1.1 uwe /* XXX: map capture DMA registers (we just know where they are) */
206 1.1 uwe if (bus_space_map(ea->ea_bustag,
207 1.1 uwe BUS_ADDR(0x14, 0x704000), /* XXX: magic num */
208 1.3 uwe EBUS_DMAC_SIZE,
209 1.3 uwe 0, &ebsc->sc_cdmareg) != 0)
210 1.1 uwe {
211 1.6 uwe printf(": unable to map capture DMA registers\n");
212 1.2 uwe return;
213 1.1 uwe }
214 1.1 uwe
215 1.1 uwe /* establish interrupt channels */
216 1.1 uwe for (i = 0; i < ea->ea_nintr; ++i)
217 1.1 uwe bus_intr_establish(ea->ea_bustag,
218 1.24 ad ea->ea_intr[i], IPL_SCHED,
219 1.1 uwe cs4231_ebus_intr, ebsc);
220 1.1 uwe
221 1.1 uwe cs4231_common_attach(sc, bh);
222 1.1 uwe printf("\n");
223 1.1 uwe
224 1.1 uwe /* XXX: todo: move to cs4231_common_attach, pass hw_if as arg? */
225 1.1 uwe audio_attach_mi(&audiocs_ebus_hw_if, sc, &sc->sc_ad1848.sc_dev);
226 1.1 uwe }
227 1.1 uwe
228 1.1 uwe
229 1.13 uwe static int
230 1.17 kent cs4231_ebus_round_blocksize(void *addr, int blk, int mode,
231 1.17 kent const audio_params_t *param)
232 1.13 uwe {
233 1.13 uwe
234 1.13 uwe /* we want to use DMA burst size of 16 words */
235 1.17 kent return blk & -64;
236 1.13 uwe }
237 1.13 uwe
238 1.13 uwe
239 1.1 uwe #ifdef AUDIO_DEBUG
240 1.1 uwe static void
241 1.17 kent cs4231_ebus_regdump(char *label, struct cs4231_ebus_softc *ebsc)
242 1.1 uwe {
243 1.1 uwe /* char bits[128]; */
244 1.1 uwe
245 1.1 uwe printf("cs4231regdump(%s): regs:", label);
246 1.11 wiz /* XXX: dump ebus DMA and aux registers */
247 1.1 uwe ad1848_dump_regs(&ebsc->sc_cs4231.sc_ad1848);
248 1.1 uwe }
249 1.1 uwe #endif /* AUDIO_DEBUG */
250 1.1 uwe
251 1.1 uwe
252 1.1 uwe /* XXX: nothing CS4231-specific in this code... */
253 1.1 uwe static int
254 1.17 kent cs4231_ebus_dma_reset(bus_space_tag_t dt, bus_space_handle_t dh)
255 1.1 uwe {
256 1.3 uwe u_int32_t csr;
257 1.1 uwe int timo;
258 1.1 uwe
259 1.3 uwe /* reset, also clear TC, just in case */
260 1.3 uwe bus_space_write_4(dt, dh, EBUS_DMAC_DCSR, EBDMA_RESET | EBDMA_TC);
261 1.1 uwe
262 1.3 uwe for (timo = 50000; timo != 0; --timo) {
263 1.3 uwe csr = bus_space_read_4(dt, dh, EBUS_DMAC_DCSR);
264 1.3 uwe if ((csr & (EBDMA_CYC_PEND | EBDMA_DRAIN)) == 0)
265 1.1 uwe break;
266 1.3 uwe }
267 1.1 uwe
268 1.1 uwe if (timo == 0) {
269 1.3 uwe char bits[128];
270 1.3 uwe
271 1.3 uwe printf("cs4231_ebus_dma_reset: timed out: csr=%s\n",
272 1.3 uwe bitmask_snprintf(csr, EBUS_DCSR_BITS,
273 1.3 uwe bits, sizeof(bits)));
274 1.17 kent return ETIMEDOUT;
275 1.1 uwe }
276 1.1 uwe
277 1.3 uwe bus_space_write_4(dt, dh, EBUS_DMAC_DCSR, csr & ~EBDMA_RESET);
278 1.17 kent return 0;
279 1.1 uwe }
280 1.1 uwe
281 1.1 uwe
282 1.1 uwe static void
283 1.17 kent cs4231_ebus_dma_advance(struct cs_transfer *t, bus_space_tag_t dt,
284 1.17 kent bus_space_handle_t dh)
285 1.1 uwe {
286 1.1 uwe bus_addr_t dmaaddr;
287 1.1 uwe bus_size_t dmasize;
288 1.1 uwe
289 1.1 uwe cs4231_transfer_advance(t, &dmaaddr, &dmasize);
290 1.3 uwe
291 1.3 uwe bus_space_write_4(dt, dh, EBUS_DMAC_DNBR, (u_int32_t)dmasize);
292 1.3 uwe bus_space_write_4(dt, dh, EBUS_DMAC_DNAR, (u_int32_t)dmaaddr);
293 1.1 uwe }
294 1.1 uwe
295 1.1 uwe
296 1.1 uwe /*
297 1.13 uwe * Trigger transfer "t" using DMA controller at "dt"/"dh".
298 1.1 uwe * "iswrite" defines direction of the transfer.
299 1.1 uwe */
300 1.1 uwe static int
301 1.17 kent cs4231_ebus_trigger_transfer(
302 1.17 kent struct cs4231_softc *sc,
303 1.17 kent struct cs_transfer *t,
304 1.17 kent bus_space_tag_t dt,
305 1.17 kent bus_space_handle_t dh,
306 1.17 kent int iswrite,
307 1.17 kent void *start, void *end,
308 1.17 kent int blksize,
309 1.17 kent void (*intr)(void *),
310 1.17 kent void *arg,
311 1.17 kent const audio_params_t *param)
312 1.1 uwe {
313 1.17 kent uint32_t csr;
314 1.1 uwe bus_addr_t dmaaddr;
315 1.1 uwe bus_size_t dmasize;
316 1.1 uwe int ret;
317 1.1 uwe
318 1.1 uwe ret = cs4231_transfer_init(sc, t, &dmaaddr, &dmasize,
319 1.1 uwe start, end, blksize, intr, arg);
320 1.1 uwe if (ret != 0)
321 1.17 kent return ret;
322 1.1 uwe
323 1.3 uwe ret = cs4231_ebus_dma_reset(dt, dh);
324 1.1 uwe if (ret != 0)
325 1.17 kent return ret;
326 1.1 uwe
327 1.5 martin csr = bus_space_read_4(dt, dh, EBUS_DMAC_DCSR);
328 1.5 martin bus_space_write_4(dt, dh, EBUS_DMAC_DCSR,
329 1.3 uwe csr | EBDMA_EN_NEXT | (iswrite ? EBDMA_WRITE : 0)
330 1.13 uwe | EBDMA_EN_DMA | EBDMA_EN_CNT | EBDMA_INT_EN
331 1.13 uwe | EBDMA_BURST_SIZE_16);
332 1.3 uwe
333 1.3 uwe /* first load: propagated to DACR/DBCR */
334 1.17 kent bus_space_write_4(dt, dh, EBUS_DMAC_DNBR, (uint32_t)dmasize);
335 1.17 kent bus_space_write_4(dt, dh, EBUS_DMAC_DNAR, (uint32_t)dmaaddr);
336 1.1 uwe
337 1.1 uwe /* next load: goes to DNAR/DNBR */
338 1.3 uwe cs4231_ebus_dma_advance(t, dt, dh);
339 1.1 uwe
340 1.17 kent return 0;
341 1.1 uwe }
342 1.1 uwe
343 1.1 uwe
344 1.1 uwe static int
345 1.17 kent cs4231_ebus_trigger_output(void *addr, void *start, void *end, int blksize,
346 1.17 kent void (*intr)(void *), void *arg,
347 1.17 kent const audio_params_t *param)
348 1.1 uwe {
349 1.17 kent struct cs4231_ebus_softc *ebsc;
350 1.17 kent struct cs4231_softc *sc;
351 1.3 uwe int cfg, ret;
352 1.1 uwe
353 1.17 kent ebsc = addr;
354 1.17 kent sc = &ebsc->sc_cs4231;
355 1.3 uwe ret = cs4231_ebus_trigger_transfer(sc, &sc->sc_playback,
356 1.3 uwe ebsc->sc_bt, ebsc->sc_pdmareg,
357 1.3 uwe 0, /* iswrite */
358 1.1 uwe start, end, blksize,
359 1.3 uwe intr, arg, param);
360 1.1 uwe if (ret != 0)
361 1.17 kent return ret;
362 1.1 uwe
363 1.1 uwe ad_write(&sc->sc_ad1848, SP_LOWER_BASE_COUNT, 0xff);
364 1.1 uwe ad_write(&sc->sc_ad1848, SP_UPPER_BASE_COUNT, 0xff);
365 1.1 uwe
366 1.1 uwe cfg = ad_read(&sc->sc_ad1848, SP_INTERFACE_CONFIG);
367 1.3 uwe ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG, cfg | PLAYBACK_ENABLE);
368 1.1 uwe
369 1.17 kent return 0;
370 1.1 uwe }
371 1.1 uwe
372 1.1 uwe
373 1.1 uwe static int
374 1.17 kent cs4231_ebus_trigger_input(void *addr, void *start, void *end, int blksize,
375 1.17 kent void (*intr)(void *), void *arg,
376 1.17 kent const audio_params_t *param)
377 1.1 uwe {
378 1.17 kent struct cs4231_ebus_softc *ebsc;
379 1.17 kent struct cs4231_softc *sc;
380 1.3 uwe int cfg, ret;
381 1.1 uwe
382 1.17 kent ebsc = addr;
383 1.17 kent sc = &ebsc->sc_cs4231;
384 1.3 uwe ret = cs4231_ebus_trigger_transfer(sc, &sc->sc_capture,
385 1.3 uwe ebsc->sc_bt, ebsc->sc_cdmareg,
386 1.3 uwe 1, /* iswrite */
387 1.1 uwe start, end, blksize,
388 1.3 uwe intr, arg, param);
389 1.1 uwe if (ret != 0)
390 1.17 kent return ret;
391 1.1 uwe
392 1.1 uwe ad_write(&sc->sc_ad1848, CS_LOWER_REC_CNT, 0xff);
393 1.1 uwe ad_write(&sc->sc_ad1848, CS_UPPER_REC_CNT, 0xff);
394 1.1 uwe
395 1.1 uwe cfg = ad_read(&sc->sc_ad1848, SP_INTERFACE_CONFIG);
396 1.3 uwe ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG, cfg | CAPTURE_ENABLE);
397 1.1 uwe
398 1.17 kent return 0;
399 1.1 uwe }
400 1.1 uwe
401 1.1 uwe
402 1.1 uwe static int
403 1.17 kent cs4231_ebus_halt_output(void *addr)
404 1.1 uwe {
405 1.17 kent struct cs4231_ebus_softc *ebsc;
406 1.17 kent struct cs4231_softc *sc;
407 1.3 uwe u_int32_t csr;
408 1.1 uwe int cfg;
409 1.1 uwe
410 1.17 kent ebsc = addr;
411 1.17 kent sc = &ebsc->sc_cs4231;
412 1.1 uwe sc->sc_playback.t_active = 0;
413 1.3 uwe
414 1.3 uwe csr = bus_space_read_4(ebsc->sc_bt, ebsc->sc_pdmareg, EBUS_DMAC_DCSR);
415 1.3 uwe bus_space_write_4(ebsc->sc_bt, ebsc->sc_pdmareg, EBUS_DMAC_DCSR,
416 1.3 uwe csr & ~EBDMA_EN_DMA);
417 1.1 uwe
418 1.1 uwe cfg = ad_read(&sc->sc_ad1848, SP_INTERFACE_CONFIG);
419 1.3 uwe ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG,
420 1.3 uwe cfg & ~PLAYBACK_ENABLE);
421 1.1 uwe
422 1.17 kent return 0;
423 1.1 uwe }
424 1.1 uwe
425 1.1 uwe
426 1.1 uwe static int
427 1.17 kent cs4231_ebus_halt_input(void *addr)
428 1.1 uwe {
429 1.17 kent struct cs4231_ebus_softc *ebsc;
430 1.17 kent struct cs4231_softc *sc;
431 1.17 kent uint32_t csr;
432 1.1 uwe int cfg;
433 1.1 uwe
434 1.17 kent ebsc = addr;
435 1.17 kent sc = &ebsc->sc_cs4231;
436 1.1 uwe sc->sc_capture.t_active = 0;
437 1.3 uwe
438 1.3 uwe csr = bus_space_read_4(ebsc->sc_bt, ebsc->sc_cdmareg, EBUS_DMAC_DCSR);
439 1.3 uwe bus_space_write_4(ebsc->sc_bt, ebsc->sc_cdmareg, EBUS_DMAC_DCSR,
440 1.3 uwe csr & ~EBDMA_EN_DMA);
441 1.1 uwe
442 1.1 uwe cfg = ad_read(&sc->sc_ad1848, SP_INTERFACE_CONFIG);
443 1.3 uwe ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG,
444 1.3 uwe cfg & ~CAPTURE_ENABLE);
445 1.1 uwe
446 1.17 kent return 0;
447 1.1 uwe }
448 1.1 uwe
449 1.1 uwe
450 1.1 uwe static int
451 1.17 kent cs4231_ebus_dma_intr(struct cs_transfer *t, bus_space_tag_t dt,
452 1.24 ad bus_space_handle_t dh, void *sih)
453 1.1 uwe {
454 1.17 kent uint32_t csr;
455 1.1 uwe #ifdef AUDIO_DEBUG
456 1.1 uwe char bits[128];
457 1.1 uwe #endif
458 1.1 uwe
459 1.1 uwe /* read DMA status, clear TC bit by writing it back */
460 1.3 uwe csr = bus_space_read_4(dt, dh, EBUS_DMAC_DCSR);
461 1.3 uwe bus_space_write_4(dt, dh, EBUS_DMAC_DCSR, csr);
462 1.1 uwe DPRINTF(("audiocs: %s dcsr=%s\n", t->t_name,
463 1.1 uwe bitmask_snprintf(csr, EBUS_DCSR_BITS, bits, sizeof(bits))));
464 1.1 uwe
465 1.1 uwe if (csr & EBDMA_ERR_PEND) {
466 1.1 uwe ++t->t_ierrcnt.ev_count;
467 1.1 uwe printf("audiocs: %s DMA error, resetting\n", t->t_name);
468 1.3 uwe cs4231_ebus_dma_reset(dt, dh);
469 1.1 uwe /* how to notify audio(9)??? */
470 1.17 kent return 1;
471 1.1 uwe }
472 1.1 uwe
473 1.1 uwe if ((csr & EBDMA_INT_PEND) == 0)
474 1.17 kent return 0;
475 1.1 uwe
476 1.1 uwe ++t->t_intrcnt.ev_count;
477 1.1 uwe
478 1.1 uwe if ((csr & EBDMA_TC) == 0) { /* can this happen? */
479 1.1 uwe printf("audiocs: %s INT_PEND but !TC\n", t->t_name);
480 1.17 kent return 1;
481 1.1 uwe }
482 1.1 uwe
483 1.1 uwe if (!t->t_active)
484 1.17 kent return 1;
485 1.1 uwe
486 1.3 uwe cs4231_ebus_dma_advance(t, dt, dh);
487 1.1 uwe
488 1.11 wiz /* call audio(9) framework while DMA is chugging along */
489 1.1 uwe if (t->t_intr != NULL)
490 1.24 ad softint_schedule(sih);
491 1.17 kent return 1;
492 1.1 uwe }
493 1.1 uwe
494 1.1 uwe
495 1.1 uwe static int
496 1.17 kent cs4231_ebus_intr(void *arg)
497 1.1 uwe {
498 1.17 kent struct cs4231_ebus_softc *ebsc;
499 1.17 kent struct cs4231_softc *sc;
500 1.1 uwe int status;
501 1.1 uwe int ret;
502 1.1 uwe #ifdef AUDIO_DEBUG
503 1.1 uwe char bits[128];
504 1.1 uwe #endif
505 1.1 uwe
506 1.17 kent ebsc = arg;
507 1.17 kent sc = &ebsc->sc_cs4231;
508 1.1 uwe status = ADREAD(&sc->sc_ad1848, AD1848_STATUS);
509 1.1 uwe
510 1.1 uwe #ifdef AUDIO_DEBUG
511 1.1 uwe if (cs4231_ebus_debug > 1)
512 1.1 uwe cs4231_ebus_regdump("audiointr", ebsc);
513 1.1 uwe
514 1.1 uwe DPRINTF(("%s: status: %s\n", sc->sc_ad1848.sc_dev.dv_xname,
515 1.1 uwe bitmask_snprintf(status, AD_R2_BITS, bits, sizeof(bits))));
516 1.1 uwe #endif
517 1.1 uwe
518 1.1 uwe if (status & INTERRUPT_STATUS) {
519 1.1 uwe #ifdef AUDIO_DEBUG
520 1.2 uwe int reason;
521 1.1 uwe
522 1.1 uwe reason = ad_read(&sc->sc_ad1848, CS_IRQ_STATUS);
523 1.1 uwe DPRINTF(("%s: i24: %s\n", sc->sc_ad1848.sc_dev.dv_xname,
524 1.1 uwe bitmask_snprintf(reason, CS_I24_BITS, bits, sizeof(bits))));
525 1.1 uwe #endif
526 1.1 uwe /* clear interrupt from ad1848 */
527 1.1 uwe ADWRITE(&sc->sc_ad1848, AD1848_STATUS, 0);
528 1.1 uwe }
529 1.1 uwe
530 1.1 uwe ret = 0;
531 1.1 uwe
532 1.24 ad if (cs4231_ebus_dma_intr(&sc->sc_capture, ebsc->sc_bt,
533 1.24 ad ebsc->sc_cdmareg, ebsc->sc_rint) != 0)
534 1.3 uwe {
535 1.2 uwe ++sc->sc_intrcnt.ev_count;
536 1.2 uwe ret = 1;
537 1.1 uwe }
538 1.1 uwe
539 1.24 ad if (cs4231_ebus_dma_intr(&sc->sc_playback, ebsc->sc_bt,
540 1.24 ad ebsc->sc_pdmareg, ebsc->sc_pint) != 0)
541 1.3 uwe {
542 1.2 uwe ++sc->sc_intrcnt.ev_count;
543 1.2 uwe ret = 1;
544 1.1 uwe }
545 1.1 uwe
546 1.17 kent return ret;
547 1.1 uwe }
548 1.24 ad
549 1.24 ad static void
550 1.24 ad cs4231_ebus_pint(void *cookie)
551 1.24 ad {
552 1.24 ad struct cs4231_softc *sc = cookie;
553 1.24 ad struct cs_transfer *t = &sc->sc_playback;
554 1.24 ad
555 1.24 ad if (t->t_intr != NULL)
556 1.24 ad (*t->t_intr)(t->t_arg);
557 1.24 ad }
558 1.24 ad
559 1.24 ad static void
560 1.24 ad cs4231_ebus_rint(void *cookie)
561 1.24 ad {
562 1.24 ad struct cs4231_softc *sc = cookie;
563 1.24 ad struct cs_transfer *t = &sc->sc_capture;
564 1.24 ad
565 1.24 ad if (t->t_intr != NULL)
566 1.24 ad (*t->t_intr)(t->t_arg);
567 1.24 ad }
568