cs4231_ebus.c revision 1.3 1 1.3 uwe /* $NetBSD: cs4231_ebus.c,v 1.3 2002/03/21 04:09:27 uwe Exp $ */
2 1.1 uwe
3 1.1 uwe /*
4 1.1 uwe * Copyright (c) 2002 Valeriy E. Ushakov
5 1.1 uwe * All rights reserved.
6 1.1 uwe *
7 1.1 uwe * Redistribution and use in source and binary forms, with or without
8 1.1 uwe * modification, are permitted provided that the following conditions
9 1.1 uwe * are met:
10 1.1 uwe * 1. Redistributions of source code must retain the above copyright
11 1.1 uwe * notice, this list of conditions and the following disclaimer.
12 1.1 uwe * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 uwe * notice, this list of conditions and the following disclaimer in the
14 1.1 uwe * documentation and/or other materials provided with the distribution.
15 1.1 uwe * 3. The name of the author may not be used to endorse or promote products
16 1.1 uwe * derived from this software without specific prior written permission
17 1.1 uwe *
18 1.1 uwe * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 1.1 uwe * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 1.1 uwe * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 1.1 uwe * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 1.1 uwe * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 1.1 uwe * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 1.1 uwe * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 1.1 uwe * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 1.1 uwe * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 1.1 uwe * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 1.1 uwe */
29 1.1 uwe
30 1.1 uwe #include <sys/param.h>
31 1.1 uwe #include <sys/systm.h>
32 1.1 uwe #include <sys/errno.h>
33 1.1 uwe #include <sys/device.h>
34 1.1 uwe #include <sys/malloc.h>
35 1.1 uwe
36 1.1 uwe #include <machine/autoconf.h>
37 1.1 uwe #include <machine/cpu.h>
38 1.1 uwe #include <dev/ebus/ebusreg.h>
39 1.1 uwe #include <dev/ebus/ebusvar.h>
40 1.1 uwe
41 1.1 uwe #include <sys/audioio.h>
42 1.1 uwe #include <dev/audio_if.h>
43 1.1 uwe
44 1.1 uwe #include <dev/ic/ad1848reg.h>
45 1.1 uwe #include <dev/ic/cs4231reg.h>
46 1.1 uwe #include <dev/ic/ad1848var.h>
47 1.1 uwe #include <dev/ic/cs4231var.h>
48 1.1 uwe
49 1.1 uwe #ifdef AUDIO_DEBUG
50 1.1 uwe int cs4231_ebus_debug = 0;
51 1.2 uwe #define DPRINTF(x) if (cs4231_ebus_debug) printf x
52 1.1 uwe #else
53 1.1 uwe #define DPRINTF(x)
54 1.1 uwe #endif
55 1.1 uwe
56 1.1 uwe
57 1.1 uwe struct cs4231_ebus_softc {
58 1.1 uwe struct cs4231_softc sc_cs4231;
59 1.1 uwe
60 1.3 uwe bus_space_tag_t sc_bt;
61 1.3 uwe bus_space_handle_t sc_pdmareg; /* playback DMA */
62 1.3 uwe bus_space_handle_t sc_cdmareg; /* record DMA */
63 1.1 uwe };
64 1.1 uwe
65 1.1 uwe
66 1.1 uwe void cs4231_ebus_attach(struct device *, struct device *, void *);
67 1.1 uwe int cs4231_ebus_match(struct device *, struct cfdata *, void *);
68 1.1 uwe
69 1.1 uwe struct cfattach audiocs_ebus_ca = {
70 1.1 uwe sizeof(struct cs4231_ebus_softc), cs4231_ebus_match, cs4231_ebus_attach
71 1.1 uwe };
72 1.1 uwe
73 1.1 uwe
74 1.1 uwe /* audio_hw_if methods specific to ebus dma */
75 1.1 uwe static int cs4231_ebus_trigger_output(void *, void *, void *, int,
76 1.1 uwe void (*)(void *), void *,
77 1.1 uwe struct audio_params *);
78 1.1 uwe static int cs4231_ebus_trigger_input(void *, void *, void *, int,
79 1.1 uwe void (*)(void *), void *,
80 1.1 uwe struct audio_params *);
81 1.1 uwe static int cs4231_ebus_halt_output(void *);
82 1.1 uwe static int cs4231_ebus_halt_input(void *);
83 1.1 uwe
84 1.1 uwe struct audio_hw_if audiocs_ebus_hw_if = {
85 1.1 uwe cs4231_open,
86 1.1 uwe cs4231_close,
87 1.1 uwe NULL, /* drain */
88 1.1 uwe ad1848_query_encoding,
89 1.1 uwe ad1848_set_params,
90 1.1 uwe cs4231_round_blocksize,
91 1.1 uwe ad1848_commit_settings,
92 1.1 uwe NULL, /* init_output */
93 1.1 uwe NULL, /* init_input */
94 1.1 uwe NULL, /* start_output */
95 1.1 uwe NULL, /* start_input */
96 1.1 uwe cs4231_ebus_halt_output,
97 1.1 uwe cs4231_ebus_halt_input,
98 1.1 uwe NULL, /* speaker_ctl */
99 1.1 uwe cs4231_getdev,
100 1.1 uwe NULL, /* setfd */
101 1.1 uwe cs4231_set_port,
102 1.1 uwe cs4231_get_port,
103 1.1 uwe cs4231_query_devinfo,
104 1.1 uwe cs4231_malloc,
105 1.1 uwe cs4231_free,
106 1.1 uwe cs4231_round_buffersize,
107 1.2 uwe NULL, /* mappage */
108 1.1 uwe cs4231_get_props,
109 1.1 uwe cs4231_ebus_trigger_output,
110 1.1 uwe cs4231_ebus_trigger_input,
111 1.1 uwe NULL, /* dev_ioctl */
112 1.1 uwe };
113 1.1 uwe
114 1.1 uwe #ifdef AUDIO_DEBUG
115 1.1 uwe static void cs4231_ebus_regdump(char *, struct cs4231_ebus_softc *);
116 1.1 uwe #endif
117 1.1 uwe
118 1.3 uwe static int cs4231_ebus_dma_reset(bus_space_tag_t, bus_space_handle_t);
119 1.1 uwe static int cs4231_ebus_trigger_transfer(struct cs4231_softc *,
120 1.3 uwe struct cs_transfer *,
121 1.3 uwe bus_space_tag_t, bus_space_handle_t,
122 1.1 uwe int, void *, void *, int, void (*)(void *), void *,
123 1.1 uwe struct audio_params *);
124 1.1 uwe static void cs4231_ebus_dma_advance(struct cs_transfer *,
125 1.3 uwe bus_space_tag_t, bus_space_handle_t);
126 1.1 uwe static int cs4231_ebus_dma_intr(struct cs_transfer *,
127 1.3 uwe bus_space_tag_t, bus_space_handle_t);
128 1.1 uwe static int cs4231_ebus_intr(void *);
129 1.1 uwe
130 1.1 uwe
131 1.1 uwe int
132 1.1 uwe cs4231_ebus_match(parent, cf, aux)
133 1.1 uwe struct device *parent;
134 1.1 uwe struct cfdata *cf;
135 1.1 uwe void *aux;
136 1.1 uwe {
137 1.1 uwe struct ebus_attach_args *ea = aux;
138 1.1 uwe
139 1.1 uwe if (strcmp(ea->ea_name, AUDIOCS_PROM_NAME) == 0)
140 1.1 uwe return (1);
141 1.1 uwe #ifdef __sparc__ /* XXX: Krups */
142 1.1 uwe if (strcmp(ea->ea_name, "sound") == 0)
143 1.1 uwe return (1);
144 1.1 uwe #endif
145 1.1 uwe
146 1.1 uwe return (0);
147 1.1 uwe }
148 1.1 uwe
149 1.1 uwe
150 1.1 uwe void
151 1.1 uwe cs4231_ebus_attach(parent, self, aux)
152 1.1 uwe struct device *parent, *self;
153 1.1 uwe void *aux;
154 1.1 uwe {
155 1.1 uwe struct cs4231_ebus_softc *ebsc = (struct cs4231_ebus_softc *)self;
156 1.1 uwe struct cs4231_softc *sc = &ebsc->sc_cs4231;
157 1.1 uwe struct ebus_attach_args *ea = aux;
158 1.1 uwe bus_space_handle_t bh;
159 1.1 uwe int i;
160 1.1 uwe
161 1.3 uwe sc->sc_bustag = ebsc->sc_bt = ea->ea_bustag;
162 1.1 uwe sc->sc_dmatag = ea->ea_dmatag;
163 1.1 uwe
164 1.1 uwe /*
165 1.1 uwe * These are the register we get from the prom:
166 1.1 uwe * - CS4231 registers
167 1.1 uwe * - Playback EBus DMA controller
168 1.1 uwe * - Capture EBus DMA controller
169 1.1 uwe * - AUXIO audio register (codec powerdown)
170 1.1 uwe *
171 1.1 uwe * Map my registers in, if they aren't already in virtual
172 1.1 uwe * address space.
173 1.1 uwe */
174 1.1 uwe if (ea->ea_nvaddr) {
175 1.1 uwe bh = (bus_space_handle_t)ea->ea_vaddr[0];
176 1.1 uwe } else {
177 1.1 uwe if (bus_space_map(ea->ea_bustag,
178 1.1 uwe EBUS_ADDR_FROM_REG(&ea->ea_reg[0]),
179 1.1 uwe ea->ea_reg[0].size,
180 1.3 uwe 0, &bh) != 0)
181 1.1 uwe {
182 1.1 uwe printf("%s: unable to map registers\n",
183 1.1 uwe self->dv_xname);
184 1.1 uwe return;
185 1.1 uwe }
186 1.1 uwe }
187 1.1 uwe
188 1.1 uwe /* XXX: map playback DMA registers (we just know where they are) */
189 1.1 uwe if (bus_space_map(ea->ea_bustag,
190 1.1 uwe BUS_ADDR(0x14, 0x702000), /* XXX: magic num */
191 1.3 uwe EBUS_DMAC_SIZE,
192 1.3 uwe 0, &ebsc->sc_pdmareg) != 0)
193 1.1 uwe {
194 1.2 uwe printf("%s: unable to map playback DMA registers\n",
195 1.2 uwe self->dv_xname);
196 1.2 uwe return;
197 1.1 uwe }
198 1.1 uwe
199 1.1 uwe /* XXX: map capture DMA registers (we just know where they are) */
200 1.1 uwe if (bus_space_map(ea->ea_bustag,
201 1.1 uwe BUS_ADDR(0x14, 0x704000), /* XXX: magic num */
202 1.3 uwe EBUS_DMAC_SIZE,
203 1.3 uwe 0, &ebsc->sc_cdmareg) != 0)
204 1.1 uwe {
205 1.2 uwe printf("%s: unable to map capture DMA registers\n",
206 1.2 uwe self->dv_xname);
207 1.2 uwe return;
208 1.1 uwe }
209 1.1 uwe
210 1.1 uwe /* establish interrupt channels */
211 1.1 uwe for (i = 0; i < ea->ea_nintr; ++i)
212 1.1 uwe bus_intr_establish(ea->ea_bustag,
213 1.1 uwe ea->ea_intr[i], IPL_AUDIO, 0,
214 1.1 uwe cs4231_ebus_intr, ebsc);
215 1.1 uwe
216 1.1 uwe cs4231_common_attach(sc, bh);
217 1.1 uwe printf("\n");
218 1.1 uwe
219 1.1 uwe /* XXX: todo: move to cs4231_common_attach, pass hw_if as arg? */
220 1.1 uwe audio_attach_mi(&audiocs_ebus_hw_if, sc, &sc->sc_ad1848.sc_dev);
221 1.1 uwe }
222 1.1 uwe
223 1.1 uwe
224 1.1 uwe #ifdef AUDIO_DEBUG
225 1.1 uwe static void
226 1.1 uwe cs4231_ebus_regdump(label, ebsc)
227 1.1 uwe char *label;
228 1.1 uwe struct cs4231_ebus_softc *ebsc;
229 1.1 uwe {
230 1.1 uwe /* char bits[128]; */
231 1.1 uwe
232 1.1 uwe printf("cs4231regdump(%s): regs:", label);
233 1.1 uwe /* XXX: dump ebus dma and aux registers */
234 1.1 uwe ad1848_dump_regs(&ebsc->sc_cs4231.sc_ad1848);
235 1.1 uwe }
236 1.1 uwe #endif /* AUDIO_DEBUG */
237 1.1 uwe
238 1.1 uwe
239 1.1 uwe /* XXX: nothing CS4231-specific in this code... */
240 1.1 uwe static int
241 1.3 uwe cs4231_ebus_dma_reset(dt, dh)
242 1.3 uwe bus_space_tag_t dt;
243 1.3 uwe bus_space_handle_t dh;
244 1.1 uwe {
245 1.3 uwe u_int32_t csr;
246 1.1 uwe int timo;
247 1.1 uwe
248 1.3 uwe /* reset, also clear TC, just in case */
249 1.3 uwe bus_space_write_4(dt, dh, EBUS_DMAC_DCSR, EBDMA_RESET | EBDMA_TC);
250 1.1 uwe
251 1.3 uwe for (timo = 50000; timo != 0; --timo) {
252 1.3 uwe csr = bus_space_read_4(dt, dh, EBUS_DMAC_DCSR);
253 1.3 uwe if ((csr & (EBDMA_CYC_PEND | EBDMA_DRAIN)) == 0)
254 1.1 uwe break;
255 1.3 uwe }
256 1.1 uwe
257 1.1 uwe if (timo == 0) {
258 1.3 uwe char bits[128];
259 1.3 uwe
260 1.3 uwe printf("cs4231_ebus_dma_reset: timed out: csr=%s\n",
261 1.3 uwe bitmask_snprintf(csr, EBUS_DCSR_BITS,
262 1.3 uwe bits, sizeof(bits)));
263 1.1 uwe return (ETIMEDOUT);
264 1.1 uwe }
265 1.1 uwe
266 1.3 uwe bus_space_write_4(dt, dh, EBUS_DMAC_DCSR, csr & ~EBDMA_RESET);
267 1.1 uwe return (0);
268 1.1 uwe }
269 1.1 uwe
270 1.1 uwe
271 1.1 uwe static void
272 1.3 uwe cs4231_ebus_dma_advance(t, dt, dh)
273 1.1 uwe struct cs_transfer *t;
274 1.3 uwe bus_space_tag_t dt;
275 1.3 uwe bus_space_handle_t dh;
276 1.1 uwe {
277 1.1 uwe bus_addr_t dmaaddr;
278 1.1 uwe bus_size_t dmasize;
279 1.1 uwe
280 1.1 uwe cs4231_transfer_advance(t, &dmaaddr, &dmasize);
281 1.3 uwe
282 1.3 uwe bus_space_write_4(dt, dh, EBUS_DMAC_DNBR, (u_int32_t)dmasize);
283 1.3 uwe bus_space_write_4(dt, dh, EBUS_DMAC_DNAR, (u_int32_t)dmaaddr);
284 1.1 uwe }
285 1.1 uwe
286 1.1 uwe
287 1.1 uwe /*
288 1.1 uwe * Trigger transfer "t" using DMA controller "dmac".
289 1.1 uwe * "iswrite" defines direction of the transfer.
290 1.1 uwe */
291 1.1 uwe static int
292 1.3 uwe cs4231_ebus_trigger_transfer(sc, t, dt, dh, iswrite,
293 1.1 uwe start, end, blksize,
294 1.1 uwe intr, arg, param)
295 1.1 uwe struct cs4231_softc *sc;
296 1.1 uwe struct cs_transfer *t;
297 1.3 uwe bus_space_tag_t dt;
298 1.3 uwe bus_space_handle_t dh;
299 1.1 uwe int iswrite;
300 1.1 uwe void *start, *end;
301 1.1 uwe int blksize;
302 1.1 uwe void (*intr)(void *);
303 1.1 uwe void *arg;
304 1.1 uwe struct audio_params *param;
305 1.1 uwe {
306 1.3 uwe u_int32_t csr;
307 1.1 uwe bus_addr_t dmaaddr;
308 1.1 uwe bus_size_t dmasize;
309 1.1 uwe int ret;
310 1.1 uwe
311 1.1 uwe ret = cs4231_transfer_init(sc, t, &dmaaddr, &dmasize,
312 1.1 uwe start, end, blksize, intr, arg);
313 1.1 uwe if (ret != 0)
314 1.1 uwe return (ret);
315 1.1 uwe
316 1.3 uwe ret = cs4231_ebus_dma_reset(dt, dh);
317 1.1 uwe if (ret != 0)
318 1.1 uwe return (ret);
319 1.1 uwe
320 1.3 uwe csr = bus_space_read_4(dh, dh, EBUS_DMAC_DCSR);
321 1.3 uwe bus_space_write_4(dh, dh, EBUS_DMAC_DCSR,
322 1.3 uwe csr | EBDMA_EN_NEXT | (iswrite ? EBDMA_WRITE : 0)
323 1.3 uwe | EBDMA_EN_DMA | EBDMA_EN_CNT | EBDMA_INT_EN);
324 1.3 uwe
325 1.3 uwe /* first load: propagated to DACR/DBCR */
326 1.3 uwe bus_space_write_4(dt, dh, EBUS_DMAC_DNBR, (u_int32_t)dmasize);
327 1.3 uwe bus_space_write_4(dt, dh, EBUS_DMAC_DNAR, (u_int32_t)dmaaddr);
328 1.1 uwe
329 1.1 uwe /* next load: goes to DNAR/DNBR */
330 1.3 uwe cs4231_ebus_dma_advance(t, dt, dh);
331 1.1 uwe
332 1.1 uwe return (0);
333 1.1 uwe }
334 1.1 uwe
335 1.1 uwe
336 1.1 uwe static int
337 1.1 uwe cs4231_ebus_trigger_output(addr, start, end, blksize, intr, arg, param)
338 1.1 uwe void *addr;
339 1.1 uwe void *start, *end;
340 1.1 uwe int blksize;
341 1.1 uwe void (*intr)(void *);
342 1.1 uwe void *arg;
343 1.1 uwe struct audio_params *param;
344 1.1 uwe {
345 1.1 uwe struct cs4231_ebus_softc *ebsc = addr;
346 1.1 uwe struct cs4231_softc *sc = &ebsc->sc_cs4231;
347 1.3 uwe int cfg, ret;
348 1.1 uwe
349 1.3 uwe ret = cs4231_ebus_trigger_transfer(sc, &sc->sc_playback,
350 1.3 uwe ebsc->sc_bt, ebsc->sc_pdmareg,
351 1.3 uwe 0, /* iswrite */
352 1.1 uwe start, end, blksize,
353 1.3 uwe intr, arg, param);
354 1.1 uwe if (ret != 0)
355 1.1 uwe return (ret);
356 1.1 uwe
357 1.1 uwe ad_write(&sc->sc_ad1848, SP_LOWER_BASE_COUNT, 0xff);
358 1.1 uwe ad_write(&sc->sc_ad1848, SP_UPPER_BASE_COUNT, 0xff);
359 1.1 uwe
360 1.1 uwe cfg = ad_read(&sc->sc_ad1848, SP_INTERFACE_CONFIG);
361 1.3 uwe ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG, cfg | PLAYBACK_ENABLE);
362 1.1 uwe
363 1.1 uwe return (0);
364 1.1 uwe }
365 1.1 uwe
366 1.1 uwe
367 1.1 uwe static int
368 1.1 uwe cs4231_ebus_trigger_input(addr, start, end, blksize, intr, arg, param)
369 1.1 uwe void *addr;
370 1.1 uwe void *start, *end;
371 1.1 uwe int blksize;
372 1.1 uwe void (*intr)(void *);
373 1.1 uwe void *arg;
374 1.1 uwe struct audio_params *param;
375 1.1 uwe {
376 1.1 uwe struct cs4231_ebus_softc *ebsc = addr;
377 1.1 uwe struct cs4231_softc *sc = &ebsc->sc_cs4231;
378 1.3 uwe int cfg, ret;
379 1.1 uwe
380 1.3 uwe ret = cs4231_ebus_trigger_transfer(sc, &sc->sc_capture,
381 1.3 uwe ebsc->sc_bt, ebsc->sc_cdmareg,
382 1.3 uwe 1, /* iswrite */
383 1.1 uwe start, end, blksize,
384 1.3 uwe intr, arg, param);
385 1.1 uwe if (ret != 0)
386 1.1 uwe return (ret);
387 1.1 uwe
388 1.1 uwe ad_write(&sc->sc_ad1848, CS_LOWER_REC_CNT, 0xff);
389 1.1 uwe ad_write(&sc->sc_ad1848, CS_UPPER_REC_CNT, 0xff);
390 1.1 uwe
391 1.1 uwe cfg = ad_read(&sc->sc_ad1848, SP_INTERFACE_CONFIG);
392 1.3 uwe ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG, cfg | CAPTURE_ENABLE);
393 1.1 uwe
394 1.1 uwe return (0);
395 1.1 uwe }
396 1.1 uwe
397 1.1 uwe
398 1.1 uwe static int
399 1.1 uwe cs4231_ebus_halt_output(addr)
400 1.1 uwe void *addr;
401 1.1 uwe {
402 1.3 uwe struct cs4231_ebus_softc *ebsc = addr;
403 1.1 uwe struct cs4231_softc *sc = &ebsc->sc_cs4231;
404 1.3 uwe u_int32_t csr;
405 1.1 uwe int cfg;
406 1.1 uwe
407 1.1 uwe sc->sc_playback.t_active = 0;
408 1.3 uwe
409 1.3 uwe csr = bus_space_read_4(ebsc->sc_bt, ebsc->sc_pdmareg, EBUS_DMAC_DCSR);
410 1.3 uwe bus_space_write_4(ebsc->sc_bt, ebsc->sc_pdmareg, EBUS_DMAC_DCSR,
411 1.3 uwe csr & ~EBDMA_EN_DMA);
412 1.1 uwe
413 1.1 uwe cfg = ad_read(&sc->sc_ad1848, SP_INTERFACE_CONFIG);
414 1.3 uwe ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG,
415 1.3 uwe cfg & ~PLAYBACK_ENABLE);
416 1.1 uwe
417 1.1 uwe return (0);
418 1.1 uwe }
419 1.1 uwe
420 1.1 uwe
421 1.1 uwe static int
422 1.1 uwe cs4231_ebus_halt_input(addr)
423 1.1 uwe void *addr;
424 1.1 uwe {
425 1.3 uwe struct cs4231_ebus_softc *ebsc = addr;
426 1.1 uwe struct cs4231_softc *sc = &ebsc->sc_cs4231;
427 1.3 uwe u_int32_t csr;
428 1.1 uwe int cfg;
429 1.1 uwe
430 1.1 uwe sc->sc_capture.t_active = 0;
431 1.3 uwe
432 1.3 uwe csr = bus_space_read_4(ebsc->sc_bt, ebsc->sc_cdmareg, EBUS_DMAC_DCSR);
433 1.3 uwe bus_space_write_4(ebsc->sc_bt, ebsc->sc_cdmareg, EBUS_DMAC_DCSR,
434 1.3 uwe csr & ~EBDMA_EN_DMA);
435 1.1 uwe
436 1.1 uwe cfg = ad_read(&sc->sc_ad1848, SP_INTERFACE_CONFIG);
437 1.3 uwe ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG,
438 1.3 uwe cfg & ~CAPTURE_ENABLE);
439 1.1 uwe
440 1.1 uwe return (0);
441 1.1 uwe }
442 1.1 uwe
443 1.1 uwe
444 1.1 uwe static int
445 1.3 uwe cs4231_ebus_dma_intr(t, dt, dh)
446 1.1 uwe struct cs_transfer *t;
447 1.3 uwe bus_space_tag_t dt;
448 1.3 uwe bus_space_handle_t dh;
449 1.1 uwe {
450 1.1 uwe u_int32_t csr;
451 1.1 uwe #ifdef AUDIO_DEBUG
452 1.1 uwe char bits[128];
453 1.1 uwe #endif
454 1.1 uwe
455 1.1 uwe /* read DMA status, clear TC bit by writing it back */
456 1.3 uwe csr = bus_space_read_4(dt, dh, EBUS_DMAC_DCSR);
457 1.3 uwe bus_space_write_4(dt, dh, EBUS_DMAC_DCSR, csr);
458 1.1 uwe DPRINTF(("audiocs: %s dcsr=%s\n", t->t_name,
459 1.1 uwe bitmask_snprintf(csr, EBUS_DCSR_BITS, bits, sizeof(bits))));
460 1.1 uwe
461 1.1 uwe if (csr & EBDMA_ERR_PEND) {
462 1.1 uwe ++t->t_ierrcnt.ev_count;
463 1.1 uwe printf("audiocs: %s DMA error, resetting\n", t->t_name);
464 1.3 uwe cs4231_ebus_dma_reset(dt, dh);
465 1.1 uwe /* how to notify audio(9)??? */
466 1.1 uwe return (1);
467 1.1 uwe }
468 1.1 uwe
469 1.1 uwe if ((csr & EBDMA_INT_PEND) == 0)
470 1.1 uwe return (0);
471 1.1 uwe
472 1.1 uwe ++t->t_intrcnt.ev_count;
473 1.1 uwe
474 1.1 uwe if ((csr & EBDMA_TC) == 0) { /* can this happen? */
475 1.1 uwe printf("audiocs: %s INT_PEND but !TC\n", t->t_name);
476 1.1 uwe return (1);
477 1.1 uwe }
478 1.1 uwe
479 1.1 uwe if (!t->t_active)
480 1.1 uwe return (1);
481 1.1 uwe
482 1.3 uwe cs4231_ebus_dma_advance(t, dt, dh);
483 1.1 uwe
484 1.1 uwe /* call audio(9) framework while dma is chugging along */
485 1.1 uwe if (t->t_intr != NULL)
486 1.1 uwe (*t->t_intr)(t->t_arg);
487 1.1 uwe return (1);
488 1.1 uwe }
489 1.1 uwe
490 1.1 uwe
491 1.1 uwe static int
492 1.1 uwe cs4231_ebus_intr(arg)
493 1.1 uwe void *arg;
494 1.1 uwe {
495 1.3 uwe struct cs4231_ebus_softc *ebsc = arg;
496 1.1 uwe struct cs4231_softc *sc = &ebsc->sc_cs4231;
497 1.1 uwe int status;
498 1.1 uwe int ret;
499 1.1 uwe #ifdef AUDIO_DEBUG
500 1.1 uwe char bits[128];
501 1.1 uwe #endif
502 1.1 uwe
503 1.1 uwe status = ADREAD(&sc->sc_ad1848, AD1848_STATUS);
504 1.1 uwe
505 1.1 uwe #ifdef AUDIO_DEBUG
506 1.1 uwe if (cs4231_ebus_debug > 1)
507 1.1 uwe cs4231_ebus_regdump("audiointr", ebsc);
508 1.1 uwe
509 1.1 uwe DPRINTF(("%s: status: %s\n", sc->sc_ad1848.sc_dev.dv_xname,
510 1.1 uwe bitmask_snprintf(status, AD_R2_BITS, bits, sizeof(bits))));
511 1.1 uwe #endif
512 1.1 uwe
513 1.1 uwe if (status & INTERRUPT_STATUS) {
514 1.1 uwe #ifdef AUDIO_DEBUG
515 1.2 uwe int reason;
516 1.1 uwe
517 1.1 uwe reason = ad_read(&sc->sc_ad1848, CS_IRQ_STATUS);
518 1.1 uwe DPRINTF(("%s: i24: %s\n", sc->sc_ad1848.sc_dev.dv_xname,
519 1.1 uwe bitmask_snprintf(reason, CS_I24_BITS, bits, sizeof(bits))));
520 1.1 uwe #endif
521 1.1 uwe /* clear interrupt from ad1848 */
522 1.1 uwe ADWRITE(&sc->sc_ad1848, AD1848_STATUS, 0);
523 1.1 uwe }
524 1.1 uwe
525 1.1 uwe ret = 0;
526 1.1 uwe
527 1.3 uwe if (cs4231_ebus_dma_intr(&sc->sc_capture,
528 1.3 uwe ebsc->sc_bt, ebsc->sc_cdmareg) != 0)
529 1.3 uwe {
530 1.2 uwe ++sc->sc_intrcnt.ev_count;
531 1.2 uwe ret = 1;
532 1.1 uwe }
533 1.1 uwe
534 1.3 uwe if (cs4231_ebus_dma_intr(&sc->sc_playback,
535 1.3 uwe ebsc->sc_bt, ebsc->sc_pdmareg) != 0)
536 1.3 uwe {
537 1.2 uwe ++sc->sc_intrcnt.ev_count;
538 1.2 uwe ret = 1;
539 1.1 uwe }
540 1.1 uwe
541 1.1 uwe return (ret);
542 1.1 uwe }
543