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cs4231_ebus.c revision 1.4
      1  1.4  eeh /*	$NetBSD: cs4231_ebus.c,v 1.4 2002/03/21 21:33:57 eeh Exp $ */
      2  1.1  uwe 
      3  1.1  uwe /*
      4  1.1  uwe  * Copyright (c) 2002 Valeriy E. Ushakov
      5  1.1  uwe  * All rights reserved.
      6  1.1  uwe  *
      7  1.1  uwe  * Redistribution and use in source and binary forms, with or without
      8  1.1  uwe  * modification, are permitted provided that the following conditions
      9  1.1  uwe  * are met:
     10  1.1  uwe  * 1. Redistributions of source code must retain the above copyright
     11  1.1  uwe  *    notice, this list of conditions and the following disclaimer.
     12  1.1  uwe  * 2. Redistributions in binary form must reproduce the above copyright
     13  1.1  uwe  *    notice, this list of conditions and the following disclaimer in the
     14  1.1  uwe  *    documentation and/or other materials provided with the distribution.
     15  1.1  uwe  * 3. The name of the author may not be used to endorse or promote products
     16  1.1  uwe  *    derived from this software without specific prior written permission
     17  1.1  uwe  *
     18  1.1  uwe  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     19  1.1  uwe  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     20  1.1  uwe  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     21  1.1  uwe  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     22  1.1  uwe  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     23  1.1  uwe  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     24  1.1  uwe  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     25  1.1  uwe  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     26  1.1  uwe  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     27  1.1  uwe  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     28  1.1  uwe  */
     29  1.1  uwe 
     30  1.1  uwe #include <sys/param.h>
     31  1.1  uwe #include <sys/systm.h>
     32  1.1  uwe #include <sys/errno.h>
     33  1.1  uwe #include <sys/device.h>
     34  1.1  uwe #include <sys/malloc.h>
     35  1.1  uwe 
     36  1.1  uwe #include <machine/autoconf.h>
     37  1.1  uwe #include <machine/cpu.h>
     38  1.1  uwe #include <dev/ebus/ebusreg.h>
     39  1.1  uwe #include <dev/ebus/ebusvar.h>
     40  1.1  uwe 
     41  1.1  uwe #include <sys/audioio.h>
     42  1.1  uwe #include <dev/audio_if.h>
     43  1.1  uwe 
     44  1.1  uwe #include <dev/ic/ad1848reg.h>
     45  1.1  uwe #include <dev/ic/cs4231reg.h>
     46  1.1  uwe #include <dev/ic/ad1848var.h>
     47  1.1  uwe #include <dev/ic/cs4231var.h>
     48  1.1  uwe 
     49  1.1  uwe #ifdef AUDIO_DEBUG
     50  1.1  uwe int cs4231_ebus_debug = 0;
     51  1.2  uwe #define DPRINTF(x)	if (cs4231_ebus_debug) printf x
     52  1.1  uwe #else
     53  1.1  uwe #define DPRINTF(x)
     54  1.1  uwe #endif
     55  1.1  uwe 
     56  1.1  uwe 
     57  1.1  uwe struct cs4231_ebus_softc {
     58  1.1  uwe 	struct cs4231_softc sc_cs4231;
     59  1.1  uwe 
     60  1.3  uwe 	bus_space_tag_t sc_bt;
     61  1.3  uwe 	bus_space_handle_t sc_pdmareg; /* playback DMA */
     62  1.3  uwe 	bus_space_handle_t sc_cdmareg; /* record DMA */
     63  1.1  uwe };
     64  1.1  uwe 
     65  1.1  uwe 
     66  1.1  uwe void	cs4231_ebus_attach(struct device *, struct device *, void *);
     67  1.1  uwe int	cs4231_ebus_match(struct device *, struct cfdata *, void *);
     68  1.1  uwe 
     69  1.1  uwe struct cfattach audiocs_ebus_ca = {
     70  1.1  uwe 	sizeof(struct cs4231_ebus_softc), cs4231_ebus_match, cs4231_ebus_attach
     71  1.1  uwe };
     72  1.1  uwe 
     73  1.1  uwe 
     74  1.1  uwe /* audio_hw_if methods specific to ebus dma */
     75  1.1  uwe static int	cs4231_ebus_trigger_output(void *, void *, void *, int,
     76  1.1  uwe 					   void (*)(void *), void *,
     77  1.1  uwe 					   struct audio_params *);
     78  1.1  uwe static int	cs4231_ebus_trigger_input(void *, void *, void *, int,
     79  1.1  uwe 					  void (*)(void *), void *,
     80  1.1  uwe 					  struct audio_params *);
     81  1.1  uwe static int	cs4231_ebus_halt_output(void *);
     82  1.1  uwe static int	cs4231_ebus_halt_input(void *);
     83  1.1  uwe 
     84  1.1  uwe struct audio_hw_if audiocs_ebus_hw_if = {
     85  1.1  uwe 	cs4231_open,
     86  1.1  uwe 	cs4231_close,
     87  1.1  uwe 	NULL,			/* drain */
     88  1.1  uwe 	ad1848_query_encoding,
     89  1.1  uwe 	ad1848_set_params,
     90  1.1  uwe 	cs4231_round_blocksize,
     91  1.1  uwe 	ad1848_commit_settings,
     92  1.1  uwe 	NULL,			/* init_output */
     93  1.1  uwe 	NULL,			/* init_input */
     94  1.1  uwe 	NULL,			/* start_output */
     95  1.1  uwe 	NULL,			/* start_input */
     96  1.1  uwe 	cs4231_ebus_halt_output,
     97  1.1  uwe 	cs4231_ebus_halt_input,
     98  1.1  uwe 	NULL,			/* speaker_ctl */
     99  1.1  uwe 	cs4231_getdev,
    100  1.1  uwe 	NULL,			/* setfd */
    101  1.1  uwe 	cs4231_set_port,
    102  1.1  uwe 	cs4231_get_port,
    103  1.1  uwe 	cs4231_query_devinfo,
    104  1.1  uwe 	cs4231_malloc,
    105  1.1  uwe 	cs4231_free,
    106  1.1  uwe 	cs4231_round_buffersize,
    107  1.2  uwe 	NULL,			/* mappage */
    108  1.1  uwe 	cs4231_get_props,
    109  1.1  uwe 	cs4231_ebus_trigger_output,
    110  1.1  uwe 	cs4231_ebus_trigger_input,
    111  1.1  uwe 	NULL,			/* dev_ioctl */
    112  1.1  uwe };
    113  1.1  uwe 
    114  1.1  uwe #ifdef AUDIO_DEBUG
    115  1.1  uwe static void	cs4231_ebus_regdump(char *, struct cs4231_ebus_softc *);
    116  1.1  uwe #endif
    117  1.1  uwe 
    118  1.3  uwe static int	cs4231_ebus_dma_reset(bus_space_tag_t, bus_space_handle_t);
    119  1.1  uwe static int	cs4231_ebus_trigger_transfer(struct cs4231_softc *,
    120  1.3  uwe 			struct cs_transfer *,
    121  1.3  uwe 			bus_space_tag_t, bus_space_handle_t,
    122  1.1  uwe 			int, void *, void *, int, void (*)(void *), void *,
    123  1.1  uwe 			struct audio_params *);
    124  1.1  uwe static void	cs4231_ebus_dma_advance(struct cs_transfer *,
    125  1.3  uwe 					bus_space_tag_t, bus_space_handle_t);
    126  1.1  uwe static int	cs4231_ebus_dma_intr(struct cs_transfer *,
    127  1.3  uwe 				     bus_space_tag_t, bus_space_handle_t);
    128  1.1  uwe static int	cs4231_ebus_intr(void *);
    129  1.1  uwe 
    130  1.1  uwe 
    131  1.1  uwe int
    132  1.1  uwe cs4231_ebus_match(parent, cf, aux)
    133  1.1  uwe 	struct device *parent;
    134  1.1  uwe 	struct cfdata *cf;
    135  1.1  uwe 	void *aux;
    136  1.1  uwe {
    137  1.1  uwe 	struct ebus_attach_args *ea = aux;
    138  1.1  uwe 
    139  1.1  uwe 	if (strcmp(ea->ea_name, AUDIOCS_PROM_NAME) == 0)
    140  1.1  uwe 		return (1);
    141  1.1  uwe #ifdef __sparc__		/* XXX: Krups */
    142  1.1  uwe 	if (strcmp(ea->ea_name, "sound") == 0)
    143  1.1  uwe 		return (1);
    144  1.1  uwe #endif
    145  1.1  uwe 
    146  1.1  uwe 	return (0);
    147  1.1  uwe }
    148  1.1  uwe 
    149  1.1  uwe 
    150  1.1  uwe void
    151  1.1  uwe cs4231_ebus_attach(parent, self, aux)
    152  1.1  uwe 	struct device *parent, *self;
    153  1.1  uwe 	void *aux;
    154  1.1  uwe {
    155  1.1  uwe 	struct cs4231_ebus_softc *ebsc = (struct cs4231_ebus_softc *)self;
    156  1.1  uwe 	struct cs4231_softc *sc = &ebsc->sc_cs4231;
    157  1.1  uwe 	struct ebus_attach_args *ea = aux;
    158  1.1  uwe 	bus_space_handle_t bh;
    159  1.1  uwe 	int i;
    160  1.1  uwe 
    161  1.3  uwe 	sc->sc_bustag = ebsc->sc_bt = ea->ea_bustag;
    162  1.1  uwe 	sc->sc_dmatag = ea->ea_dmatag;
    163  1.1  uwe 
    164  1.1  uwe 	/*
    165  1.1  uwe 	 * These are the register we get from the prom:
    166  1.1  uwe 	 *	- CS4231 registers
    167  1.1  uwe 	 *	- Playback EBus DMA controller
    168  1.1  uwe 	 *	- Capture EBus DMA controller
    169  1.1  uwe 	 *	- AUXIO audio register (codec powerdown)
    170  1.1  uwe 	 *
    171  1.1  uwe 	 * Map my registers in, if they aren't already in virtual
    172  1.1  uwe 	 * address space.
    173  1.1  uwe 	 */
    174  1.4  eeh 	if (bus_space_map(ea->ea_bustag, EBUS_ADDR_FROM_REG(&ea->ea_reg[0]),
    175  1.4  eeh 		ea->ea_reg[0].size, 0, &bh) != 0) {
    176  1.4  eeh 		printf("%s: unable to map registers\n",
    177  1.4  eeh 			self->dv_xname);
    178  1.4  eeh 		return;
    179  1.1  uwe 	}
    180  1.4  eeh 
    181  1.1  uwe 	/* XXX: map playback DMA registers (we just know where they are) */
    182  1.1  uwe 	if (bus_space_map(ea->ea_bustag,
    183  1.1  uwe 			  BUS_ADDR(0x14, 0x702000), /* XXX: magic num */
    184  1.3  uwe 			  EBUS_DMAC_SIZE,
    185  1.3  uwe 			  0, &ebsc->sc_pdmareg) != 0)
    186  1.1  uwe 	{
    187  1.2  uwe 		printf("%s: unable to map playback DMA registers\n",
    188  1.2  uwe 		       self->dv_xname);
    189  1.2  uwe 		return;
    190  1.1  uwe 	}
    191  1.1  uwe 
    192  1.1  uwe 	/* XXX: map capture DMA registers (we just know where they are) */
    193  1.1  uwe 	if (bus_space_map(ea->ea_bustag,
    194  1.1  uwe 			  BUS_ADDR(0x14, 0x704000), /* XXX: magic num */
    195  1.3  uwe 			  EBUS_DMAC_SIZE,
    196  1.3  uwe 			  0, &ebsc->sc_cdmareg) != 0)
    197  1.1  uwe 	{
    198  1.2  uwe 		printf("%s: unable to map capture DMA registers\n",
    199  1.2  uwe 		       self->dv_xname);
    200  1.2  uwe 		return;
    201  1.1  uwe 	}
    202  1.1  uwe 
    203  1.1  uwe 	/* establish interrupt channels */
    204  1.1  uwe 	for (i = 0; i < ea->ea_nintr; ++i)
    205  1.1  uwe 		bus_intr_establish(ea->ea_bustag,
    206  1.1  uwe 				   ea->ea_intr[i], IPL_AUDIO, 0,
    207  1.1  uwe 				   cs4231_ebus_intr, ebsc);
    208  1.1  uwe 
    209  1.1  uwe 	cs4231_common_attach(sc, bh);
    210  1.1  uwe 	printf("\n");
    211  1.1  uwe 
    212  1.1  uwe 	/* XXX: todo: move to cs4231_common_attach, pass hw_if as arg? */
    213  1.1  uwe 	audio_attach_mi(&audiocs_ebus_hw_if, sc, &sc->sc_ad1848.sc_dev);
    214  1.1  uwe }
    215  1.1  uwe 
    216  1.1  uwe 
    217  1.1  uwe #ifdef AUDIO_DEBUG
    218  1.1  uwe static void
    219  1.1  uwe cs4231_ebus_regdump(label, ebsc)
    220  1.1  uwe 	char *label;
    221  1.1  uwe 	struct cs4231_ebus_softc *ebsc;
    222  1.1  uwe {
    223  1.1  uwe 	/* char bits[128]; */
    224  1.1  uwe 
    225  1.1  uwe 	printf("cs4231regdump(%s): regs:", label);
    226  1.1  uwe 	/* XXX: dump ebus dma and aux registers */
    227  1.1  uwe 	ad1848_dump_regs(&ebsc->sc_cs4231.sc_ad1848);
    228  1.1  uwe }
    229  1.1  uwe #endif /* AUDIO_DEBUG */
    230  1.1  uwe 
    231  1.1  uwe 
    232  1.1  uwe /* XXX: nothing CS4231-specific in this code... */
    233  1.1  uwe static int
    234  1.3  uwe cs4231_ebus_dma_reset(dt, dh)
    235  1.3  uwe 	bus_space_tag_t dt;
    236  1.3  uwe 	bus_space_handle_t dh;
    237  1.1  uwe {
    238  1.3  uwe 	u_int32_t csr;
    239  1.1  uwe 	int timo;
    240  1.1  uwe 
    241  1.3  uwe 	/* reset, also clear TC, just in case */
    242  1.3  uwe 	bus_space_write_4(dt, dh, EBUS_DMAC_DCSR, EBDMA_RESET | EBDMA_TC);
    243  1.1  uwe 
    244  1.3  uwe 	for (timo = 50000; timo != 0; --timo) {
    245  1.3  uwe 		csr = bus_space_read_4(dt, dh, EBUS_DMAC_DCSR);
    246  1.3  uwe 		if ((csr & (EBDMA_CYC_PEND | EBDMA_DRAIN)) == 0)
    247  1.1  uwe 			break;
    248  1.3  uwe 	}
    249  1.1  uwe 
    250  1.1  uwe 	if (timo == 0) {
    251  1.3  uwe 		char bits[128];
    252  1.3  uwe 
    253  1.3  uwe 		printf("cs4231_ebus_dma_reset: timed out: csr=%s\n",
    254  1.3  uwe 		       bitmask_snprintf(csr, EBUS_DCSR_BITS,
    255  1.3  uwe 					bits, sizeof(bits)));
    256  1.1  uwe 		return (ETIMEDOUT);
    257  1.1  uwe 	}
    258  1.1  uwe 
    259  1.3  uwe 	bus_space_write_4(dt, dh, EBUS_DMAC_DCSR, csr & ~EBDMA_RESET);
    260  1.1  uwe 	return (0);
    261  1.1  uwe }
    262  1.1  uwe 
    263  1.1  uwe 
    264  1.1  uwe static void
    265  1.3  uwe cs4231_ebus_dma_advance(t, dt, dh)
    266  1.1  uwe 	struct cs_transfer *t;
    267  1.3  uwe 	bus_space_tag_t dt;
    268  1.3  uwe 	bus_space_handle_t dh;
    269  1.1  uwe {
    270  1.1  uwe 	bus_addr_t dmaaddr;
    271  1.1  uwe 	bus_size_t dmasize;
    272  1.1  uwe 
    273  1.1  uwe 	cs4231_transfer_advance(t, &dmaaddr, &dmasize);
    274  1.3  uwe 
    275  1.3  uwe 	bus_space_write_4(dt, dh, EBUS_DMAC_DNBR, (u_int32_t)dmasize);
    276  1.3  uwe 	bus_space_write_4(dt, dh, EBUS_DMAC_DNAR, (u_int32_t)dmaaddr);
    277  1.1  uwe }
    278  1.1  uwe 
    279  1.1  uwe 
    280  1.1  uwe /*
    281  1.1  uwe  * Trigger transfer "t" using DMA controller "dmac".
    282  1.1  uwe  * "iswrite" defines direction of the transfer.
    283  1.1  uwe  */
    284  1.1  uwe static int
    285  1.3  uwe cs4231_ebus_trigger_transfer(sc, t, dt, dh, iswrite,
    286  1.1  uwe 			     start, end, blksize,
    287  1.1  uwe 			     intr, arg, param)
    288  1.1  uwe 	struct cs4231_softc *sc;
    289  1.1  uwe 	struct cs_transfer *t;
    290  1.3  uwe 	bus_space_tag_t dt;
    291  1.3  uwe 	bus_space_handle_t dh;
    292  1.1  uwe 	int iswrite;
    293  1.1  uwe 	void *start, *end;
    294  1.1  uwe 	int blksize;
    295  1.1  uwe 	void (*intr)(void *);
    296  1.1  uwe 	void *arg;
    297  1.1  uwe 	struct audio_params *param;
    298  1.1  uwe {
    299  1.3  uwe 	u_int32_t csr;
    300  1.1  uwe 	bus_addr_t dmaaddr;
    301  1.1  uwe 	bus_size_t dmasize;
    302  1.1  uwe 	int ret;
    303  1.1  uwe 
    304  1.1  uwe 	ret = cs4231_transfer_init(sc, t, &dmaaddr, &dmasize,
    305  1.1  uwe 				   start, end, blksize, intr, arg);
    306  1.1  uwe 	if (ret != 0)
    307  1.1  uwe 		return (ret);
    308  1.1  uwe 
    309  1.3  uwe 	ret = cs4231_ebus_dma_reset(dt, dh);
    310  1.1  uwe 	if (ret != 0)
    311  1.1  uwe 		return (ret);
    312  1.1  uwe 
    313  1.3  uwe 	csr = bus_space_read_4(dh, dh, EBUS_DMAC_DCSR);
    314  1.3  uwe 	bus_space_write_4(dh, dh, EBUS_DMAC_DCSR,
    315  1.3  uwe 			  csr | EBDMA_EN_NEXT | (iswrite ? EBDMA_WRITE : 0)
    316  1.3  uwe 			  | EBDMA_EN_DMA | EBDMA_EN_CNT | EBDMA_INT_EN);
    317  1.3  uwe 
    318  1.3  uwe 	/* first load: propagated to DACR/DBCR */
    319  1.3  uwe 	bus_space_write_4(dt, dh, EBUS_DMAC_DNBR, (u_int32_t)dmasize);
    320  1.3  uwe 	bus_space_write_4(dt, dh, EBUS_DMAC_DNAR, (u_int32_t)dmaaddr);
    321  1.1  uwe 
    322  1.1  uwe 	/* next load: goes to DNAR/DNBR */
    323  1.3  uwe 	cs4231_ebus_dma_advance(t, dt, dh);
    324  1.1  uwe 
    325  1.1  uwe 	return (0);
    326  1.1  uwe }
    327  1.1  uwe 
    328  1.1  uwe 
    329  1.1  uwe static int
    330  1.1  uwe cs4231_ebus_trigger_output(addr, start, end, blksize, intr, arg, param)
    331  1.1  uwe 	void *addr;
    332  1.1  uwe 	void *start, *end;
    333  1.1  uwe 	int blksize;
    334  1.1  uwe 	void (*intr)(void *);
    335  1.1  uwe 	void *arg;
    336  1.1  uwe 	struct audio_params *param;
    337  1.1  uwe {
    338  1.1  uwe 	struct cs4231_ebus_softc *ebsc = addr;
    339  1.1  uwe 	struct cs4231_softc *sc = &ebsc->sc_cs4231;
    340  1.3  uwe 	int cfg, ret;
    341  1.1  uwe 
    342  1.3  uwe 	ret = cs4231_ebus_trigger_transfer(sc, &sc->sc_playback,
    343  1.3  uwe 					   ebsc->sc_bt, ebsc->sc_pdmareg,
    344  1.3  uwe 					   0, /* iswrite */
    345  1.1  uwe 					   start, end, blksize,
    346  1.3  uwe 					   intr, arg, param);
    347  1.1  uwe 	if (ret != 0)
    348  1.1  uwe 		return (ret);
    349  1.1  uwe 
    350  1.1  uwe 	ad_write(&sc->sc_ad1848, SP_LOWER_BASE_COUNT, 0xff);
    351  1.1  uwe 	ad_write(&sc->sc_ad1848, SP_UPPER_BASE_COUNT, 0xff);
    352  1.1  uwe 
    353  1.1  uwe 	cfg = ad_read(&sc->sc_ad1848, SP_INTERFACE_CONFIG);
    354  1.3  uwe 	ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG, cfg | PLAYBACK_ENABLE);
    355  1.1  uwe 
    356  1.1  uwe 	return (0);
    357  1.1  uwe }
    358  1.1  uwe 
    359  1.1  uwe 
    360  1.1  uwe static int
    361  1.1  uwe cs4231_ebus_trigger_input(addr, start, end, blksize, intr, arg, param)
    362  1.1  uwe 	void *addr;
    363  1.1  uwe 	void *start, *end;
    364  1.1  uwe 	int blksize;
    365  1.1  uwe 	void (*intr)(void *);
    366  1.1  uwe 	void *arg;
    367  1.1  uwe 	struct audio_params *param;
    368  1.1  uwe {
    369  1.1  uwe 	struct cs4231_ebus_softc *ebsc = addr;
    370  1.1  uwe 	struct cs4231_softc *sc = &ebsc->sc_cs4231;
    371  1.3  uwe 	int cfg, ret;
    372  1.1  uwe 
    373  1.3  uwe 	ret = cs4231_ebus_trigger_transfer(sc, &sc->sc_capture,
    374  1.3  uwe 					   ebsc->sc_bt, ebsc->sc_cdmareg,
    375  1.3  uwe 					   1, /* iswrite */
    376  1.1  uwe 					   start, end, blksize,
    377  1.3  uwe 					   intr, arg, param);
    378  1.1  uwe 	if (ret != 0)
    379  1.1  uwe 		return (ret);
    380  1.1  uwe 
    381  1.1  uwe 	ad_write(&sc->sc_ad1848, CS_LOWER_REC_CNT, 0xff);
    382  1.1  uwe 	ad_write(&sc->sc_ad1848, CS_UPPER_REC_CNT, 0xff);
    383  1.1  uwe 
    384  1.1  uwe 	cfg = ad_read(&sc->sc_ad1848, SP_INTERFACE_CONFIG);
    385  1.3  uwe 	ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG, cfg | CAPTURE_ENABLE);
    386  1.1  uwe 
    387  1.1  uwe 	return (0);
    388  1.1  uwe }
    389  1.1  uwe 
    390  1.1  uwe 
    391  1.1  uwe static int
    392  1.1  uwe cs4231_ebus_halt_output(addr)
    393  1.1  uwe 	void *addr;
    394  1.1  uwe {
    395  1.3  uwe 	struct cs4231_ebus_softc *ebsc = addr;
    396  1.1  uwe 	struct cs4231_softc *sc = &ebsc->sc_cs4231;
    397  1.3  uwe 	u_int32_t csr;
    398  1.1  uwe 	int cfg;
    399  1.1  uwe 
    400  1.1  uwe 	sc->sc_playback.t_active = 0;
    401  1.3  uwe 
    402  1.3  uwe 	csr = bus_space_read_4(ebsc->sc_bt, ebsc->sc_pdmareg, EBUS_DMAC_DCSR);
    403  1.3  uwe 	bus_space_write_4(ebsc->sc_bt, ebsc->sc_pdmareg, EBUS_DMAC_DCSR,
    404  1.3  uwe 			  csr & ~EBDMA_EN_DMA);
    405  1.1  uwe 
    406  1.1  uwe 	cfg = ad_read(&sc->sc_ad1848, SP_INTERFACE_CONFIG);
    407  1.3  uwe 	ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG,
    408  1.3  uwe 		 cfg & ~PLAYBACK_ENABLE);
    409  1.1  uwe 
    410  1.1  uwe 	return (0);
    411  1.1  uwe }
    412  1.1  uwe 
    413  1.1  uwe 
    414  1.1  uwe static int
    415  1.1  uwe cs4231_ebus_halt_input(addr)
    416  1.1  uwe 	void *addr;
    417  1.1  uwe {
    418  1.3  uwe 	struct cs4231_ebus_softc *ebsc = addr;
    419  1.1  uwe 	struct cs4231_softc *sc = &ebsc->sc_cs4231;
    420  1.3  uwe 	u_int32_t csr;
    421  1.1  uwe 	int cfg;
    422  1.1  uwe 
    423  1.1  uwe 	sc->sc_capture.t_active = 0;
    424  1.3  uwe 
    425  1.3  uwe 	csr = bus_space_read_4(ebsc->sc_bt, ebsc->sc_cdmareg, EBUS_DMAC_DCSR);
    426  1.3  uwe 	bus_space_write_4(ebsc->sc_bt, ebsc->sc_cdmareg, EBUS_DMAC_DCSR,
    427  1.3  uwe 			  csr & ~EBDMA_EN_DMA);
    428  1.1  uwe 
    429  1.1  uwe 	cfg = ad_read(&sc->sc_ad1848, SP_INTERFACE_CONFIG);
    430  1.3  uwe 	ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG,
    431  1.3  uwe 		 cfg & ~CAPTURE_ENABLE);
    432  1.1  uwe 
    433  1.1  uwe 	return (0);
    434  1.1  uwe }
    435  1.1  uwe 
    436  1.1  uwe 
    437  1.1  uwe static int
    438  1.3  uwe cs4231_ebus_dma_intr(t, dt, dh)
    439  1.1  uwe 	struct cs_transfer *t;
    440  1.3  uwe 	bus_space_tag_t dt;
    441  1.3  uwe 	bus_space_handle_t dh;
    442  1.1  uwe {
    443  1.1  uwe 	u_int32_t csr;
    444  1.1  uwe #ifdef AUDIO_DEBUG
    445  1.1  uwe 	char bits[128];
    446  1.1  uwe #endif
    447  1.1  uwe 
    448  1.1  uwe 	/* read DMA status, clear TC bit by writing it back */
    449  1.3  uwe 	csr = bus_space_read_4(dt, dh, EBUS_DMAC_DCSR);
    450  1.3  uwe 	bus_space_write_4(dt, dh, EBUS_DMAC_DCSR, csr);
    451  1.1  uwe 	DPRINTF(("audiocs: %s dcsr=%s\n", t->t_name,
    452  1.1  uwe 		 bitmask_snprintf(csr, EBUS_DCSR_BITS, bits, sizeof(bits))));
    453  1.1  uwe 
    454  1.1  uwe 	if (csr & EBDMA_ERR_PEND) {
    455  1.1  uwe 		++t->t_ierrcnt.ev_count;
    456  1.1  uwe 		printf("audiocs: %s DMA error, resetting\n", t->t_name);
    457  1.3  uwe 		cs4231_ebus_dma_reset(dt, dh);
    458  1.1  uwe 		/* how to notify audio(9)??? */
    459  1.1  uwe 		return (1);
    460  1.1  uwe 	}
    461  1.1  uwe 
    462  1.1  uwe 	if ((csr & EBDMA_INT_PEND) == 0)
    463  1.1  uwe 		return (0);
    464  1.1  uwe 
    465  1.1  uwe 	++t->t_intrcnt.ev_count;
    466  1.1  uwe 
    467  1.1  uwe 	if ((csr & EBDMA_TC) == 0) { /* can this happen? */
    468  1.1  uwe 		printf("audiocs: %s INT_PEND but !TC\n", t->t_name);
    469  1.1  uwe 		return (1);
    470  1.1  uwe 	}
    471  1.1  uwe 
    472  1.1  uwe 	if (!t->t_active)
    473  1.1  uwe 		return (1);
    474  1.1  uwe 
    475  1.3  uwe 	cs4231_ebus_dma_advance(t, dt, dh);
    476  1.1  uwe 
    477  1.1  uwe 	/* call audio(9) framework while dma is chugging along */
    478  1.1  uwe 	if (t->t_intr != NULL)
    479  1.1  uwe 		(*t->t_intr)(t->t_arg);
    480  1.1  uwe 	return (1);
    481  1.1  uwe }
    482  1.1  uwe 
    483  1.1  uwe 
    484  1.1  uwe static int
    485  1.1  uwe cs4231_ebus_intr(arg)
    486  1.1  uwe 	void *arg;
    487  1.1  uwe {
    488  1.3  uwe 	struct cs4231_ebus_softc *ebsc = arg;
    489  1.1  uwe 	struct cs4231_softc *sc = &ebsc->sc_cs4231;
    490  1.1  uwe 	int status;
    491  1.1  uwe 	int ret;
    492  1.1  uwe #ifdef AUDIO_DEBUG
    493  1.1  uwe 	char bits[128];
    494  1.1  uwe #endif
    495  1.1  uwe 
    496  1.1  uwe 	status = ADREAD(&sc->sc_ad1848, AD1848_STATUS);
    497  1.1  uwe 
    498  1.1  uwe #ifdef AUDIO_DEBUG
    499  1.1  uwe 	if (cs4231_ebus_debug > 1)
    500  1.1  uwe 		cs4231_ebus_regdump("audiointr", ebsc);
    501  1.1  uwe 
    502  1.1  uwe 	DPRINTF(("%s: status: %s\n", sc->sc_ad1848.sc_dev.dv_xname,
    503  1.1  uwe 		 bitmask_snprintf(status, AD_R2_BITS, bits, sizeof(bits))));
    504  1.1  uwe #endif
    505  1.1  uwe 
    506  1.1  uwe 	if (status & INTERRUPT_STATUS) {
    507  1.1  uwe #ifdef AUDIO_DEBUG
    508  1.2  uwe 		int reason;
    509  1.1  uwe 
    510  1.1  uwe 		reason = ad_read(&sc->sc_ad1848, CS_IRQ_STATUS);
    511  1.1  uwe 		DPRINTF(("%s: i24: %s\n", sc->sc_ad1848.sc_dev.dv_xname,
    512  1.1  uwe 		  bitmask_snprintf(reason, CS_I24_BITS, bits, sizeof(bits))));
    513  1.1  uwe #endif
    514  1.1  uwe 		/* clear interrupt from ad1848 */
    515  1.1  uwe 		ADWRITE(&sc->sc_ad1848, AD1848_STATUS, 0);
    516  1.1  uwe 	}
    517  1.1  uwe 
    518  1.1  uwe 	ret = 0;
    519  1.1  uwe 
    520  1.3  uwe 	if (cs4231_ebus_dma_intr(&sc->sc_capture,
    521  1.3  uwe 				 ebsc->sc_bt, ebsc->sc_cdmareg) != 0)
    522  1.3  uwe 	{
    523  1.2  uwe 		++sc->sc_intrcnt.ev_count;
    524  1.2  uwe 		ret = 1;
    525  1.1  uwe 	}
    526  1.1  uwe 
    527  1.3  uwe 	if (cs4231_ebus_dma_intr(&sc->sc_playback,
    528  1.3  uwe 				 ebsc->sc_bt, ebsc->sc_pdmareg) != 0)
    529  1.3  uwe 	{
    530  1.2  uwe 		++sc->sc_intrcnt.ev_count;
    531  1.2  uwe 		ret = 1;
    532  1.1  uwe 	}
    533  1.1  uwe 
    534  1.1  uwe 	return (ret);
    535  1.1  uwe }
    536