cs4231_ebus.c revision 1.5.2.3
1 1.5.2.3 nathanw /* $NetBSD: cs4231_ebus.c,v 1.5.2.3 2002/04/17 00:05:26 nathanw Exp $ */ 2 1.5.2.2 nathanw 3 1.5.2.2 nathanw /* 4 1.5.2.2 nathanw * Copyright (c) 2002 Valeriy E. Ushakov 5 1.5.2.2 nathanw * All rights reserved. 6 1.5.2.2 nathanw * 7 1.5.2.2 nathanw * Redistribution and use in source and binary forms, with or without 8 1.5.2.2 nathanw * modification, are permitted provided that the following conditions 9 1.5.2.2 nathanw * are met: 10 1.5.2.2 nathanw * 1. Redistributions of source code must retain the above copyright 11 1.5.2.2 nathanw * notice, this list of conditions and the following disclaimer. 12 1.5.2.2 nathanw * 2. Redistributions in binary form must reproduce the above copyright 13 1.5.2.2 nathanw * notice, this list of conditions and the following disclaimer in the 14 1.5.2.2 nathanw * documentation and/or other materials provided with the distribution. 15 1.5.2.2 nathanw * 3. The name of the author may not be used to endorse or promote products 16 1.5.2.2 nathanw * derived from this software without specific prior written permission 17 1.5.2.2 nathanw * 18 1.5.2.2 nathanw * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 1.5.2.2 nathanw * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 1.5.2.2 nathanw * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 1.5.2.2 nathanw * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 1.5.2.2 nathanw * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 1.5.2.2 nathanw * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 1.5.2.2 nathanw * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 1.5.2.2 nathanw * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 1.5.2.2 nathanw * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 1.5.2.2 nathanw * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 1.5.2.2 nathanw */ 29 1.5.2.2 nathanw 30 1.5.2.2 nathanw #include <sys/param.h> 31 1.5.2.2 nathanw #include <sys/systm.h> 32 1.5.2.2 nathanw #include <sys/errno.h> 33 1.5.2.2 nathanw #include <sys/device.h> 34 1.5.2.2 nathanw #include <sys/malloc.h> 35 1.5.2.2 nathanw 36 1.5.2.2 nathanw #include <machine/autoconf.h> 37 1.5.2.2 nathanw #include <machine/cpu.h> 38 1.5.2.2 nathanw #include <dev/ebus/ebusreg.h> 39 1.5.2.2 nathanw #include <dev/ebus/ebusvar.h> 40 1.5.2.2 nathanw 41 1.5.2.2 nathanw #include <sys/audioio.h> 42 1.5.2.2 nathanw #include <dev/audio_if.h> 43 1.5.2.2 nathanw 44 1.5.2.2 nathanw #include <dev/ic/ad1848reg.h> 45 1.5.2.2 nathanw #include <dev/ic/cs4231reg.h> 46 1.5.2.2 nathanw #include <dev/ic/ad1848var.h> 47 1.5.2.2 nathanw #include <dev/ic/cs4231var.h> 48 1.5.2.2 nathanw 49 1.5.2.2 nathanw #ifdef AUDIO_DEBUG 50 1.5.2.2 nathanw int cs4231_ebus_debug = 0; 51 1.5.2.2 nathanw #define DPRINTF(x) if (cs4231_ebus_debug) printf x 52 1.5.2.2 nathanw #else 53 1.5.2.2 nathanw #define DPRINTF(x) 54 1.5.2.2 nathanw #endif 55 1.5.2.2 nathanw 56 1.5.2.2 nathanw 57 1.5.2.2 nathanw struct cs4231_ebus_softc { 58 1.5.2.2 nathanw struct cs4231_softc sc_cs4231; 59 1.5.2.2 nathanw 60 1.5.2.2 nathanw bus_space_tag_t sc_bt; 61 1.5.2.2 nathanw bus_space_handle_t sc_pdmareg; /* playback DMA */ 62 1.5.2.2 nathanw bus_space_handle_t sc_cdmareg; /* record DMA */ 63 1.5.2.2 nathanw }; 64 1.5.2.2 nathanw 65 1.5.2.2 nathanw 66 1.5.2.2 nathanw void cs4231_ebus_attach(struct device *, struct device *, void *); 67 1.5.2.2 nathanw int cs4231_ebus_match(struct device *, struct cfdata *, void *); 68 1.5.2.2 nathanw 69 1.5.2.2 nathanw struct cfattach audiocs_ebus_ca = { 70 1.5.2.2 nathanw sizeof(struct cs4231_ebus_softc), cs4231_ebus_match, cs4231_ebus_attach 71 1.5.2.2 nathanw }; 72 1.5.2.2 nathanw 73 1.5.2.2 nathanw 74 1.5.2.2 nathanw /* audio_hw_if methods specific to ebus dma */ 75 1.5.2.2 nathanw static int cs4231_ebus_trigger_output(void *, void *, void *, int, 76 1.5.2.2 nathanw void (*)(void *), void *, 77 1.5.2.2 nathanw struct audio_params *); 78 1.5.2.2 nathanw static int cs4231_ebus_trigger_input(void *, void *, void *, int, 79 1.5.2.2 nathanw void (*)(void *), void *, 80 1.5.2.2 nathanw struct audio_params *); 81 1.5.2.2 nathanw static int cs4231_ebus_halt_output(void *); 82 1.5.2.2 nathanw static int cs4231_ebus_halt_input(void *); 83 1.5.2.2 nathanw 84 1.5.2.2 nathanw struct audio_hw_if audiocs_ebus_hw_if = { 85 1.5.2.2 nathanw cs4231_open, 86 1.5.2.2 nathanw cs4231_close, 87 1.5.2.2 nathanw NULL, /* drain */ 88 1.5.2.2 nathanw ad1848_query_encoding, 89 1.5.2.2 nathanw ad1848_set_params, 90 1.5.2.2 nathanw cs4231_round_blocksize, 91 1.5.2.2 nathanw ad1848_commit_settings, 92 1.5.2.2 nathanw NULL, /* init_output */ 93 1.5.2.2 nathanw NULL, /* init_input */ 94 1.5.2.2 nathanw NULL, /* start_output */ 95 1.5.2.2 nathanw NULL, /* start_input */ 96 1.5.2.2 nathanw cs4231_ebus_halt_output, 97 1.5.2.2 nathanw cs4231_ebus_halt_input, 98 1.5.2.2 nathanw NULL, /* speaker_ctl */ 99 1.5.2.2 nathanw cs4231_getdev, 100 1.5.2.2 nathanw NULL, /* setfd */ 101 1.5.2.2 nathanw cs4231_set_port, 102 1.5.2.2 nathanw cs4231_get_port, 103 1.5.2.2 nathanw cs4231_query_devinfo, 104 1.5.2.2 nathanw cs4231_malloc, 105 1.5.2.2 nathanw cs4231_free, 106 1.5.2.2 nathanw cs4231_round_buffersize, 107 1.5.2.2 nathanw NULL, /* mappage */ 108 1.5.2.2 nathanw cs4231_get_props, 109 1.5.2.2 nathanw cs4231_ebus_trigger_output, 110 1.5.2.2 nathanw cs4231_ebus_trigger_input, 111 1.5.2.2 nathanw NULL, /* dev_ioctl */ 112 1.5.2.2 nathanw }; 113 1.5.2.2 nathanw 114 1.5.2.2 nathanw #ifdef AUDIO_DEBUG 115 1.5.2.2 nathanw static void cs4231_ebus_regdump(char *, struct cs4231_ebus_softc *); 116 1.5.2.2 nathanw #endif 117 1.5.2.2 nathanw 118 1.5.2.2 nathanw static int cs4231_ebus_dma_reset(bus_space_tag_t, bus_space_handle_t); 119 1.5.2.2 nathanw static int cs4231_ebus_trigger_transfer(struct cs4231_softc *, 120 1.5.2.2 nathanw struct cs_transfer *, 121 1.5.2.2 nathanw bus_space_tag_t, bus_space_handle_t, 122 1.5.2.2 nathanw int, void *, void *, int, void (*)(void *), void *, 123 1.5.2.2 nathanw struct audio_params *); 124 1.5.2.2 nathanw static void cs4231_ebus_dma_advance(struct cs_transfer *, 125 1.5.2.2 nathanw bus_space_tag_t, bus_space_handle_t); 126 1.5.2.2 nathanw static int cs4231_ebus_dma_intr(struct cs_transfer *, 127 1.5.2.2 nathanw bus_space_tag_t, bus_space_handle_t); 128 1.5.2.2 nathanw static int cs4231_ebus_intr(void *); 129 1.5.2.2 nathanw 130 1.5.2.2 nathanw 131 1.5.2.2 nathanw int 132 1.5.2.2 nathanw cs4231_ebus_match(parent, cf, aux) 133 1.5.2.2 nathanw struct device *parent; 134 1.5.2.2 nathanw struct cfdata *cf; 135 1.5.2.2 nathanw void *aux; 136 1.5.2.2 nathanw { 137 1.5.2.2 nathanw struct ebus_attach_args *ea = aux; 138 1.5.2.2 nathanw 139 1.5.2.2 nathanw if (strcmp(ea->ea_name, AUDIOCS_PROM_NAME) == 0) 140 1.5.2.2 nathanw return (1); 141 1.5.2.2 nathanw #ifdef __sparc__ /* XXX: Krups */ 142 1.5.2.2 nathanw if (strcmp(ea->ea_name, "sound") == 0) 143 1.5.2.2 nathanw return (1); 144 1.5.2.2 nathanw #endif 145 1.5.2.2 nathanw 146 1.5.2.2 nathanw return (0); 147 1.5.2.2 nathanw } 148 1.5.2.2 nathanw 149 1.5.2.2 nathanw 150 1.5.2.2 nathanw void 151 1.5.2.2 nathanw cs4231_ebus_attach(parent, self, aux) 152 1.5.2.2 nathanw struct device *parent, *self; 153 1.5.2.2 nathanw void *aux; 154 1.5.2.2 nathanw { 155 1.5.2.2 nathanw struct cs4231_ebus_softc *ebsc = (struct cs4231_ebus_softc *)self; 156 1.5.2.2 nathanw struct cs4231_softc *sc = &ebsc->sc_cs4231; 157 1.5.2.2 nathanw struct ebus_attach_args *ea = aux; 158 1.5.2.2 nathanw bus_space_handle_t bh; 159 1.5.2.2 nathanw int i; 160 1.5.2.2 nathanw 161 1.5.2.2 nathanw sc->sc_bustag = ebsc->sc_bt = ea->ea_bustag; 162 1.5.2.2 nathanw sc->sc_dmatag = ea->ea_dmatag; 163 1.5.2.2 nathanw 164 1.5.2.2 nathanw /* 165 1.5.2.2 nathanw * These are the register we get from the prom: 166 1.5.2.2 nathanw * - CS4231 registers 167 1.5.2.2 nathanw * - Playback EBus DMA controller 168 1.5.2.2 nathanw * - Capture EBus DMA controller 169 1.5.2.2 nathanw * - AUXIO audio register (codec powerdown) 170 1.5.2.2 nathanw * 171 1.5.2.2 nathanw * Map my registers in, if they aren't already in virtual 172 1.5.2.2 nathanw * address space. 173 1.5.2.2 nathanw */ 174 1.5.2.2 nathanw if (bus_space_map(ea->ea_bustag, EBUS_ADDR_FROM_REG(&ea->ea_reg[0]), 175 1.5.2.2 nathanw ea->ea_reg[0].size, 0, &bh) != 0) { 176 1.5.2.3 nathanw printf(": unable to map registers\n"); 177 1.5.2.2 nathanw return; 178 1.5.2.2 nathanw } 179 1.5.2.2 nathanw 180 1.5.2.2 nathanw /* XXX: map playback DMA registers (we just know where they are) */ 181 1.5.2.2 nathanw if (bus_space_map(ea->ea_bustag, 182 1.5.2.2 nathanw BUS_ADDR(0x14, 0x702000), /* XXX: magic num */ 183 1.5.2.2 nathanw EBUS_DMAC_SIZE, 184 1.5.2.2 nathanw 0, &ebsc->sc_pdmareg) != 0) 185 1.5.2.2 nathanw { 186 1.5.2.3 nathanw printf(": unable to map playback DMA registers\n"); 187 1.5.2.2 nathanw return; 188 1.5.2.2 nathanw } 189 1.5.2.2 nathanw 190 1.5.2.2 nathanw /* XXX: map capture DMA registers (we just know where they are) */ 191 1.5.2.2 nathanw if (bus_space_map(ea->ea_bustag, 192 1.5.2.2 nathanw BUS_ADDR(0x14, 0x704000), /* XXX: magic num */ 193 1.5.2.2 nathanw EBUS_DMAC_SIZE, 194 1.5.2.2 nathanw 0, &ebsc->sc_cdmareg) != 0) 195 1.5.2.2 nathanw { 196 1.5.2.3 nathanw printf(": unable to map capture DMA registers\n"); 197 1.5.2.2 nathanw return; 198 1.5.2.2 nathanw } 199 1.5.2.2 nathanw 200 1.5.2.2 nathanw /* establish interrupt channels */ 201 1.5.2.2 nathanw for (i = 0; i < ea->ea_nintr; ++i) 202 1.5.2.2 nathanw bus_intr_establish(ea->ea_bustag, 203 1.5.2.2 nathanw ea->ea_intr[i], IPL_AUDIO, 0, 204 1.5.2.2 nathanw cs4231_ebus_intr, ebsc); 205 1.5.2.2 nathanw 206 1.5.2.2 nathanw cs4231_common_attach(sc, bh); 207 1.5.2.2 nathanw printf("\n"); 208 1.5.2.2 nathanw 209 1.5.2.2 nathanw /* XXX: todo: move to cs4231_common_attach, pass hw_if as arg? */ 210 1.5.2.2 nathanw audio_attach_mi(&audiocs_ebus_hw_if, sc, &sc->sc_ad1848.sc_dev); 211 1.5.2.2 nathanw } 212 1.5.2.2 nathanw 213 1.5.2.2 nathanw 214 1.5.2.2 nathanw #ifdef AUDIO_DEBUG 215 1.5.2.2 nathanw static void 216 1.5.2.2 nathanw cs4231_ebus_regdump(label, ebsc) 217 1.5.2.2 nathanw char *label; 218 1.5.2.2 nathanw struct cs4231_ebus_softc *ebsc; 219 1.5.2.2 nathanw { 220 1.5.2.2 nathanw /* char bits[128]; */ 221 1.5.2.2 nathanw 222 1.5.2.2 nathanw printf("cs4231regdump(%s): regs:", label); 223 1.5.2.2 nathanw /* XXX: dump ebus dma and aux registers */ 224 1.5.2.2 nathanw ad1848_dump_regs(&ebsc->sc_cs4231.sc_ad1848); 225 1.5.2.2 nathanw } 226 1.5.2.2 nathanw #endif /* AUDIO_DEBUG */ 227 1.5.2.2 nathanw 228 1.5.2.2 nathanw 229 1.5.2.2 nathanw /* XXX: nothing CS4231-specific in this code... */ 230 1.5.2.2 nathanw static int 231 1.5.2.2 nathanw cs4231_ebus_dma_reset(dt, dh) 232 1.5.2.2 nathanw bus_space_tag_t dt; 233 1.5.2.2 nathanw bus_space_handle_t dh; 234 1.5.2.2 nathanw { 235 1.5.2.2 nathanw u_int32_t csr; 236 1.5.2.2 nathanw int timo; 237 1.5.2.2 nathanw 238 1.5.2.2 nathanw /* reset, also clear TC, just in case */ 239 1.5.2.2 nathanw bus_space_write_4(dt, dh, EBUS_DMAC_DCSR, EBDMA_RESET | EBDMA_TC); 240 1.5.2.2 nathanw 241 1.5.2.2 nathanw for (timo = 50000; timo != 0; --timo) { 242 1.5.2.2 nathanw csr = bus_space_read_4(dt, dh, EBUS_DMAC_DCSR); 243 1.5.2.2 nathanw if ((csr & (EBDMA_CYC_PEND | EBDMA_DRAIN)) == 0) 244 1.5.2.2 nathanw break; 245 1.5.2.2 nathanw } 246 1.5.2.2 nathanw 247 1.5.2.2 nathanw if (timo == 0) { 248 1.5.2.2 nathanw char bits[128]; 249 1.5.2.2 nathanw 250 1.5.2.2 nathanw printf("cs4231_ebus_dma_reset: timed out: csr=%s\n", 251 1.5.2.2 nathanw bitmask_snprintf(csr, EBUS_DCSR_BITS, 252 1.5.2.2 nathanw bits, sizeof(bits))); 253 1.5.2.2 nathanw return (ETIMEDOUT); 254 1.5.2.2 nathanw } 255 1.5.2.2 nathanw 256 1.5.2.2 nathanw bus_space_write_4(dt, dh, EBUS_DMAC_DCSR, csr & ~EBDMA_RESET); 257 1.5.2.2 nathanw return (0); 258 1.5.2.2 nathanw } 259 1.5.2.2 nathanw 260 1.5.2.2 nathanw 261 1.5.2.2 nathanw static void 262 1.5.2.2 nathanw cs4231_ebus_dma_advance(t, dt, dh) 263 1.5.2.2 nathanw struct cs_transfer *t; 264 1.5.2.2 nathanw bus_space_tag_t dt; 265 1.5.2.2 nathanw bus_space_handle_t dh; 266 1.5.2.2 nathanw { 267 1.5.2.2 nathanw bus_addr_t dmaaddr; 268 1.5.2.2 nathanw bus_size_t dmasize; 269 1.5.2.2 nathanw 270 1.5.2.2 nathanw cs4231_transfer_advance(t, &dmaaddr, &dmasize); 271 1.5.2.2 nathanw 272 1.5.2.2 nathanw bus_space_write_4(dt, dh, EBUS_DMAC_DNBR, (u_int32_t)dmasize); 273 1.5.2.2 nathanw bus_space_write_4(dt, dh, EBUS_DMAC_DNAR, (u_int32_t)dmaaddr); 274 1.5.2.2 nathanw } 275 1.5.2.2 nathanw 276 1.5.2.2 nathanw 277 1.5.2.2 nathanw /* 278 1.5.2.2 nathanw * Trigger transfer "t" using DMA controller "dmac". 279 1.5.2.2 nathanw * "iswrite" defines direction of the transfer. 280 1.5.2.2 nathanw */ 281 1.5.2.2 nathanw static int 282 1.5.2.2 nathanw cs4231_ebus_trigger_transfer(sc, t, dt, dh, iswrite, 283 1.5.2.2 nathanw start, end, blksize, 284 1.5.2.2 nathanw intr, arg, param) 285 1.5.2.2 nathanw struct cs4231_softc *sc; 286 1.5.2.2 nathanw struct cs_transfer *t; 287 1.5.2.2 nathanw bus_space_tag_t dt; 288 1.5.2.2 nathanw bus_space_handle_t dh; 289 1.5.2.2 nathanw int iswrite; 290 1.5.2.2 nathanw void *start, *end; 291 1.5.2.2 nathanw int blksize; 292 1.5.2.2 nathanw void (*intr)(void *); 293 1.5.2.2 nathanw void *arg; 294 1.5.2.2 nathanw struct audio_params *param; 295 1.5.2.2 nathanw { 296 1.5.2.2 nathanw u_int32_t csr; 297 1.5.2.2 nathanw bus_addr_t dmaaddr; 298 1.5.2.2 nathanw bus_size_t dmasize; 299 1.5.2.2 nathanw int ret; 300 1.5.2.2 nathanw 301 1.5.2.2 nathanw ret = cs4231_transfer_init(sc, t, &dmaaddr, &dmasize, 302 1.5.2.2 nathanw start, end, blksize, intr, arg); 303 1.5.2.2 nathanw if (ret != 0) 304 1.5.2.2 nathanw return (ret); 305 1.5.2.2 nathanw 306 1.5.2.2 nathanw ret = cs4231_ebus_dma_reset(dt, dh); 307 1.5.2.2 nathanw if (ret != 0) 308 1.5.2.2 nathanw return (ret); 309 1.5.2.2 nathanw 310 1.5.2.2 nathanw csr = bus_space_read_4(dt, dh, EBUS_DMAC_DCSR); 311 1.5.2.2 nathanw bus_space_write_4(dt, dh, EBUS_DMAC_DCSR, 312 1.5.2.2 nathanw csr | EBDMA_EN_NEXT | (iswrite ? EBDMA_WRITE : 0) 313 1.5.2.2 nathanw | EBDMA_EN_DMA | EBDMA_EN_CNT | EBDMA_INT_EN); 314 1.5.2.2 nathanw 315 1.5.2.2 nathanw /* first load: propagated to DACR/DBCR */ 316 1.5.2.2 nathanw bus_space_write_4(dt, dh, EBUS_DMAC_DNBR, (u_int32_t)dmasize); 317 1.5.2.2 nathanw bus_space_write_4(dt, dh, EBUS_DMAC_DNAR, (u_int32_t)dmaaddr); 318 1.5.2.2 nathanw 319 1.5.2.2 nathanw /* next load: goes to DNAR/DNBR */ 320 1.5.2.2 nathanw cs4231_ebus_dma_advance(t, dt, dh); 321 1.5.2.2 nathanw 322 1.5.2.2 nathanw return (0); 323 1.5.2.2 nathanw } 324 1.5.2.2 nathanw 325 1.5.2.2 nathanw 326 1.5.2.2 nathanw static int 327 1.5.2.2 nathanw cs4231_ebus_trigger_output(addr, start, end, blksize, intr, arg, param) 328 1.5.2.2 nathanw void *addr; 329 1.5.2.2 nathanw void *start, *end; 330 1.5.2.2 nathanw int blksize; 331 1.5.2.2 nathanw void (*intr)(void *); 332 1.5.2.2 nathanw void *arg; 333 1.5.2.2 nathanw struct audio_params *param; 334 1.5.2.2 nathanw { 335 1.5.2.2 nathanw struct cs4231_ebus_softc *ebsc = addr; 336 1.5.2.2 nathanw struct cs4231_softc *sc = &ebsc->sc_cs4231; 337 1.5.2.2 nathanw int cfg, ret; 338 1.5.2.2 nathanw 339 1.5.2.2 nathanw ret = cs4231_ebus_trigger_transfer(sc, &sc->sc_playback, 340 1.5.2.2 nathanw ebsc->sc_bt, ebsc->sc_pdmareg, 341 1.5.2.2 nathanw 0, /* iswrite */ 342 1.5.2.2 nathanw start, end, blksize, 343 1.5.2.2 nathanw intr, arg, param); 344 1.5.2.2 nathanw if (ret != 0) 345 1.5.2.2 nathanw return (ret); 346 1.5.2.2 nathanw 347 1.5.2.2 nathanw ad_write(&sc->sc_ad1848, SP_LOWER_BASE_COUNT, 0xff); 348 1.5.2.2 nathanw ad_write(&sc->sc_ad1848, SP_UPPER_BASE_COUNT, 0xff); 349 1.5.2.2 nathanw 350 1.5.2.2 nathanw cfg = ad_read(&sc->sc_ad1848, SP_INTERFACE_CONFIG); 351 1.5.2.2 nathanw ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG, cfg | PLAYBACK_ENABLE); 352 1.5.2.2 nathanw 353 1.5.2.2 nathanw return (0); 354 1.5.2.2 nathanw } 355 1.5.2.2 nathanw 356 1.5.2.2 nathanw 357 1.5.2.2 nathanw static int 358 1.5.2.2 nathanw cs4231_ebus_trigger_input(addr, start, end, blksize, intr, arg, param) 359 1.5.2.2 nathanw void *addr; 360 1.5.2.2 nathanw void *start, *end; 361 1.5.2.2 nathanw int blksize; 362 1.5.2.2 nathanw void (*intr)(void *); 363 1.5.2.2 nathanw void *arg; 364 1.5.2.2 nathanw struct audio_params *param; 365 1.5.2.2 nathanw { 366 1.5.2.2 nathanw struct cs4231_ebus_softc *ebsc = addr; 367 1.5.2.2 nathanw struct cs4231_softc *sc = &ebsc->sc_cs4231; 368 1.5.2.2 nathanw int cfg, ret; 369 1.5.2.2 nathanw 370 1.5.2.2 nathanw ret = cs4231_ebus_trigger_transfer(sc, &sc->sc_capture, 371 1.5.2.2 nathanw ebsc->sc_bt, ebsc->sc_cdmareg, 372 1.5.2.2 nathanw 1, /* iswrite */ 373 1.5.2.2 nathanw start, end, blksize, 374 1.5.2.2 nathanw intr, arg, param); 375 1.5.2.2 nathanw if (ret != 0) 376 1.5.2.2 nathanw return (ret); 377 1.5.2.2 nathanw 378 1.5.2.2 nathanw ad_write(&sc->sc_ad1848, CS_LOWER_REC_CNT, 0xff); 379 1.5.2.2 nathanw ad_write(&sc->sc_ad1848, CS_UPPER_REC_CNT, 0xff); 380 1.5.2.2 nathanw 381 1.5.2.2 nathanw cfg = ad_read(&sc->sc_ad1848, SP_INTERFACE_CONFIG); 382 1.5.2.2 nathanw ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG, cfg | CAPTURE_ENABLE); 383 1.5.2.2 nathanw 384 1.5.2.2 nathanw return (0); 385 1.5.2.2 nathanw } 386 1.5.2.2 nathanw 387 1.5.2.2 nathanw 388 1.5.2.2 nathanw static int 389 1.5.2.2 nathanw cs4231_ebus_halt_output(addr) 390 1.5.2.2 nathanw void *addr; 391 1.5.2.2 nathanw { 392 1.5.2.2 nathanw struct cs4231_ebus_softc *ebsc = addr; 393 1.5.2.2 nathanw struct cs4231_softc *sc = &ebsc->sc_cs4231; 394 1.5.2.2 nathanw u_int32_t csr; 395 1.5.2.2 nathanw int cfg; 396 1.5.2.2 nathanw 397 1.5.2.2 nathanw sc->sc_playback.t_active = 0; 398 1.5.2.2 nathanw 399 1.5.2.2 nathanw csr = bus_space_read_4(ebsc->sc_bt, ebsc->sc_pdmareg, EBUS_DMAC_DCSR); 400 1.5.2.2 nathanw bus_space_write_4(ebsc->sc_bt, ebsc->sc_pdmareg, EBUS_DMAC_DCSR, 401 1.5.2.2 nathanw csr & ~EBDMA_EN_DMA); 402 1.5.2.2 nathanw 403 1.5.2.2 nathanw cfg = ad_read(&sc->sc_ad1848, SP_INTERFACE_CONFIG); 404 1.5.2.2 nathanw ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG, 405 1.5.2.2 nathanw cfg & ~PLAYBACK_ENABLE); 406 1.5.2.2 nathanw 407 1.5.2.2 nathanw return (0); 408 1.5.2.2 nathanw } 409 1.5.2.2 nathanw 410 1.5.2.2 nathanw 411 1.5.2.2 nathanw static int 412 1.5.2.2 nathanw cs4231_ebus_halt_input(addr) 413 1.5.2.2 nathanw void *addr; 414 1.5.2.2 nathanw { 415 1.5.2.2 nathanw struct cs4231_ebus_softc *ebsc = addr; 416 1.5.2.2 nathanw struct cs4231_softc *sc = &ebsc->sc_cs4231; 417 1.5.2.2 nathanw u_int32_t csr; 418 1.5.2.2 nathanw int cfg; 419 1.5.2.2 nathanw 420 1.5.2.2 nathanw sc->sc_capture.t_active = 0; 421 1.5.2.2 nathanw 422 1.5.2.2 nathanw csr = bus_space_read_4(ebsc->sc_bt, ebsc->sc_cdmareg, EBUS_DMAC_DCSR); 423 1.5.2.2 nathanw bus_space_write_4(ebsc->sc_bt, ebsc->sc_cdmareg, EBUS_DMAC_DCSR, 424 1.5.2.2 nathanw csr & ~EBDMA_EN_DMA); 425 1.5.2.2 nathanw 426 1.5.2.2 nathanw cfg = ad_read(&sc->sc_ad1848, SP_INTERFACE_CONFIG); 427 1.5.2.2 nathanw ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG, 428 1.5.2.2 nathanw cfg & ~CAPTURE_ENABLE); 429 1.5.2.2 nathanw 430 1.5.2.2 nathanw return (0); 431 1.5.2.2 nathanw } 432 1.5.2.2 nathanw 433 1.5.2.2 nathanw 434 1.5.2.2 nathanw static int 435 1.5.2.2 nathanw cs4231_ebus_dma_intr(t, dt, dh) 436 1.5.2.2 nathanw struct cs_transfer *t; 437 1.5.2.2 nathanw bus_space_tag_t dt; 438 1.5.2.2 nathanw bus_space_handle_t dh; 439 1.5.2.2 nathanw { 440 1.5.2.2 nathanw u_int32_t csr; 441 1.5.2.2 nathanw #ifdef AUDIO_DEBUG 442 1.5.2.2 nathanw char bits[128]; 443 1.5.2.2 nathanw #endif 444 1.5.2.2 nathanw 445 1.5.2.2 nathanw /* read DMA status, clear TC bit by writing it back */ 446 1.5.2.2 nathanw csr = bus_space_read_4(dt, dh, EBUS_DMAC_DCSR); 447 1.5.2.2 nathanw bus_space_write_4(dt, dh, EBUS_DMAC_DCSR, csr); 448 1.5.2.2 nathanw DPRINTF(("audiocs: %s dcsr=%s\n", t->t_name, 449 1.5.2.2 nathanw bitmask_snprintf(csr, EBUS_DCSR_BITS, bits, sizeof(bits)))); 450 1.5.2.2 nathanw 451 1.5.2.2 nathanw if (csr & EBDMA_ERR_PEND) { 452 1.5.2.2 nathanw ++t->t_ierrcnt.ev_count; 453 1.5.2.2 nathanw printf("audiocs: %s DMA error, resetting\n", t->t_name); 454 1.5.2.2 nathanw cs4231_ebus_dma_reset(dt, dh); 455 1.5.2.2 nathanw /* how to notify audio(9)??? */ 456 1.5.2.2 nathanw return (1); 457 1.5.2.2 nathanw } 458 1.5.2.2 nathanw 459 1.5.2.2 nathanw if ((csr & EBDMA_INT_PEND) == 0) 460 1.5.2.2 nathanw return (0); 461 1.5.2.2 nathanw 462 1.5.2.2 nathanw ++t->t_intrcnt.ev_count; 463 1.5.2.2 nathanw 464 1.5.2.2 nathanw if ((csr & EBDMA_TC) == 0) { /* can this happen? */ 465 1.5.2.2 nathanw printf("audiocs: %s INT_PEND but !TC\n", t->t_name); 466 1.5.2.2 nathanw return (1); 467 1.5.2.2 nathanw } 468 1.5.2.2 nathanw 469 1.5.2.2 nathanw if (!t->t_active) 470 1.5.2.2 nathanw return (1); 471 1.5.2.2 nathanw 472 1.5.2.2 nathanw cs4231_ebus_dma_advance(t, dt, dh); 473 1.5.2.2 nathanw 474 1.5.2.2 nathanw /* call audio(9) framework while dma is chugging along */ 475 1.5.2.2 nathanw if (t->t_intr != NULL) 476 1.5.2.2 nathanw (*t->t_intr)(t->t_arg); 477 1.5.2.2 nathanw return (1); 478 1.5.2.2 nathanw } 479 1.5.2.2 nathanw 480 1.5.2.2 nathanw 481 1.5.2.2 nathanw static int 482 1.5.2.2 nathanw cs4231_ebus_intr(arg) 483 1.5.2.2 nathanw void *arg; 484 1.5.2.2 nathanw { 485 1.5.2.2 nathanw struct cs4231_ebus_softc *ebsc = arg; 486 1.5.2.2 nathanw struct cs4231_softc *sc = &ebsc->sc_cs4231; 487 1.5.2.2 nathanw int status; 488 1.5.2.2 nathanw int ret; 489 1.5.2.2 nathanw #ifdef AUDIO_DEBUG 490 1.5.2.2 nathanw char bits[128]; 491 1.5.2.2 nathanw #endif 492 1.5.2.2 nathanw 493 1.5.2.2 nathanw status = ADREAD(&sc->sc_ad1848, AD1848_STATUS); 494 1.5.2.2 nathanw 495 1.5.2.2 nathanw #ifdef AUDIO_DEBUG 496 1.5.2.2 nathanw if (cs4231_ebus_debug > 1) 497 1.5.2.2 nathanw cs4231_ebus_regdump("audiointr", ebsc); 498 1.5.2.2 nathanw 499 1.5.2.2 nathanw DPRINTF(("%s: status: %s\n", sc->sc_ad1848.sc_dev.dv_xname, 500 1.5.2.2 nathanw bitmask_snprintf(status, AD_R2_BITS, bits, sizeof(bits)))); 501 1.5.2.2 nathanw #endif 502 1.5.2.2 nathanw 503 1.5.2.2 nathanw if (status & INTERRUPT_STATUS) { 504 1.5.2.2 nathanw #ifdef AUDIO_DEBUG 505 1.5.2.2 nathanw int reason; 506 1.5.2.2 nathanw 507 1.5.2.2 nathanw reason = ad_read(&sc->sc_ad1848, CS_IRQ_STATUS); 508 1.5.2.2 nathanw DPRINTF(("%s: i24: %s\n", sc->sc_ad1848.sc_dev.dv_xname, 509 1.5.2.2 nathanw bitmask_snprintf(reason, CS_I24_BITS, bits, sizeof(bits)))); 510 1.5.2.2 nathanw #endif 511 1.5.2.2 nathanw /* clear interrupt from ad1848 */ 512 1.5.2.2 nathanw ADWRITE(&sc->sc_ad1848, AD1848_STATUS, 0); 513 1.5.2.2 nathanw } 514 1.5.2.2 nathanw 515 1.5.2.2 nathanw ret = 0; 516 1.5.2.2 nathanw 517 1.5.2.2 nathanw if (cs4231_ebus_dma_intr(&sc->sc_capture, 518 1.5.2.2 nathanw ebsc->sc_bt, ebsc->sc_cdmareg) != 0) 519 1.5.2.2 nathanw { 520 1.5.2.2 nathanw ++sc->sc_intrcnt.ev_count; 521 1.5.2.2 nathanw ret = 1; 522 1.5.2.2 nathanw } 523 1.5.2.2 nathanw 524 1.5.2.2 nathanw if (cs4231_ebus_dma_intr(&sc->sc_playback, 525 1.5.2.2 nathanw ebsc->sc_bt, ebsc->sc_pdmareg) != 0) 526 1.5.2.2 nathanw { 527 1.5.2.2 nathanw ++sc->sc_intrcnt.ev_count; 528 1.5.2.2 nathanw ret = 1; 529 1.5.2.2 nathanw } 530 1.5.2.2 nathanw 531 1.5.2.2 nathanw return (ret); 532 1.5.2.2 nathanw } 533
Indexes created Thu Oct 09 06:09:57 GMT 2025