cs4231_ebus.c revision 1.22.6.1
1 /* $NetBSD: cs4231_ebus.c,v 1.22.6.1 2007/02/27 14:16:01 ad Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Valeriy E. Ushakov 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: cs4231_ebus.c,v 1.22.6.1 2007/02/27 14:16:01 ad Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/errno.h> 36 #include <sys/device.h> 37 #include <sys/malloc.h> 38 39 #include <machine/autoconf.h> 40 #include <machine/cpu.h> 41 #include <dev/ebus/ebusreg.h> 42 #include <dev/ebus/ebusvar.h> 43 44 #include <sys/audioio.h> 45 #include <dev/audio_if.h> 46 47 #include <dev/ic/ad1848reg.h> 48 #include <dev/ic/cs4231reg.h> 49 #include <dev/ic/ad1848var.h> 50 #include <dev/ic/cs4231var.h> 51 52 #ifdef AUDIO_DEBUG 53 int cs4231_ebus_debug = 0; 54 #define DPRINTF(x) if (cs4231_ebus_debug) printf x 55 #else 56 #define DPRINTF(x) 57 #endif 58 59 60 struct cs4231_ebus_softc { 61 struct cs4231_softc sc_cs4231; 62 63 bus_space_tag_t sc_bt; 64 bus_space_handle_t sc_pdmareg; /* playback DMA */ 65 bus_space_handle_t sc_cdmareg; /* record DMA */ 66 }; 67 68 69 void cs4231_ebus_attach(struct device *, struct device *, void *); 70 int cs4231_ebus_match(struct device *, struct cfdata *, void *); 71 72 CFATTACH_DECL(audiocs_ebus, sizeof(struct cs4231_ebus_softc), 73 cs4231_ebus_match, cs4231_ebus_attach, NULL, NULL); 74 75 /* audio_hw_if methods specific to ebus DMA */ 76 static int cs4231_ebus_round_blocksize(void *, int, int, 77 const audio_params_t *); 78 static int cs4231_ebus_trigger_output(void *, void *, void *, int, 79 void (*)(void *), void *, 80 const audio_params_t *); 81 static int cs4231_ebus_trigger_input(void *, void *, void *, int, 82 void (*)(void *), void *, 83 const audio_params_t *); 84 static int cs4231_ebus_halt_output(void *); 85 static int cs4231_ebus_halt_input(void *); 86 87 const struct audio_hw_if audiocs_ebus_hw_if = { 88 cs4231_open, 89 cs4231_close, 90 NULL, /* drain */ 91 ad1848_query_encoding, 92 ad1848_set_params, 93 cs4231_ebus_round_blocksize, 94 ad1848_commit_settings, 95 NULL, /* init_output */ 96 NULL, /* init_input */ 97 NULL, /* start_output */ 98 NULL, /* start_input */ 99 cs4231_ebus_halt_output, 100 cs4231_ebus_halt_input, 101 NULL, /* speaker_ctl */ 102 cs4231_getdev, 103 NULL, /* setfd */ 104 cs4231_set_port, 105 cs4231_get_port, 106 cs4231_query_devinfo, 107 cs4231_malloc, 108 cs4231_free, 109 NULL, /* round_buffersize */ 110 NULL, /* mappage */ 111 cs4231_get_props, 112 cs4231_ebus_trigger_output, 113 cs4231_ebus_trigger_input, 114 NULL, /* dev_ioctl */ 115 NULL, /* powerstate */ 116 cs4231_get_lock, 117 }; 118 119 #ifdef AUDIO_DEBUG 120 static void cs4231_ebus_regdump(char *, struct cs4231_ebus_softc *); 121 #endif 122 123 static int cs4231_ebus_dma_reset(bus_space_tag_t, bus_space_handle_t); 124 static int cs4231_ebus_trigger_transfer(struct cs4231_softc *, 125 struct cs_transfer *, 126 bus_space_tag_t, bus_space_handle_t, 127 int, void *, void *, int, void (*)(void *), void *, 128 const audio_params_t *); 129 static void cs4231_ebus_dma_advance(struct cs_transfer *, 130 bus_space_tag_t, bus_space_handle_t); 131 static int cs4231_ebus_dma_intr(struct cs_transfer *, 132 bus_space_tag_t, bus_space_handle_t); 133 static int cs4231_ebus_intr(void *); 134 135 136 int 137 cs4231_ebus_match(struct device *parent, struct cfdata *cf, void *aux) 138 { 139 struct ebus_attach_args *ea; 140 141 ea = aux; 142 if (strcmp(ea->ea_name, AUDIOCS_PROM_NAME) == 0) 143 return 1; 144 #ifdef __sparc__ /* XXX: Krups */ 145 if (strcmp(ea->ea_name, "sound") == 0) 146 return 1; 147 #endif 148 149 return 0; 150 } 151 152 153 void 154 cs4231_ebus_attach(struct device *parent, struct device *self, void *aux) 155 { 156 struct cs4231_ebus_softc *ebsc; 157 struct cs4231_softc *sc; 158 struct ebus_attach_args *ea; 159 bus_space_handle_t bh; 160 int i; 161 162 ebsc = device_private(self); 163 sc = &ebsc->sc_cs4231; 164 ea = aux; 165 sc->sc_bustag = ebsc->sc_bt = ea->ea_bustag; 166 sc->sc_dmatag = ea->ea_dmatag; 167 168 /* 169 * These are the register we get from the prom: 170 * - CS4231 registers 171 * - Playback EBus DMA controller 172 * - Capture EBus DMA controller 173 * - AUXIO audio register (codec powerdown) 174 * 175 * Map my registers in, if they aren't already in virtual 176 * address space. 177 */ 178 if (bus_space_map(ea->ea_bustag, EBUS_ADDR_FROM_REG(&ea->ea_reg[0]), 179 ea->ea_reg[0].size, 0, &bh) != 0) { 180 printf(": unable to map registers\n"); 181 return; 182 } 183 184 /* XXX: map playback DMA registers (we just know where they are) */ 185 if (bus_space_map(ea->ea_bustag, 186 BUS_ADDR(0x14, 0x702000), /* XXX: magic num */ 187 EBUS_DMAC_SIZE, 188 0, &ebsc->sc_pdmareg) != 0) 189 { 190 printf(": unable to map playback DMA registers\n"); 191 return; 192 } 193 194 /* XXX: map capture DMA registers (we just know where they are) */ 195 if (bus_space_map(ea->ea_bustag, 196 BUS_ADDR(0x14, 0x704000), /* XXX: magic num */ 197 EBUS_DMAC_SIZE, 198 0, &ebsc->sc_cdmareg) != 0) 199 { 200 printf(": unable to map capture DMA registers\n"); 201 return; 202 } 203 204 mutex_init(&sc->sc_lock, MUTEX_DRIVER, IPL_AUDIO); 205 206 /* establish interrupt channels */ 207 for (i = 0; i < ea->ea_nintr; ++i) 208 bus_intr_establish(ea->ea_bustag, 209 ea->ea_intr[i], IPL_AUDIO, 210 cs4231_ebus_intr, ebsc); 211 212 cs4231_common_attach(sc, bh); 213 printf("\n"); 214 215 /* XXX: todo: move to cs4231_common_attach, pass hw_if as arg? */ 216 audio_attach_mi(&audiocs_ebus_hw_if, sc, &sc->sc_ad1848.sc_dev); 217 } 218 219 220 static int 221 cs4231_ebus_round_blocksize(void *addr, int blk, int mode, 222 const audio_params_t *param) 223 { 224 225 /* we want to use DMA burst size of 16 words */ 226 return blk & -64; 227 } 228 229 230 #ifdef AUDIO_DEBUG 231 static void 232 cs4231_ebus_regdump(char *label, struct cs4231_ebus_softc *ebsc) 233 { 234 /* char bits[128]; */ 235 236 printf("cs4231regdump(%s): regs:", label); 237 /* XXX: dump ebus DMA and aux registers */ 238 ad1848_dump_regs(&ebsc->sc_cs4231.sc_ad1848); 239 } 240 #endif /* AUDIO_DEBUG */ 241 242 243 /* XXX: nothing CS4231-specific in this code... */ 244 static int 245 cs4231_ebus_dma_reset(bus_space_tag_t dt, bus_space_handle_t dh) 246 { 247 u_int32_t csr; 248 int timo; 249 250 /* reset, also clear TC, just in case */ 251 bus_space_write_4(dt, dh, EBUS_DMAC_DCSR, EBDMA_RESET | EBDMA_TC); 252 253 for (timo = 50000; timo != 0; --timo) { 254 csr = bus_space_read_4(dt, dh, EBUS_DMAC_DCSR); 255 if ((csr & (EBDMA_CYC_PEND | EBDMA_DRAIN)) == 0) 256 break; 257 } 258 259 if (timo == 0) { 260 char bits[128]; 261 262 printf("cs4231_ebus_dma_reset: timed out: csr=%s\n", 263 bitmask_snprintf(csr, EBUS_DCSR_BITS, 264 bits, sizeof(bits))); 265 return ETIMEDOUT; 266 } 267 268 bus_space_write_4(dt, dh, EBUS_DMAC_DCSR, csr & ~EBDMA_RESET); 269 return 0; 270 } 271 272 273 static void 274 cs4231_ebus_dma_advance(struct cs_transfer *t, bus_space_tag_t dt, 275 bus_space_handle_t dh) 276 { 277 bus_addr_t dmaaddr; 278 bus_size_t dmasize; 279 280 cs4231_transfer_advance(t, &dmaaddr, &dmasize); 281 282 bus_space_write_4(dt, dh, EBUS_DMAC_DNBR, (u_int32_t)dmasize); 283 bus_space_write_4(dt, dh, EBUS_DMAC_DNAR, (u_int32_t)dmaaddr); 284 } 285 286 287 /* 288 * Trigger transfer "t" using DMA controller at "dt"/"dh". 289 * "iswrite" defines direction of the transfer. 290 */ 291 static int 292 cs4231_ebus_trigger_transfer( 293 struct cs4231_softc *sc, 294 struct cs_transfer *t, 295 bus_space_tag_t dt, 296 bus_space_handle_t dh, 297 int iswrite, 298 void *start, void *end, 299 int blksize, 300 void (*intr)(void *), 301 void *arg, 302 const audio_params_t *param) 303 { 304 uint32_t csr; 305 bus_addr_t dmaaddr; 306 bus_size_t dmasize; 307 int ret; 308 309 ret = cs4231_transfer_init(sc, t, &dmaaddr, &dmasize, 310 start, end, blksize, intr, arg); 311 if (ret != 0) 312 return ret; 313 314 ret = cs4231_ebus_dma_reset(dt, dh); 315 if (ret != 0) 316 return ret; 317 318 csr = bus_space_read_4(dt, dh, EBUS_DMAC_DCSR); 319 bus_space_write_4(dt, dh, EBUS_DMAC_DCSR, 320 csr | EBDMA_EN_NEXT | (iswrite ? EBDMA_WRITE : 0) 321 | EBDMA_EN_DMA | EBDMA_EN_CNT | EBDMA_INT_EN 322 | EBDMA_BURST_SIZE_16); 323 324 /* first load: propagated to DACR/DBCR */ 325 bus_space_write_4(dt, dh, EBUS_DMAC_DNBR, (uint32_t)dmasize); 326 bus_space_write_4(dt, dh, EBUS_DMAC_DNAR, (uint32_t)dmaaddr); 327 328 /* next load: goes to DNAR/DNBR */ 329 cs4231_ebus_dma_advance(t, dt, dh); 330 331 return 0; 332 } 333 334 335 static int 336 cs4231_ebus_trigger_output(void *addr, void *start, void *end, int blksize, 337 void (*intr)(void *), void *arg, 338 const audio_params_t *param) 339 { 340 struct cs4231_ebus_softc *ebsc; 341 struct cs4231_softc *sc; 342 int cfg, ret; 343 344 ebsc = addr; 345 sc = &ebsc->sc_cs4231; 346 ret = cs4231_ebus_trigger_transfer(sc, &sc->sc_playback, 347 ebsc->sc_bt, ebsc->sc_pdmareg, 348 0, /* iswrite */ 349 start, end, blksize, 350 intr, arg, param); 351 if (ret != 0) 352 return ret; 353 354 ad_write(&sc->sc_ad1848, SP_LOWER_BASE_COUNT, 0xff); 355 ad_write(&sc->sc_ad1848, SP_UPPER_BASE_COUNT, 0xff); 356 357 cfg = ad_read(&sc->sc_ad1848, SP_INTERFACE_CONFIG); 358 ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG, cfg | PLAYBACK_ENABLE); 359 360 return 0; 361 } 362 363 364 static int 365 cs4231_ebus_trigger_input(void *addr, void *start, void *end, int blksize, 366 void (*intr)(void *), void *arg, 367 const audio_params_t *param) 368 { 369 struct cs4231_ebus_softc *ebsc; 370 struct cs4231_softc *sc; 371 int cfg, ret; 372 373 ebsc = addr; 374 sc = &ebsc->sc_cs4231; 375 ret = cs4231_ebus_trigger_transfer(sc, &sc->sc_capture, 376 ebsc->sc_bt, ebsc->sc_cdmareg, 377 1, /* iswrite */ 378 start, end, blksize, 379 intr, arg, param); 380 if (ret != 0) 381 return ret; 382 383 ad_write(&sc->sc_ad1848, CS_LOWER_REC_CNT, 0xff); 384 ad_write(&sc->sc_ad1848, CS_UPPER_REC_CNT, 0xff); 385 386 cfg = ad_read(&sc->sc_ad1848, SP_INTERFACE_CONFIG); 387 ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG, cfg | CAPTURE_ENABLE); 388 389 return 0; 390 } 391 392 393 static int 394 cs4231_ebus_halt_output(void *addr) 395 { 396 struct cs4231_ebus_softc *ebsc; 397 struct cs4231_softc *sc; 398 u_int32_t csr; 399 int cfg; 400 401 ebsc = addr; 402 sc = &ebsc->sc_cs4231; 403 sc->sc_playback.t_active = 0; 404 405 csr = bus_space_read_4(ebsc->sc_bt, ebsc->sc_pdmareg, EBUS_DMAC_DCSR); 406 bus_space_write_4(ebsc->sc_bt, ebsc->sc_pdmareg, EBUS_DMAC_DCSR, 407 csr & ~EBDMA_EN_DMA); 408 409 cfg = ad_read(&sc->sc_ad1848, SP_INTERFACE_CONFIG); 410 ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG, 411 cfg & ~PLAYBACK_ENABLE); 412 413 return 0; 414 } 415 416 417 static int 418 cs4231_ebus_halt_input(void *addr) 419 { 420 struct cs4231_ebus_softc *ebsc; 421 struct cs4231_softc *sc; 422 uint32_t csr; 423 int cfg; 424 425 ebsc = addr; 426 sc = &ebsc->sc_cs4231; 427 sc->sc_capture.t_active = 0; 428 429 csr = bus_space_read_4(ebsc->sc_bt, ebsc->sc_cdmareg, EBUS_DMAC_DCSR); 430 bus_space_write_4(ebsc->sc_bt, ebsc->sc_cdmareg, EBUS_DMAC_DCSR, 431 csr & ~EBDMA_EN_DMA); 432 433 cfg = ad_read(&sc->sc_ad1848, SP_INTERFACE_CONFIG); 434 ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG, 435 cfg & ~CAPTURE_ENABLE); 436 437 return 0; 438 } 439 440 441 static int 442 cs4231_ebus_dma_intr(struct cs_transfer *t, bus_space_tag_t dt, 443 bus_space_handle_t dh) 444 { 445 uint32_t csr; 446 #ifdef AUDIO_DEBUG 447 char bits[128]; 448 #endif 449 450 /* read DMA status, clear TC bit by writing it back */ 451 csr = bus_space_read_4(dt, dh, EBUS_DMAC_DCSR); 452 bus_space_write_4(dt, dh, EBUS_DMAC_DCSR, csr); 453 DPRINTF(("audiocs: %s dcsr=%s\n", t->t_name, 454 bitmask_snprintf(csr, EBUS_DCSR_BITS, bits, sizeof(bits)))); 455 456 if (csr & EBDMA_ERR_PEND) { 457 ++t->t_ierrcnt.ev_count; 458 printf("audiocs: %s DMA error, resetting\n", t->t_name); 459 cs4231_ebus_dma_reset(dt, dh); 460 /* how to notify audio(9)??? */ 461 return 1; 462 } 463 464 if ((csr & EBDMA_INT_PEND) == 0) 465 return 0; 466 467 ++t->t_intrcnt.ev_count; 468 469 if ((csr & EBDMA_TC) == 0) { /* can this happen? */ 470 printf("audiocs: %s INT_PEND but !TC\n", t->t_name); 471 return 1; 472 } 473 474 if (!t->t_active) 475 return 1; 476 477 cs4231_ebus_dma_advance(t, dt, dh); 478 479 /* call audio(9) framework while DMA is chugging along */ 480 if (t->t_intr != NULL) 481 (*t->t_intr)(t->t_arg); 482 return 1; 483 } 484 485 486 static int 487 cs4231_ebus_intr(void *arg) 488 { 489 struct cs4231_ebus_softc *ebsc; 490 struct cs4231_softc *sc; 491 int status; 492 int ret; 493 #ifdef AUDIO_DEBUG 494 char bits[128]; 495 #endif 496 497 ebsc = arg; 498 sc = &ebsc->sc_cs4231; 499 500 mutex_enter(&sc->sc_lock); 501 502 status = ADREAD(&sc->sc_ad1848, AD1848_STATUS); 503 504 #ifdef AUDIO_DEBUG 505 if (cs4231_ebus_debug > 1) 506 cs4231_ebus_regdump("audiointr", ebsc); 507 508 DPRINTF(("%s: status: %s\n", sc->sc_ad1848.sc_dev.dv_xname, 509 bitmask_snprintf(status, AD_R2_BITS, bits, sizeof(bits)))); 510 #endif 511 512 if (status & INTERRUPT_STATUS) { 513 #ifdef AUDIO_DEBUG 514 int reason; 515 516 reason = ad_read(&sc->sc_ad1848, CS_IRQ_STATUS); 517 DPRINTF(("%s: i24: %s\n", sc->sc_ad1848.sc_dev.dv_xname, 518 bitmask_snprintf(reason, CS_I24_BITS, bits, sizeof(bits)))); 519 #endif 520 /* clear interrupt from ad1848 */ 521 ADWRITE(&sc->sc_ad1848, AD1848_STATUS, 0); 522 } 523 524 ret = 0; 525 526 if (cs4231_ebus_dma_intr(&sc->sc_capture, 527 ebsc->sc_bt, ebsc->sc_cdmareg) != 0) 528 { 529 ++sc->sc_intrcnt.ev_count; 530 ret = 1; 531 } 532 533 if (cs4231_ebus_dma_intr(&sc->sc_playback, 534 ebsc->sc_bt, ebsc->sc_pdmareg) != 0) 535 { 536 ++sc->sc_intrcnt.ev_count; 537 ret = 1; 538 } 539 540 mutex_exit(&sc->sc_lock); 541 542 return ret; 543 } 544
Indexes created Tue Oct 07 21:09:53 GMT 2025