cs4231_ebus.c revision 1.5
1 /* $NetBSD: cs4231_ebus.c,v 1.5 2002/03/22 11:52:07 martin Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Valeriy E. Ushakov 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/errno.h> 33 #include <sys/device.h> 34 #include <sys/malloc.h> 35 36 #include <machine/autoconf.h> 37 #include <machine/cpu.h> 38 #include <dev/ebus/ebusreg.h> 39 #include <dev/ebus/ebusvar.h> 40 41 #include <sys/audioio.h> 42 #include <dev/audio_if.h> 43 44 #include <dev/ic/ad1848reg.h> 45 #include <dev/ic/cs4231reg.h> 46 #include <dev/ic/ad1848var.h> 47 #include <dev/ic/cs4231var.h> 48 49 #ifdef AUDIO_DEBUG 50 int cs4231_ebus_debug = 0; 51 #define DPRINTF(x) if (cs4231_ebus_debug) printf x 52 #else 53 #define DPRINTF(x) 54 #endif 55 56 57 struct cs4231_ebus_softc { 58 struct cs4231_softc sc_cs4231; 59 60 bus_space_tag_t sc_bt; 61 bus_space_handle_t sc_pdmareg; /* playback DMA */ 62 bus_space_handle_t sc_cdmareg; /* record DMA */ 63 }; 64 65 66 void cs4231_ebus_attach(struct device *, struct device *, void *); 67 int cs4231_ebus_match(struct device *, struct cfdata *, void *); 68 69 struct cfattach audiocs_ebus_ca = { 70 sizeof(struct cs4231_ebus_softc), cs4231_ebus_match, cs4231_ebus_attach 71 }; 72 73 74 /* audio_hw_if methods specific to ebus dma */ 75 static int cs4231_ebus_trigger_output(void *, void *, void *, int, 76 void (*)(void *), void *, 77 struct audio_params *); 78 static int cs4231_ebus_trigger_input(void *, void *, void *, int, 79 void (*)(void *), void *, 80 struct audio_params *); 81 static int cs4231_ebus_halt_output(void *); 82 static int cs4231_ebus_halt_input(void *); 83 84 struct audio_hw_if audiocs_ebus_hw_if = { 85 cs4231_open, 86 cs4231_close, 87 NULL, /* drain */ 88 ad1848_query_encoding, 89 ad1848_set_params, 90 cs4231_round_blocksize, 91 ad1848_commit_settings, 92 NULL, /* init_output */ 93 NULL, /* init_input */ 94 NULL, /* start_output */ 95 NULL, /* start_input */ 96 cs4231_ebus_halt_output, 97 cs4231_ebus_halt_input, 98 NULL, /* speaker_ctl */ 99 cs4231_getdev, 100 NULL, /* setfd */ 101 cs4231_set_port, 102 cs4231_get_port, 103 cs4231_query_devinfo, 104 cs4231_malloc, 105 cs4231_free, 106 cs4231_round_buffersize, 107 NULL, /* mappage */ 108 cs4231_get_props, 109 cs4231_ebus_trigger_output, 110 cs4231_ebus_trigger_input, 111 NULL, /* dev_ioctl */ 112 }; 113 114 #ifdef AUDIO_DEBUG 115 static void cs4231_ebus_regdump(char *, struct cs4231_ebus_softc *); 116 #endif 117 118 static int cs4231_ebus_dma_reset(bus_space_tag_t, bus_space_handle_t); 119 static int cs4231_ebus_trigger_transfer(struct cs4231_softc *, 120 struct cs_transfer *, 121 bus_space_tag_t, bus_space_handle_t, 122 int, void *, void *, int, void (*)(void *), void *, 123 struct audio_params *); 124 static void cs4231_ebus_dma_advance(struct cs_transfer *, 125 bus_space_tag_t, bus_space_handle_t); 126 static int cs4231_ebus_dma_intr(struct cs_transfer *, 127 bus_space_tag_t, bus_space_handle_t); 128 static int cs4231_ebus_intr(void *); 129 130 131 int 132 cs4231_ebus_match(parent, cf, aux) 133 struct device *parent; 134 struct cfdata *cf; 135 void *aux; 136 { 137 struct ebus_attach_args *ea = aux; 138 139 if (strcmp(ea->ea_name, AUDIOCS_PROM_NAME) == 0) 140 return (1); 141 #ifdef __sparc__ /* XXX: Krups */ 142 if (strcmp(ea->ea_name, "sound") == 0) 143 return (1); 144 #endif 145 146 return (0); 147 } 148 149 150 void 151 cs4231_ebus_attach(parent, self, aux) 152 struct device *parent, *self; 153 void *aux; 154 { 155 struct cs4231_ebus_softc *ebsc = (struct cs4231_ebus_softc *)self; 156 struct cs4231_softc *sc = &ebsc->sc_cs4231; 157 struct ebus_attach_args *ea = aux; 158 bus_space_handle_t bh; 159 int i; 160 161 sc->sc_bustag = ebsc->sc_bt = ea->ea_bustag; 162 sc->sc_dmatag = ea->ea_dmatag; 163 164 /* 165 * These are the register we get from the prom: 166 * - CS4231 registers 167 * - Playback EBus DMA controller 168 * - Capture EBus DMA controller 169 * - AUXIO audio register (codec powerdown) 170 * 171 * Map my registers in, if they aren't already in virtual 172 * address space. 173 */ 174 if (bus_space_map(ea->ea_bustag, EBUS_ADDR_FROM_REG(&ea->ea_reg[0]), 175 ea->ea_reg[0].size, 0, &bh) != 0) { 176 printf("%s: unable to map registers\n", 177 self->dv_xname); 178 return; 179 } 180 181 /* XXX: map playback DMA registers (we just know where they are) */ 182 if (bus_space_map(ea->ea_bustag, 183 BUS_ADDR(0x14, 0x702000), /* XXX: magic num */ 184 EBUS_DMAC_SIZE, 185 0, &ebsc->sc_pdmareg) != 0) 186 { 187 printf("%s: unable to map playback DMA registers\n", 188 self->dv_xname); 189 return; 190 } 191 192 /* XXX: map capture DMA registers (we just know where they are) */ 193 if (bus_space_map(ea->ea_bustag, 194 BUS_ADDR(0x14, 0x704000), /* XXX: magic num */ 195 EBUS_DMAC_SIZE, 196 0, &ebsc->sc_cdmareg) != 0) 197 { 198 printf("%s: unable to map capture DMA registers\n", 199 self->dv_xname); 200 return; 201 } 202 203 /* establish interrupt channels */ 204 for (i = 0; i < ea->ea_nintr; ++i) 205 bus_intr_establish(ea->ea_bustag, 206 ea->ea_intr[i], IPL_AUDIO, 0, 207 cs4231_ebus_intr, ebsc); 208 209 cs4231_common_attach(sc, bh); 210 printf("\n"); 211 212 /* XXX: todo: move to cs4231_common_attach, pass hw_if as arg? */ 213 audio_attach_mi(&audiocs_ebus_hw_if, sc, &sc->sc_ad1848.sc_dev); 214 } 215 216 217 #ifdef AUDIO_DEBUG 218 static void 219 cs4231_ebus_regdump(label, ebsc) 220 char *label; 221 struct cs4231_ebus_softc *ebsc; 222 { 223 /* char bits[128]; */ 224 225 printf("cs4231regdump(%s): regs:", label); 226 /* XXX: dump ebus dma and aux registers */ 227 ad1848_dump_regs(&ebsc->sc_cs4231.sc_ad1848); 228 } 229 #endif /* AUDIO_DEBUG */ 230 231 232 /* XXX: nothing CS4231-specific in this code... */ 233 static int 234 cs4231_ebus_dma_reset(dt, dh) 235 bus_space_tag_t dt; 236 bus_space_handle_t dh; 237 { 238 u_int32_t csr; 239 int timo; 240 241 /* reset, also clear TC, just in case */ 242 bus_space_write_4(dt, dh, EBUS_DMAC_DCSR, EBDMA_RESET | EBDMA_TC); 243 244 for (timo = 50000; timo != 0; --timo) { 245 csr = bus_space_read_4(dt, dh, EBUS_DMAC_DCSR); 246 if ((csr & (EBDMA_CYC_PEND | EBDMA_DRAIN)) == 0) 247 break; 248 } 249 250 if (timo == 0) { 251 char bits[128]; 252 253 printf("cs4231_ebus_dma_reset: timed out: csr=%s\n", 254 bitmask_snprintf(csr, EBUS_DCSR_BITS, 255 bits, sizeof(bits))); 256 return (ETIMEDOUT); 257 } 258 259 bus_space_write_4(dt, dh, EBUS_DMAC_DCSR, csr & ~EBDMA_RESET); 260 return (0); 261 } 262 263 264 static void 265 cs4231_ebus_dma_advance(t, dt, dh) 266 struct cs_transfer *t; 267 bus_space_tag_t dt; 268 bus_space_handle_t dh; 269 { 270 bus_addr_t dmaaddr; 271 bus_size_t dmasize; 272 273 cs4231_transfer_advance(t, &dmaaddr, &dmasize); 274 275 bus_space_write_4(dt, dh, EBUS_DMAC_DNBR, (u_int32_t)dmasize); 276 bus_space_write_4(dt, dh, EBUS_DMAC_DNAR, (u_int32_t)dmaaddr); 277 } 278 279 280 /* 281 * Trigger transfer "t" using DMA controller "dmac". 282 * "iswrite" defines direction of the transfer. 283 */ 284 static int 285 cs4231_ebus_trigger_transfer(sc, t, dt, dh, iswrite, 286 start, end, blksize, 287 intr, arg, param) 288 struct cs4231_softc *sc; 289 struct cs_transfer *t; 290 bus_space_tag_t dt; 291 bus_space_handle_t dh; 292 int iswrite; 293 void *start, *end; 294 int blksize; 295 void (*intr)(void *); 296 void *arg; 297 struct audio_params *param; 298 { 299 u_int32_t csr; 300 bus_addr_t dmaaddr; 301 bus_size_t dmasize; 302 int ret; 303 304 ret = cs4231_transfer_init(sc, t, &dmaaddr, &dmasize, 305 start, end, blksize, intr, arg); 306 if (ret != 0) 307 return (ret); 308 309 ret = cs4231_ebus_dma_reset(dt, dh); 310 if (ret != 0) 311 return (ret); 312 313 csr = bus_space_read_4(dt, dh, EBUS_DMAC_DCSR); 314 bus_space_write_4(dt, dh, EBUS_DMAC_DCSR, 315 csr | EBDMA_EN_NEXT | (iswrite ? EBDMA_WRITE : 0) 316 | EBDMA_EN_DMA | EBDMA_EN_CNT | EBDMA_INT_EN); 317 318 /* first load: propagated to DACR/DBCR */ 319 bus_space_write_4(dt, dh, EBUS_DMAC_DNBR, (u_int32_t)dmasize); 320 bus_space_write_4(dt, dh, EBUS_DMAC_DNAR, (u_int32_t)dmaaddr); 321 322 /* next load: goes to DNAR/DNBR */ 323 cs4231_ebus_dma_advance(t, dt, dh); 324 325 return (0); 326 } 327 328 329 static int 330 cs4231_ebus_trigger_output(addr, start, end, blksize, intr, arg, param) 331 void *addr; 332 void *start, *end; 333 int blksize; 334 void (*intr)(void *); 335 void *arg; 336 struct audio_params *param; 337 { 338 struct cs4231_ebus_softc *ebsc = addr; 339 struct cs4231_softc *sc = &ebsc->sc_cs4231; 340 int cfg, ret; 341 342 ret = cs4231_ebus_trigger_transfer(sc, &sc->sc_playback, 343 ebsc->sc_bt, ebsc->sc_pdmareg, 344 0, /* iswrite */ 345 start, end, blksize, 346 intr, arg, param); 347 if (ret != 0) 348 return (ret); 349 350 ad_write(&sc->sc_ad1848, SP_LOWER_BASE_COUNT, 0xff); 351 ad_write(&sc->sc_ad1848, SP_UPPER_BASE_COUNT, 0xff); 352 353 cfg = ad_read(&sc->sc_ad1848, SP_INTERFACE_CONFIG); 354 ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG, cfg | PLAYBACK_ENABLE); 355 356 return (0); 357 } 358 359 360 static int 361 cs4231_ebus_trigger_input(addr, start, end, blksize, intr, arg, param) 362 void *addr; 363 void *start, *end; 364 int blksize; 365 void (*intr)(void *); 366 void *arg; 367 struct audio_params *param; 368 { 369 struct cs4231_ebus_softc *ebsc = addr; 370 struct cs4231_softc *sc = &ebsc->sc_cs4231; 371 int cfg, ret; 372 373 ret = cs4231_ebus_trigger_transfer(sc, &sc->sc_capture, 374 ebsc->sc_bt, ebsc->sc_cdmareg, 375 1, /* iswrite */ 376 start, end, blksize, 377 intr, arg, param); 378 if (ret != 0) 379 return (ret); 380 381 ad_write(&sc->sc_ad1848, CS_LOWER_REC_CNT, 0xff); 382 ad_write(&sc->sc_ad1848, CS_UPPER_REC_CNT, 0xff); 383 384 cfg = ad_read(&sc->sc_ad1848, SP_INTERFACE_CONFIG); 385 ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG, cfg | CAPTURE_ENABLE); 386 387 return (0); 388 } 389 390 391 static int 392 cs4231_ebus_halt_output(addr) 393 void *addr; 394 { 395 struct cs4231_ebus_softc *ebsc = addr; 396 struct cs4231_softc *sc = &ebsc->sc_cs4231; 397 u_int32_t csr; 398 int cfg; 399 400 sc->sc_playback.t_active = 0; 401 402 csr = bus_space_read_4(ebsc->sc_bt, ebsc->sc_pdmareg, EBUS_DMAC_DCSR); 403 bus_space_write_4(ebsc->sc_bt, ebsc->sc_pdmareg, EBUS_DMAC_DCSR, 404 csr & ~EBDMA_EN_DMA); 405 406 cfg = ad_read(&sc->sc_ad1848, SP_INTERFACE_CONFIG); 407 ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG, 408 cfg & ~PLAYBACK_ENABLE); 409 410 return (0); 411 } 412 413 414 static int 415 cs4231_ebus_halt_input(addr) 416 void *addr; 417 { 418 struct cs4231_ebus_softc *ebsc = addr; 419 struct cs4231_softc *sc = &ebsc->sc_cs4231; 420 u_int32_t csr; 421 int cfg; 422 423 sc->sc_capture.t_active = 0; 424 425 csr = bus_space_read_4(ebsc->sc_bt, ebsc->sc_cdmareg, EBUS_DMAC_DCSR); 426 bus_space_write_4(ebsc->sc_bt, ebsc->sc_cdmareg, EBUS_DMAC_DCSR, 427 csr & ~EBDMA_EN_DMA); 428 429 cfg = ad_read(&sc->sc_ad1848, SP_INTERFACE_CONFIG); 430 ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG, 431 cfg & ~CAPTURE_ENABLE); 432 433 return (0); 434 } 435 436 437 static int 438 cs4231_ebus_dma_intr(t, dt, dh) 439 struct cs_transfer *t; 440 bus_space_tag_t dt; 441 bus_space_handle_t dh; 442 { 443 u_int32_t csr; 444 #ifdef AUDIO_DEBUG 445 char bits[128]; 446 #endif 447 448 /* read DMA status, clear TC bit by writing it back */ 449 csr = bus_space_read_4(dt, dh, EBUS_DMAC_DCSR); 450 bus_space_write_4(dt, dh, EBUS_DMAC_DCSR, csr); 451 DPRINTF(("audiocs: %s dcsr=%s\n", t->t_name, 452 bitmask_snprintf(csr, EBUS_DCSR_BITS, bits, sizeof(bits)))); 453 454 if (csr & EBDMA_ERR_PEND) { 455 ++t->t_ierrcnt.ev_count; 456 printf("audiocs: %s DMA error, resetting\n", t->t_name); 457 cs4231_ebus_dma_reset(dt, dh); 458 /* how to notify audio(9)??? */ 459 return (1); 460 } 461 462 if ((csr & EBDMA_INT_PEND) == 0) 463 return (0); 464 465 ++t->t_intrcnt.ev_count; 466 467 if ((csr & EBDMA_TC) == 0) { /* can this happen? */ 468 printf("audiocs: %s INT_PEND but !TC\n", t->t_name); 469 return (1); 470 } 471 472 if (!t->t_active) 473 return (1); 474 475 cs4231_ebus_dma_advance(t, dt, dh); 476 477 /* call audio(9) framework while dma is chugging along */ 478 if (t->t_intr != NULL) 479 (*t->t_intr)(t->t_arg); 480 return (1); 481 } 482 483 484 static int 485 cs4231_ebus_intr(arg) 486 void *arg; 487 { 488 struct cs4231_ebus_softc *ebsc = arg; 489 struct cs4231_softc *sc = &ebsc->sc_cs4231; 490 int status; 491 int ret; 492 #ifdef AUDIO_DEBUG 493 char bits[128]; 494 #endif 495 496 status = ADREAD(&sc->sc_ad1848, AD1848_STATUS); 497 498 #ifdef AUDIO_DEBUG 499 if (cs4231_ebus_debug > 1) 500 cs4231_ebus_regdump("audiointr", ebsc); 501 502 DPRINTF(("%s: status: %s\n", sc->sc_ad1848.sc_dev.dv_xname, 503 bitmask_snprintf(status, AD_R2_BITS, bits, sizeof(bits)))); 504 #endif 505 506 if (status & INTERRUPT_STATUS) { 507 #ifdef AUDIO_DEBUG 508 int reason; 509 510 reason = ad_read(&sc->sc_ad1848, CS_IRQ_STATUS); 511 DPRINTF(("%s: i24: %s\n", sc->sc_ad1848.sc_dev.dv_xname, 512 bitmask_snprintf(reason, CS_I24_BITS, bits, sizeof(bits)))); 513 #endif 514 /* clear interrupt from ad1848 */ 515 ADWRITE(&sc->sc_ad1848, AD1848_STATUS, 0); 516 } 517 518 ret = 0; 519 520 if (cs4231_ebus_dma_intr(&sc->sc_capture, 521 ebsc->sc_bt, ebsc->sc_cdmareg) != 0) 522 { 523 ++sc->sc_intrcnt.ev_count; 524 ret = 1; 525 } 526 527 if (cs4231_ebus_dma_intr(&sc->sc_playback, 528 ebsc->sc_bt, ebsc->sc_pdmareg) != 0) 529 { 530 ++sc->sc_intrcnt.ev_count; 531 ret = 1; 532 } 533 534 return (ret); 535 } 536
Indexes created Mon Sep 22 21:09:42 GMT 2025