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ebusreg.h revision 1.1.2.2 
      1 /*	$NetBSD: ebusreg.h,v 1.1.2.2 2001/10/01 12:45:19 fvdl Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 1999 Matthew R. Green
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  * 3. The name of the author may not be used to endorse or promote products
     16  *    derived from this software without specific prior written permission.
     17  *
     18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     19  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     20  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     21  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     22  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     23  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     24  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     25  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     26  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     28  * SUCH DAMAGE.
     29  */
     30 
     31 #ifndef _SPARC64_DEV_EBUSREG_H_
     32 #define _SPARC64_DEV_EBUSREG_H_
     33 
     34 /*
     35  * SPARC `ebus'
     36  *
     37  * The `ebus' bus is designed to plug traditional PC-ISA devices into
     38  * an SPARC system with as few costs as possible, without sacrificing
     39  * to performance.  Typically, it is implemented in the PCIO IC from
     40  * SME, which also implements a `hme-compatible' PCI network device
     41  * (`network').  The ebus has 4 DMA channels, similar to the DMA seen
     42  * in the ESP SCSI DMA.
     43  *
     44  * Typical UltraSPARC systems have a NatSemi SuperIO IC to provide
     45  * serial ports for the keyboard and mouse (`se'), floppy disk
     46  * controller (`fdthree'), parallel port controller (`bpp') connected
     47  * to the ebus, and a PCI-IDE controller (connected directly to the
     48  * PCI bus, of course), as well as a Siemens Nixdorf SAB82532 dual
     49  * channel serial controller (`su' providing ttya and ttyb), an MK48T59
     50  * EEPROM/clock controller (also where the idprom, including the
     51  * ethernet address, is located), the audio system (`SUNW,CS4231', same
     52  * as other UltraSPARC and some SPARC systems), and other various
     53  * internal devices found on traditional SPARC systems such as the
     54  * `power', `flashprom', etc., devices.  Other machines with this
     55  * device include the JavaStation10.
     56  *
     57  * The ebus uses an interrupt mapping scheme similar to PCI, though
     58  * the actual structures are different.
     59  */
     60 
     61 /*
     62  * ebus PROM structures
     63  */
     64 
     65 struct ebus_regs {
     66 	u_int32_t	hi;		/* high bits of physaddr */
     67 	u_int32_t	lo;
     68 	u_int32_t	size;
     69 };
     70 
     71 #define	EBUS_PADDR_FROM_REG(reg)	((((paddr_t)((reg)->hi)) << 32UL) | ((paddr_t)(reg)->lo))
     72 
     73 struct ebus_ranges {
     74 	u_int32_t	child_hi;	/* child high phys addr */
     75 	u_int32_t	child_lo;	/* child low phys addr */
     76 	u_int32_t	phys_hi;	/* parent high phys addr */
     77 	u_int32_t	phys_mid;	/* parent mid phys addr */
     78 	u_int32_t	phys_lo;	/* parent low phys addr */
     79 	u_int32_t	size;
     80 };
     81 
     82 struct ebus_interrupt_map {
     83 	u_int32_t	hi;		/* high phys addr mask */
     84 	u_int32_t	lo;		/* low phys addr mask */
     85 	u_int32_t	intr;		/* interrupt mask */
     86 	int32_t		cnode;		/* child node */
     87 	u_int32_t	cintr;		/* child interrupt */
     88 };
     89 
     90 struct ebus_interrupt_map_mask {
     91 	u_int32_t	hi;		/* high phys addr */
     92 	u_int32_t	lo;		/* low phys addr */
     93 	u_int32_t	intr;		/* interrupt */
     94 };
     95 
     96 #endif /* _SPARC64_DEV_EBUSREG_H_ */
     97