ahbreg.h revision 1.2
1 /* $NetBSD: ahbreg.h,v 1.2 1996/09/01 00:54:34 mycroft Exp $ */ 2 3 /* 4 * Copyright (c) 1994, 1996 Charles M. Hannum. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Charles M. Hannum. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Originally written by Julian Elischer (julian (at) tfs.com) 34 * for TRW Financial Systems for use under the MACH(2.5) operating system. 35 * 36 * TRW Financial Systems, in accordance with their agreement with Carnegie 37 * Mellon University, makes this software available to CMU to distribute 38 * or use in any manner that they see fit as long as this message is kept with 39 * the software. For this reason TFS also grants any other persons or 40 * organisations permission to use or modify this software. 41 * 42 * TFS supplies this software to be publicly redistributed 43 * on the understanding that TFS is not responsible for the correct 44 * functioning of this software in any circumstances. 45 */ 46 47 typedef u_long physaddr; 48 typedef u_long physlen; 49 50 /* 51 * AHA1740 EISA board mode registers (Offset from slot base) 52 */ 53 #define PORTADDR 0xCC0 54 #define PORTADDR_ENHANCED 0x80 55 #define BIOSADDR 0xCC1 56 #define INTDEF 0xCC2 57 #define SCSIDEF 0xCC3 58 #define BUSDEF 0xCC4 59 #define RESV0 0xCC5 60 #define RESV1 0xCC6 61 #define RESV2 0xCC7 62 /**** bit definitions for INTDEF ****/ 63 #define INT9 0x00 64 #define INT10 0x01 65 #define INT11 0x02 66 #define INT12 0x03 67 #define INT14 0x05 68 #define INT15 0x06 69 #define INTHIGH 0x08 /* int high=ACTIVE (else edge) */ 70 #define INTEN 0x10 71 /**** bit definitions for SCSIDEF ****/ 72 #define HSCSIID 0x0F /* our SCSI ID */ 73 #define RSTPWR 0x10 /* reset scsi bus on power up or reset */ 74 /**** bit definitions for BUSDEF ****/ 75 #define B0uS 0x00 /* give up bus immediatly */ 76 #define B4uS 0x01 /* delay 4uSec. */ 77 #define B8uS 0x02 78 79 /* 80 * AHA1740 ENHANCED mode mailbox control regs (Offset from slot base) 81 */ 82 #define MBOXOUT0 0xCD0 83 #define MBOXOUT1 0xCD1 84 #define MBOXOUT2 0xCD2 85 #define MBOXOUT3 0xCD3 86 87 #define ATTN 0xCD4 88 #define G2CNTRL 0xCD5 89 #define G2INTST 0xCD6 90 #define G2STAT 0xCD7 91 92 #define MBOXIN0 0xCD8 93 #define MBOXIN1 0xCD9 94 #define MBOXIN2 0xCDA 95 #define MBOXIN3 0xCDB 96 97 #define G2STAT2 0xCDC 98 99 /* 100 * Bit definitions for the 5 control/status registers 101 */ 102 #define ATTN_TARGET 0x0F 103 #define ATTN_OPCODE 0xF0 104 #define OP_IMMED 0x10 105 #define AHB_TARG_RESET 0x80 106 #define OP_START_ECB 0x40 107 #define OP_ABORT_ECB 0x50 108 109 #define G2CNTRL_SET_HOST_READY 0x20 110 #define G2CNTRL_CLEAR_EISA_INT 0x40 111 #define G2CNTRL_HARD_RESET 0x80 112 113 #define G2INTST_TARGET 0x0F 114 #define G2INTST_INT_STAT 0xF0 115 #define AHB_ECB_OK 0x10 116 #define AHB_ECB_RECOVERED 0x50 117 #define AHB_HW_ERR 0x70 118 #define AHB_IMMED_OK 0xA0 119 #define AHB_ECB_ERR 0xC0 120 #define AHB_ASN 0xD0 /* for target mode */ 121 #define AHB_IMMED_ERR 0xE0 122 123 #define G2STAT_BUSY 0x01 124 #define G2STAT_INT_PEND 0x02 125 #define G2STAT_MBOX_EMPTY 0x04 126 127 #define G2STAT2_HOST_READY 0x01 128 129 #define AHB_NSEG 33 /* number of dma segments supported */ 130 131 struct ahb_dma_seg { 132 physaddr seg_addr; 133 physlen seg_len; 134 }; 135 136 struct ahb_ecb_status { 137 u_short status; 138 #define ST_DON 0x0001 139 #define ST_DU 0x0002 140 #define ST_QF 0x0008 141 #define ST_SC 0x0010 142 #define ST_DO 0x0020 143 #define ST_CH 0x0040 144 #define ST_INT 0x0080 145 #define ST_ASA 0x0100 146 #define ST_SNS 0x0200 147 #define ST_INI 0x0800 148 #define ST_ME 0x1000 149 #define ST_ECA 0x4000 150 u_char host_stat; 151 #define HS_OK 0x00 152 #define HS_CMD_ABORTED_HOST 0x04 153 #define HS_CMD_ABORTED_ADAPTER 0x05 154 #define HS_TIMED_OUT 0x11 155 #define HS_HARDWARE_ERR 0x20 156 #define HS_SCSI_RESET_ADAPTER 0x22 157 #define HS_SCSI_RESET_INCOMING 0x23 158 u_char target_stat; 159 u_long resid_count; 160 u_long resid_addr; 161 u_short addit_status; 162 u_char sense_len; 163 u_char unused[9]; 164 u_char cdb[6]; 165 }; 166 167 struct ahb_ecb { 168 u_char opcode; 169 #define ECB_SCSI_OP 0x01 170 u_char:4; 171 u_char options:3; 172 u_char:1; 173 short opt1; 174 #define ECB_CNE 0x0001 175 #define ECB_DI 0x0080 176 #define ECB_SES 0x0400 177 #define ECB_S_G 0x1000 178 #define ECB_DSB 0x4000 179 #define ECB_ARS 0x8000 180 short opt2; 181 #define ECB_LUN 0x0007 182 #define ECB_TAG 0x0008 183 #define ECB_TT 0x0030 184 #define ECB_ND 0x0040 185 #define ECB_DAT 0x0100 186 #define ECB_DIR 0x0200 187 #define ECB_ST 0x0400 188 #define ECB_CHK 0x0800 189 #define ECB_REC 0x4000 190 #define ECB_NRB 0x8000 191 u_short unused1; 192 physaddr data_addr; 193 physlen data_length; 194 physaddr status; 195 physaddr link_addr; 196 short unused2; 197 short unused3; 198 physaddr sense_ptr; 199 u_char req_sense_length; 200 u_char scsi_cmd_length; 201 short cksum; 202 struct scsi_generic scsi_cmd; 203 204 struct ahb_dma_seg ahb_dma[AHB_NSEG]; 205 struct ahb_ecb_status ecb_status; 206 struct scsi_sense_data ecb_sense; 207 /*-----------------end of hardware supported fields----------------*/ 208 TAILQ_ENTRY(ahb_ecb) chain; 209 struct ahb_ecb *nexthash; 210 long hashkey; 211 struct scsi_xfer *xs; /* the scsi_xfer for this cmd */ 212 int flags; 213 #define ECB_ALLOC 0x01 214 #define ECB_ABORT 0x02 215 #define ECB_IMMED 0x04 216 #define ECB_IMMED_FAIL 0x08 217 int timeout; 218 }; 219
Indexes created Tue Sep 30 11:09:46 GMT 2025