ahbreg.h revision 1.5
1 /* $NetBSD: ahbreg.h,v 1.5 1998/02/17 03:02:30 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1994, 1996 Charles M. Hannum. All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by Charles M. Hannum. 54 * 4. The name of the author may not be used to endorse or promote products 55 * derived from this software without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 58 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 59 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 60 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 61 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 62 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 63 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 64 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 65 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 66 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * Originally written by Julian Elischer (julian (at) tfs.com) 71 * for TRW Financial Systems for use under the MACH(2.5) operating system. 72 * 73 * TRW Financial Systems, in accordance with their agreement with Carnegie 74 * Mellon University, makes this software available to CMU to distribute 75 * or use in any manner that they see fit as long as this message is kept with 76 * the software. For this reason TFS also grants any other persons or 77 * organisations permission to use or modify this software. 78 * 79 * TFS supplies this software to be publicly redistributed 80 * on the understanding that TFS is not responsible for the correct 81 * functioning of this software in any circumstances. 82 */ 83 84 typedef u_long physaddr; 85 typedef u_long physlen; 86 87 /* 88 * AHA1740 EISA board mode registers (Offset from slot base) 89 */ 90 #define PORTADDR 0xCC0 91 #define PORTADDR_ENHANCED 0x80 92 #define BIOSADDR 0xCC1 93 #define INTDEF 0xCC2 94 #define SCSIDEF 0xCC3 95 #define BUSDEF 0xCC4 96 #define RESV0 0xCC5 97 #define RESV1 0xCC6 98 #define RESV2 0xCC7 99 /**** bit definitions for INTDEF ****/ 100 #define INT9 0x00 101 #define INT10 0x01 102 #define INT11 0x02 103 #define INT12 0x03 104 #define INT14 0x05 105 #define INT15 0x06 106 #define INTHIGH 0x08 /* int high=ACTIVE (else edge) */ 107 #define INTEN 0x10 108 /**** bit definitions for SCSIDEF ****/ 109 #define HSCSIID 0x0F /* our SCSI ID */ 110 #define RSTPWR 0x10 /* reset scsi bus on power up or reset */ 111 /**** bit definitions for BUSDEF ****/ 112 #define B0uS 0x00 /* give up bus immediatly */ 113 #define B4uS 0x01 /* delay 4uSec. */ 114 #define B8uS 0x02 115 116 /* 117 * AHA1740 ENHANCED mode mailbox control regs (Offset from slot base) 118 */ 119 #define MBOXOUT0 0xCD0 120 #define MBOXOUT1 0xCD1 121 #define MBOXOUT2 0xCD2 122 #define MBOXOUT3 0xCD3 123 124 #define ATTN 0xCD4 125 #define G2CNTRL 0xCD5 126 #define G2INTST 0xCD6 127 #define G2STAT 0xCD7 128 129 #define MBOXIN0 0xCD8 130 #define MBOXIN1 0xCD9 131 #define MBOXIN2 0xCDA 132 #define MBOXIN3 0xCDB 133 134 #define G2STAT2 0xCDC 135 136 /* 137 * Bit definitions for the 5 control/status registers 138 */ 139 #define ATTN_TARGET 0x0F 140 #define ATTN_OPCODE 0xF0 141 #define OP_IMMED 0x10 142 #define AHB_TARG_RESET 0x80 143 #define OP_START_ECB 0x40 144 #define OP_ABORT_ECB 0x50 145 146 #define G2CNTRL_SET_HOST_READY 0x20 147 #define G2CNTRL_CLEAR_EISA_INT 0x40 148 #define G2CNTRL_HARD_RESET 0x80 149 150 #define G2INTST_TARGET 0x0F 151 #define G2INTST_INT_STAT 0xF0 152 #define AHB_ECB_OK 0x10 153 #define AHB_ECB_RECOVERED 0x50 154 #define AHB_HW_ERR 0x70 155 #define AHB_IMMED_OK 0xA0 156 #define AHB_ECB_ERR 0xC0 157 #define AHB_ASN 0xD0 /* for target mode */ 158 #define AHB_IMMED_ERR 0xE0 159 160 #define G2STAT_BUSY 0x01 161 #define G2STAT_INT_PEND 0x02 162 #define G2STAT_MBOX_EMPTY 0x04 163 164 #define G2STAT2_HOST_READY 0x01 165 166 #define AHB_NSEG 33 /* number of dma segments supported */ 167 168 struct ahb_dma_seg { 169 physaddr seg_addr; 170 physlen seg_len; 171 }; 172 173 struct ahb_ecb_status { 174 u_short status; 175 #define ST_DON 0x0001 176 #define ST_DU 0x0002 177 #define ST_QF 0x0008 178 #define ST_SC 0x0010 179 #define ST_DO 0x0020 180 #define ST_CH 0x0040 181 #define ST_INT 0x0080 182 #define ST_ASA 0x0100 183 #define ST_SNS 0x0200 184 #define ST_INI 0x0800 185 #define ST_ME 0x1000 186 #define ST_ECA 0x4000 187 u_char host_stat; 188 #define HS_OK 0x00 189 #define HS_CMD_ABORTED_HOST 0x04 190 #define HS_CMD_ABORTED_ADAPTER 0x05 191 #define HS_TIMED_OUT 0x11 192 #define HS_HARDWARE_ERR 0x20 193 #define HS_SCSI_RESET_ADAPTER 0x22 194 #define HS_SCSI_RESET_INCOMING 0x23 195 u_char target_stat; 196 u_long resid_count; 197 u_long resid_addr; 198 u_short addit_status; 199 u_char sense_len; 200 u_char unused[9]; 201 u_char cdb[6]; 202 }; 203 204 struct ahb_ecb { 205 u_char opcode; 206 #define ECB_SCSI_OP 0x01 207 u_char:4; 208 u_char options:3; 209 u_char:1; 210 short opt1; 211 #define ECB_CNE 0x0001 212 #define ECB_DI 0x0080 213 #define ECB_SES 0x0400 214 #define ECB_S_G 0x1000 215 #define ECB_DSB 0x4000 216 #define ECB_ARS 0x8000 217 short opt2; 218 #define ECB_LUN 0x0007 219 #define ECB_TAG 0x0008 220 #define ECB_TT 0x0030 221 #define ECB_ND 0x0040 222 #define ECB_DAT 0x0100 223 #define ECB_DIR 0x0200 224 #define ECB_ST 0x0400 225 #define ECB_CHK 0x0800 226 #define ECB_REC 0x4000 227 #define ECB_NRB 0x8000 228 u_short unused1; 229 physaddr data_addr; 230 physlen data_length; 231 physaddr status; 232 physaddr link_addr; 233 short unused2; 234 short unused3; 235 physaddr sense_ptr; 236 u_char req_sense_length; 237 u_char scsi_cmd_length; 238 short cksum; 239 struct scsi_generic scsi_cmd; 240 241 struct ahb_dma_seg ahb_dma[AHB_NSEG]; 242 struct ahb_ecb_status ecb_status; 243 struct scsipi_sense_data ecb_sense; 244 /*-----------------end of hardware supported fields----------------*/ 245 TAILQ_ENTRY(ahb_ecb) chain; 246 struct ahb_ecb *nexthash; 247 long hashkey; 248 struct scsipi_xfer *xs; /* the scsipi_xfer for this cmd */ 249 int flags; 250 #define ECB_ALLOC 0x01 251 #define ECB_ABORT 0x02 252 #define ECB_IMMED 0x04 253 #define ECB_IMMED_FAIL 0x08 254 int timeout; 255 256 /* 257 * This DMA map maps the buffer involved in the transfer. 258 * Its contents are loaded into "ahb_dma" above. 259 */ 260 bus_dmamap_t dmamap_xfer; 261 }; 262
Indexes created Tue Sep 30 11:09:46 GMT 2025