ahbreg.h revision 1.6
1 /* $NetBSD: ahbreg.h,v 1.6 1998/08/15 01:59:25 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1994, 1996 Charles M. Hannum. All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by Charles M. Hannum. 54 * 4. The name of the author may not be used to endorse or promote products 55 * derived from this software without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 58 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 59 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 60 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 61 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 62 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 63 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 64 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 65 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 66 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * Originally written by Julian Elischer (julian (at) tfs.com) 71 * for TRW Financial Systems for use under the MACH(2.5) operating system. 72 * 73 * TRW Financial Systems, in accordance with their agreement with Carnegie 74 * Mellon University, makes this software available to CMU to distribute 75 * or use in any manner that they see fit as long as this message is kept with 76 * the software. For this reason TFS also grants any other persons or 77 * organisations permission to use or modify this software. 78 * 79 * TFS supplies this software to be publicly redistributed 80 * on the understanding that TFS is not responsible for the correct 81 * functioning of this software in any circumstances. 82 */ 83 84 typedef u_long physaddr; 85 typedef u_long physlen; 86 87 /* 88 * Offset of AHA1740 registers, relative from slot base. 89 */ 90 #define AHB_PORT_OFFSET 0xcc0 91 #define AHB_PORT_SIZE 32 92 93 /* 94 * AHA1740 EISA board mode registers (relative to port offset) 95 */ 96 #define PORTADDR 0x00 97 #define PORTADDR_ENHANCED 0x80 98 #define BIOSADDR 0x01 99 #define INTDEF 0x02 100 #define SCSIDEF 0x03 101 #define BUSDEF 0x04 102 #define RESV0 0x05 103 #define RESV1 0x06 104 #define RESV2 0x07 105 /**** bit definitions for INTDEF ****/ 106 #define INT9 0x00 107 #define INT10 0x01 108 #define INT11 0x02 109 #define INT12 0x03 110 #define INT14 0x05 111 #define INT15 0x06 112 #define INTHIGH 0x08 /* int high=ACTIVE (else edge) */ 113 #define INTEN 0x10 114 /**** bit definitions for SCSIDEF ****/ 115 #define HSCSIID 0x0F /* our SCSI ID */ 116 #define RSTPWR 0x10 /* reset scsi bus on power up or reset */ 117 /**** bit definitions for BUSDEF ****/ 118 #define B0uS 0x00 /* give up bus immediatly */ 119 #define B4uS 0x01 /* delay 4uSec. */ 120 #define B8uS 0x02 121 122 /* 123 * AHA1740 ENHANCED mode mailbox control regs (relative to port offset) 124 */ 125 #define MBOXOUT0 0x10 126 #define MBOXOUT1 0x11 127 #define MBOXOUT2 0x12 128 #define MBOXOUT3 0x13 129 130 #define ATTN 0x14 131 #define G2CNTRL 0x15 132 #define G2INTST 0x16 133 #define G2STAT 0x17 134 135 #define MBOXIN0 0x18 136 #define MBOXIN1 0x19 137 #define MBOXIN2 0x1A 138 #define MBOXIN3 0x1B 139 140 #define G2STAT2 0x1C 141 142 /* 143 * Bit definitions for the 5 control/status registers 144 */ 145 #define ATTN_TARGET 0x0F 146 #define ATTN_OPCODE 0xF0 147 #define OP_IMMED 0x10 148 #define AHB_TARG_RESET 0x80 149 #define OP_START_ECB 0x40 150 #define OP_ABORT_ECB 0x50 151 152 #define G2CNTRL_SET_HOST_READY 0x20 153 #define G2CNTRL_CLEAR_EISA_INT 0x40 154 #define G2CNTRL_HARD_RESET 0x80 155 156 #define G2INTST_TARGET 0x0F 157 #define G2INTST_INT_STAT 0xF0 158 #define AHB_ECB_OK 0x10 159 #define AHB_ECB_RECOVERED 0x50 160 #define AHB_HW_ERR 0x70 161 #define AHB_IMMED_OK 0xA0 162 #define AHB_ECB_ERR 0xC0 163 #define AHB_ASN 0xD0 /* for target mode */ 164 #define AHB_IMMED_ERR 0xE0 165 166 #define G2STAT_BUSY 0x01 167 #define G2STAT_INT_PEND 0x02 168 #define G2STAT_MBOX_EMPTY 0x04 169 170 #define G2STAT2_HOST_READY 0x01 171 172 #define AHB_NSEG 33 /* number of dma segments supported */ 173 174 struct ahb_dma_seg { 175 physaddr seg_addr; 176 physlen seg_len; 177 }; 178 179 struct ahb_ecb_status { 180 u_short status; 181 #define ST_DON 0x0001 182 #define ST_DU 0x0002 183 #define ST_QF 0x0008 184 #define ST_SC 0x0010 185 #define ST_DO 0x0020 186 #define ST_CH 0x0040 187 #define ST_INT 0x0080 188 #define ST_ASA 0x0100 189 #define ST_SNS 0x0200 190 #define ST_INI 0x0800 191 #define ST_ME 0x1000 192 #define ST_ECA 0x4000 193 u_char host_stat; 194 #define HS_OK 0x00 195 #define HS_CMD_ABORTED_HOST 0x04 196 #define HS_CMD_ABORTED_ADAPTER 0x05 197 #define HS_TIMED_OUT 0x11 198 #define HS_HARDWARE_ERR 0x20 199 #define HS_SCSI_RESET_ADAPTER 0x22 200 #define HS_SCSI_RESET_INCOMING 0x23 201 u_char target_stat; 202 u_long resid_count; 203 u_long resid_addr; 204 u_short addit_status; 205 u_char sense_len; 206 u_char unused[9]; 207 u_char cdb[6]; 208 }; 209 210 struct ahb_ecb { 211 u_char opcode; 212 #define ECB_SCSI_OP 0x01 213 u_char:4; 214 u_char options:3; 215 u_char:1; 216 short opt1; 217 #define ECB_CNE 0x0001 218 #define ECB_DI 0x0080 219 #define ECB_SES 0x0400 220 #define ECB_S_G 0x1000 221 #define ECB_DSB 0x4000 222 #define ECB_ARS 0x8000 223 short opt2; 224 #define ECB_LUN 0x0007 225 #define ECB_TAG 0x0008 226 #define ECB_TT 0x0030 227 #define ECB_ND 0x0040 228 #define ECB_DAT 0x0100 229 #define ECB_DIR 0x0200 230 #define ECB_ST 0x0400 231 #define ECB_CHK 0x0800 232 #define ECB_REC 0x4000 233 #define ECB_NRB 0x8000 234 u_short unused1; 235 physaddr data_addr; 236 physlen data_length; 237 physaddr status; 238 physaddr link_addr; 239 short unused2; 240 short unused3; 241 physaddr sense_ptr; 242 u_char req_sense_length; 243 u_char scsi_cmd_length; 244 short cksum; 245 struct scsi_generic scsi_cmd; 246 247 struct ahb_dma_seg ahb_dma[AHB_NSEG]; 248 struct ahb_ecb_status ecb_status; 249 struct scsipi_sense_data ecb_sense; 250 /*-----------------end of hardware supported fields----------------*/ 251 TAILQ_ENTRY(ahb_ecb) chain; 252 struct ahb_ecb *nexthash; 253 long hashkey; 254 struct scsipi_xfer *xs; /* the scsipi_xfer for this cmd */ 255 int flags; 256 #define ECB_ALLOC 0x01 257 #define ECB_ABORT 0x02 258 #define ECB_IMMED 0x04 259 #define ECB_IMMED_FAIL 0x08 260 int timeout; 261 262 /* 263 * This DMA map maps the buffer involved in the transfer. 264 * Its contents are loaded into "ahb_dma" above. 265 */ 266 bus_dmamap_t dmamap_xfer; 267 }; 268
Indexes created Tue Sep 30 07:10:03 GMT 2025