eisareg.h revision 1.2 1 /* $NetBSD: eisareg.h,v 1.2 1996/02/27 00:21:02 cgd Exp $ */
2
3 /*
4 * Copyright (c) 1995, 1996 Christopher G. Demetriou
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Christopher G. Demetriou
18 * for the NetBSD Project.
19 * 4. The name of the author may not be used to endorse or promote products
20 * derived from this software without specific prior written permission
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef __DEV_EISA_EISAREG_H__
35 #define __DEV_EISA_EISAREG_H__
36
37 /*
38 * Register (etc.) descriptions for the EISA bus.
39
40 * Mostly culled from EISA chipset descriptions in:
41 * Intel Peripheral Components Databook (1992)
42 */
43
44 /*
45 * Max number of EISA slots in a machine. 64K I/O space total.
46 */
47 #define EISA_MAX_SLOT 16 /* number of slots. 0 -> 0xf */
48
49 /*
50 * Slot I/O space size, and I/O address of a given slot.
51 */
52 #define EISA_SLOT_SIZE 0x1000
53 #define EISA_SLOT_ADDR(s) ((s) * EISA_SLOT_SIZE)
54
55 /*
56 * Slot offsets for important/standard registers.
57 */
58 #define EISA_SLOTOFF_VID 0xc80 /* offset of vendor id regs */
59 #define EISA_NVIDREGS 2
60 #define EISA_SLOTOFF_PID 0xc82 /* offset of product id regs */
61 #define EISA_NPIDREGS 2
62
63
64 /*
65 * EISA ID functions, used to manipulate and decode EISA ID registers.
66 * ``Somebody was let out without adult supervision.''
67 */
68
69 #define EISA_IDSTRINGLEN 8 /* length of ID string, incl. NUL */
70
71 /*
72 * Vendor ID: three characters, encoded in 16 bits.
73 *
74 * EISA_VENDID_NODEV returns true if there's no device in the slot.
75 * EISA_VENDID_IDDELAY returns true if there's a device in the slot,
76 * but that device hasn't been configured by system firmware.
77 * EISA_VENDID_n returns the "n"th character of the vendor ID.
78 */
79 #define EISA_VENDID_NODEV(vid) \
80 (((vid)[0] & 0x80) != 0)
81 #define EISA_VENDID_IDDELAY(vid) \
82 (((vid)[0] & 0xf0) == 0x70)
83 #define EISA_VENDID_0(vid) \
84 ((((vid)[0] & 0x7c) >> 2) + '@')
85 #define EISA_VENDID_1(vid) \
86 (((((vid)[0] & 0x03) << 3) | (((vid)[1] & 0xe0) >> 5)) + '@')
87 #define EISA_VENDID_2(vid) \
88 (((vid)[1] & 0x1f) + '@')
89
90 /*
91 * Product ID: four hex digits, encoded in 16 bits (normal, sort of).
92 *
93 * EISA_PRIDID_n returns the "n"th hex digit of the product ID.
94 */
95 #define __EISA_HEX_MAP "0123456789ABCDEF"
96 #define EISA_PRODID_0(pid) \
97 (__EISA_HEX_MAP[(((pid)[0] >> 4) & 0xf)])
98 #define EISA_PRODID_1(pid) \
99 (__EISA_HEX_MAP[(((pid)[0] >> 0) & 0xf)])
100 #define EISA_PRODID_2(pid) \
101 (__EISA_HEX_MAP[(((pid)[1] >> 4) & 0xf)])
102 #define EISA_PRODID_3(pid) \
103 (__EISA_HEX_MAP[(((pid)[1] >> 0) & 0xf)])
104
105 #endif /* !__DEV_EISA_EISAREG_H__ */
106