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mlx_eisa.c revision 1.28
      1  1.28   thorpej /*	$NetBSD: mlx_eisa.c,v 1.28 2021/04/24 23:36:53 thorpej Exp $	*/
      2   1.1        ad 
      3   1.1        ad /*-
      4   1.1        ad  * Copyright (c) 2001 The NetBSD Foundation, Inc.
      5   1.1        ad  * All rights reserved.
      6   1.1        ad  *
      7   1.1        ad  * This code is derived from software contributed to The NetBSD Foundation
      8   1.1        ad  * by Andrew Doran.
      9   1.1        ad  *
     10   1.1        ad  * Redistribution and use in source and binary forms, with or without
     11   1.1        ad  * modification, are permitted provided that the following conditions
     12   1.1        ad  * are met:
     13   1.1        ad  * 1. Redistributions of source code must retain the above copyright
     14   1.1        ad  *    notice, this list of conditions and the following disclaimer.
     15   1.1        ad  * 2. Redistributions in binary form must reproduce the above copyright
     16   1.1        ad  *    notice, this list of conditions and the following disclaimer in the
     17   1.1        ad  *    documentation and/or other materials provided with the distribution.
     18   1.1        ad  *
     19   1.1        ad  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20   1.1        ad  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21   1.1        ad  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22   1.1        ad  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23   1.1        ad  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24   1.1        ad  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25   1.1        ad  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26   1.1        ad  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27   1.1        ad  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28   1.1        ad  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29   1.1        ad  * POSSIBILITY OF SUCH DAMAGE.
     30   1.1        ad  */
     31   1.1        ad 
     32   1.1        ad /*
     33   1.1        ad  * EISA front-end for mlx(4) driver.
     34   1.1        ad  */
     35   1.4     lukem 
     36   1.4     lukem #include <sys/cdefs.h>
     37  1.28   thorpej __KERNEL_RCSID(0, "$NetBSD: mlx_eisa.c,v 1.28 2021/04/24 23:36:53 thorpej Exp $");
     38   1.1        ad 
     39   1.1        ad #include <sys/param.h>
     40   1.1        ad #include <sys/systm.h>
     41   1.1        ad #include <sys/device.h>
     42  1.26  pgoyette #include <sys/module.h>
     43  1.19        ad #include <sys/bus.h>
     44  1.19        ad #include <sys/intr.h>
     45   1.1        ad 
     46   1.1        ad #include <dev/eisa/eisavar.h>
     47   1.1        ad #include <dev/eisa/eisadevs.h>
     48   1.1        ad 
     49   1.1        ad #include <dev/ic/mlxreg.h>
     50   1.1        ad #include <dev/ic/mlxio.h>
     51   1.1        ad #include <dev/ic/mlxvar.h>
     52   1.1        ad 
     53  1.26  pgoyette #include "ioconf.h"
     54  1.26  pgoyette 
     55  1.12        ad #define	MLX_EISA_SLOT_OFFSET		0x0c80
     56  1.12        ad #define	MLX_EISA_IOSIZE			(0x0ce0 - MLX_EISA_SLOT_OFFSET)
     57  1.12        ad #define	MLX_EISA_CFG01			(0x0cc0 - MLX_EISA_SLOT_OFFSET)
     58  1.12        ad #define	MLX_EISA_CFG02			(0x0cc1 - MLX_EISA_SLOT_OFFSET)
     59  1.12        ad #define	MLX_EISA_CFG03			(0x0cc3 - MLX_EISA_SLOT_OFFSET)
     60  1.12        ad #define	MLX_EISA_CFG04			(0x0c8d - MLX_EISA_SLOT_OFFSET)
     61  1.12        ad #define	MLX_EISA_CFG05			(0x0c90 - MLX_EISA_SLOT_OFFSET)
     62  1.12        ad #define	MLX_EISA_CFG06			(0x0c91 - MLX_EISA_SLOT_OFFSET)
     63  1.12        ad #define	MLX_EISA_CFG07			(0x0c92 - MLX_EISA_SLOT_OFFSET)
     64  1.12        ad #define	MLX_EISA_CFG08			(0x0c93 - MLX_EISA_SLOT_OFFSET)
     65  1.12        ad #define	MLX_EISA_CFG09			(0x0c94 - MLX_EISA_SLOT_OFFSET)
     66  1.12        ad #define	MLX_EISA_CFG10			(0x0c95 - MLX_EISA_SLOT_OFFSET)
     67   1.1        ad 
     68  1.22    cegger static void	mlx_eisa_attach(device_t, device_t, void *);
     69  1.22    cegger static int	mlx_eisa_match(device_t, cfdata_t, void *);
     70  1.26  pgoyette static int	mlx_eisa_rescan(device_t, const char *, const int *);
     71   1.1        ad 
     72   1.1        ad static int	mlx_v1_submit(struct mlx_softc *, struct mlx_ccb *);
     73   1.1        ad static int	mlx_v1_findcomplete(struct mlx_softc *, u_int *, u_int *);
     74   1.1        ad static void	mlx_v1_intaction(struct mlx_softc *, int);
     75   1.1        ad static int	mlx_v1_fw_handshake(struct mlx_softc *, int *, int *, int *);
     76   1.1        ad #ifdef MLX_RESET
     77   1.1        ad static int	mlx_v1_reset(struct mlx_softc *);
     78   1.1        ad #endif
     79   1.1        ad 
     80  1.26  pgoyette CFATTACH_DECL3_NEW(mlx_eisa, sizeof(struct mlx_softc),
     81  1.26  pgoyette     mlx_eisa_match, mlx_eisa_attach, NULL, NULL, mlx_eisa_rescan, NULL, 0);
     82   1.1        ad 
     83  1.27   thorpej static const struct device_compatible_entry compat_data[] = {
     84  1.27   thorpej 				/* nchan */
     85  1.27   thorpej 	{ .compat = "MLX0070",	.value = 1 },
     86  1.27   thorpej 	{ .compat = "MLX0071",	.value = 3 },
     87  1.27   thorpej 	{ .compat = "MLX0072",	.value = 3 },
     88  1.27   thorpej 	{ .compat = "MLX0073",	.value = 2 },
     89  1.27   thorpej 	{ .compat = "MLX0074",	.value = 1 },
     90  1.27   thorpej 	{ .compat = "MLX0075",	.value = 3 },
     91  1.27   thorpej 	{ .compat = "MLX0076",	.value = 2 },
     92  1.27   thorpej 	{ .compat = "MLX0077",	.value = 1 },
     93  1.27   thorpej 	DEVICE_COMPAT_EOL
     94   1.1        ad };
     95   1.1        ad 
     96   1.1        ad static int
     97  1.22    cegger mlx_eisa_match(device_t parent, cfdata_t match,
     98  1.17  christos     void *aux)
     99   1.1        ad {
    100  1.27   thorpej 	struct eisa_attach_args *ea = aux;
    101   1.1        ad 
    102  1.27   thorpej 	return (eisa_compatible_match(ea, compat_data));
    103   1.1        ad }
    104   1.1        ad 
    105   1.1        ad static void
    106  1.22    cegger mlx_eisa_attach(device_t parent, device_t self, void *aux)
    107   1.1        ad {
    108  1.27   thorpej 	struct eisa_attach_args *ea = aux;
    109  1.27   thorpej 	const struct device_compatible_entry *dce;
    110   1.1        ad 	bus_space_handle_t ioh;
    111   1.1        ad 	eisa_chipset_tag_t ec;
    112   1.1        ad 	eisa_intr_handle_t ih;
    113   1.1        ad 	struct mlx_softc *mlx;
    114   1.1        ad 	bus_space_tag_t iot;
    115   1.1        ad 	const char *intrstr;
    116  1.27   thorpej 	int irq, icfg;
    117  1.24  christos 	char intrbuf[EISA_INTRSTR_LEN];
    118  1.12        ad 
    119  1.15   thorpej 	mlx = device_private(self);
    120   1.1        ad 	iot = ea->ea_iot;
    121   1.1        ad 	ec = ea->ea_ec;
    122  1.12        ad 
    123   1.1        ad 	if (bus_space_map(iot, EISA_SLOT_ADDR(ea->ea_slot) +
    124   1.1        ad 	    MLX_EISA_SLOT_OFFSET, MLX_EISA_IOSIZE, 0, &ioh)) {
    125  1.25   msaitoh 		aprint_error(": can't map i/o space\n");
    126   1.1        ad 		return;
    127   1.1        ad 	}
    128   1.1        ad 
    129  1.23       chs 	mlx->mlx_dv = self;
    130   1.1        ad 	mlx->mlx_iot = iot;
    131   1.1        ad 	mlx->mlx_ioh = ioh;
    132   1.1        ad 	mlx->mlx_dmat = ea->ea_dmat;
    133   1.1        ad 
    134  1.13     perry 	/*
    135   1.1        ad 	 * Map and establish the interrupt.
    136   1.1        ad 	 */
    137  1.12        ad 	icfg = bus_space_read_1(iot, ioh, MLX_EISA_CFG03);
    138  1.12        ad 
    139  1.12        ad 	switch (icfg & 0xf0) {
    140   1.1        ad 	case 0xa0:
    141   1.1        ad 		irq = 11;
    142   1.1        ad 		break;
    143   1.1        ad 	case 0xc0:
    144   1.1        ad 		irq = 12;
    145   1.1        ad 		break;
    146   1.1        ad 	case 0xe0:
    147   1.1        ad 		irq = 14;
    148   1.1        ad 		break;
    149   1.1        ad 	case 0x80:
    150   1.1        ad 		irq = 15;
    151   1.1        ad 		break;
    152   1.1        ad 	default:
    153  1.25   msaitoh 		aprint_error(": controller on invalid IRQ\n");
    154   1.1        ad 		return;
    155   1.1        ad 	}
    156   1.1        ad 
    157   1.1        ad 	if (eisa_intr_map(ec, irq, &ih)) {
    158  1.25   msaitoh 		aprint_error(": can't map interrupt (%d)\n", irq);
    159   1.1        ad 		return;
    160   1.1        ad 	}
    161   1.1        ad 
    162  1.24  christos 	intrstr = eisa_intr_string(ec, ih, intrbuf, sizeof(intrbuf));
    163  1.12        ad 	mlx->mlx_ih = eisa_intr_establish(ec, ih,
    164  1.12        ad 	    ((icfg & 0x08) != 0 ? IST_LEVEL : IST_EDGE),
    165  1.12        ad 	    IPL_BIO, mlx_intr, mlx);
    166   1.1        ad 	if (mlx->mlx_ih == NULL) {
    167  1.25   msaitoh 		aprint_error(": can't establish interrupt");
    168   1.1        ad 		if (intrstr != NULL)
    169  1.25   msaitoh 			aprint_normal(" at %s", intrstr);
    170  1.25   msaitoh 		aprint_normal("\n");
    171   1.1        ad 		return;
    172   1.1        ad 	}
    173   1.1        ad 
    174  1.27   thorpej 	dce = eisa_compatible_lookup(ea, compat_data);
    175  1.27   thorpej 	KASSERT(dce != NULL);
    176  1.27   thorpej 
    177  1.27   thorpej 	mlx->mlx_ci.ci_nchan = (int)dce->value;
    178   1.7        ad 	mlx->mlx_ci.ci_iftype = 1;
    179   1.1        ad 
    180   1.1        ad 	mlx->mlx_submit = mlx_v1_submit;
    181   1.1        ad 	mlx->mlx_findcomplete = mlx_v1_findcomplete;
    182   1.1        ad 	mlx->mlx_intaction = mlx_v1_intaction;
    183   1.1        ad 	mlx->mlx_fw_handshake = mlx_v1_fw_handshake;
    184   1.1        ad #ifdef MLX_RESET
    185   1.1        ad 	mlx->mlx_reset = mlx_v1_reset;
    186   1.1        ad #endif
    187   1.1        ad 
    188  1.25   msaitoh 	aprint_normal(": Mylex RAID\n");
    189   1.1        ad 	mlx_init(mlx, intrstr);
    190   1.1        ad }
    191   1.1        ad 
    192  1.26  pgoyette static int
    193  1.28   thorpej mlx_eisa_rescan(device_t self, const char *ifattr, const int *locs)
    194  1.26  pgoyette {
    195  1.26  pgoyette 
    196  1.26  pgoyette 	return mlx_configure(device_private(self), 1);
    197  1.26  pgoyette }
    198  1.26  pgoyette 
    199   1.1        ad /*
    200   1.1        ad  * ================= V1 interface linkage =================
    201   1.1        ad  */
    202   1.1        ad 
    203   1.1        ad /*
    204   1.1        ad  * Try to give (mc) to the controller.  Returns 1 if successful, 0 on
    205   1.1        ad  * failure (the controller is not ready to take a command).
    206   1.1        ad  *
    207   1.1        ad  * Must be called at splbio or in a fashion that prevents reentry.
    208   1.1        ad  */
    209   1.1        ad static int
    210   1.1        ad mlx_v1_submit(struct mlx_softc *mlx, struct mlx_ccb *mc)
    211   1.1        ad {
    212   1.1        ad 
    213   1.1        ad 	/* Ready for our command? */
    214   1.1        ad 	if ((mlx_inb(mlx, MLX_V1REG_IDB) & MLX_V1_IDB_FULL) == 0) {
    215   1.1        ad 		/* Copy mailbox data to window. */
    216   1.1        ad 		bus_space_write_region_1(mlx->mlx_iot, mlx->mlx_ioh,
    217   1.8        ad 		    MLX_V1REG_MAILBOX, mc->mc_mbox, 13);
    218   1.1        ad 		bus_space_barrier(mlx->mlx_iot, mlx->mlx_ioh,
    219   1.8        ad 		    MLX_V1REG_MAILBOX, 13,
    220   1.1        ad 		    BUS_SPACE_BARRIER_WRITE);
    221   1.1        ad 
    222   1.1        ad 		/* Post command. */
    223   1.7        ad 		mlx_outb(mlx, MLX_V1REG_IDB, MLX_V1_IDB_FULL);
    224   1.1        ad 		return (1);
    225   1.1        ad 	}
    226   1.1        ad 
    227   1.1        ad 	return (0);
    228   1.1        ad }
    229   1.1        ad 
    230   1.1        ad /*
    231   1.1        ad  * See if a command has been completed, if so acknowledge its completion and
    232   1.1        ad  * recover the slot number and status code.
    233   1.1        ad  *
    234   1.1        ad  * Must be called at splbio or in a fashion that prevents reentry.
    235   1.1        ad  */
    236   1.1        ad static int
    237   1.1        ad mlx_v1_findcomplete(struct mlx_softc *mlx, u_int *slot, u_int *status)
    238   1.1        ad {
    239   1.1        ad 
    240   1.1        ad 	/* Status available? */
    241   1.7        ad 	if ((mlx_inb(mlx, MLX_V1REG_ODB) & MLX_V1_ODB_SAVAIL) != 0) {
    242   1.1        ad 		*slot = mlx_inb(mlx, MLX_V1REG_MAILBOX + 0x0d);
    243   1.1        ad 		*status = mlx_inw(mlx, MLX_V1REG_MAILBOX + 0x0e);
    244   1.1        ad 
    245   1.1        ad 		/* Acknowledge completion. */
    246   1.1        ad 		mlx_outb(mlx, MLX_V1REG_ODB, MLX_V1_ODB_SAVAIL);
    247   1.1        ad 		mlx_outb(mlx, MLX_V1REG_IDB, MLX_V1_IDB_SACK);
    248   1.1        ad 		return (1);
    249   1.1        ad 	}
    250   1.1        ad 
    251   1.1        ad 	return (0);
    252   1.1        ad }
    253   1.1        ad 
    254   1.1        ad /*
    255   1.1        ad  * Enable/disable interrupts as requested. (No acknowledge required)
    256   1.1        ad  *
    257   1.1        ad  * Must be called at splbio or in a fashion that prevents reentry.
    258   1.1        ad  */
    259   1.1        ad static void
    260   1.1        ad mlx_v1_intaction(struct mlx_softc *mlx, int action)
    261   1.1        ad {
    262   1.1        ad 
    263   1.1        ad 	mlx_outb(mlx, MLX_V1REG_IE, action ? 1 : 0);
    264   1.1        ad }
    265   1.1        ad 
    266   1.1        ad /*
    267   1.1        ad  * Poll for firmware error codes during controller initialisation.
    268   1.1        ad  *
    269   1.1        ad  * Returns 0 if initialisation is complete, 1 if still in progress but no
    270   1.1        ad  * error has been fetched, 2 if an error has been retrieved.
    271   1.1        ad  */
    272  1.13     perry static int
    273   1.1        ad mlx_v1_fw_handshake(struct mlx_softc *mlx, int *error, int *param1, int *param2)
    274   1.1        ad {
    275   1.1        ad 	u_int8_t fwerror;
    276   1.1        ad 
    277   1.1        ad 	/*
    278   1.1        ad 	 * First time around, enable the IDB interrupt and clear any
    279   1.1        ad 	 * hardware completion status.
    280   1.1        ad 	 */
    281   1.1        ad 	if ((mlx->mlx_flags & MLXF_FW_INITTED) == 0) {
    282   1.1        ad 		mlx_outb(mlx, MLX_V1REG_ODB_EN, 1);
    283   1.6        ad 		DELAY(1000);
    284   1.6        ad 		mlx_outb(mlx, MLX_V1REG_ODB, 1);
    285   1.1        ad 		DELAY(1000);
    286   1.1        ad 		mlx_outb(mlx, MLX_V1REG_IDB, MLX_V1_IDB_SACK);
    287   1.1        ad 		DELAY(1000);
    288   1.1        ad 		mlx->mlx_flags |= MLXF_FW_INITTED;
    289   1.1        ad 	}
    290   1.1        ad 
    291   1.1        ad 	/* Init in progress? */
    292   1.1        ad 	if ((mlx_inb(mlx, MLX_V1REG_IDB) & MLX_V1_IDB_INIT_BUSY) == 0)
    293   1.1        ad 		return (0);
    294   1.1        ad 
    295   1.1        ad 	/* Test error value. */
    296   1.1        ad 	fwerror = mlx_inb(mlx, MLX_V1REG_ODB);
    297   1.1        ad 
    298   1.1        ad 	if ((fwerror & MLX_V1_FWERROR_PEND) == 0)
    299   1.1        ad 		return (1);
    300   1.1        ad 
    301   1.1        ad 	/* XXX Fetch status. */
    302   1.1        ad 	*error = fwerror & 0xf0;
    303   1.1        ad 	*param1 = -1;
    304   1.1        ad 	*param2 = -1;
    305   1.1        ad 
    306   1.1        ad 	/* Acknowledge. */
    307   1.1        ad 	mlx_outb(mlx, MLX_V1REG_ODB, fwerror);
    308   1.1        ad 
    309   1.1        ad 	return (2);
    310   1.1        ad }
    311   1.1        ad 
    312   1.1        ad #ifdef MLX_RESET
    313   1.1        ad /*
    314   1.1        ad  * Reset the controller.  Return non-zero on failure.
    315   1.1        ad  */
    316  1.13     perry static int
    317   1.1        ad mlx_v1_reset(struct mlx_softc *mlx)
    318   1.1        ad {
    319   1.1        ad 	int i;
    320   1.1        ad 
    321   1.1        ad 	mlx_outb(mlx, MLX_V1REG_IDB, MLX_V1_IDB_SACK);
    322   1.1        ad 	delay(1000000);
    323   1.1        ad 
    324   1.1        ad 	/* Wait up to 2 minutes for the bit to clear. */
    325   1.1        ad 	for (i = 120; i != 0; i--) {
    326   1.1        ad 		delay(1000000);
    327   1.1        ad 		if ((mlx_inb(mlx, MLX_V1REG_IDB) & MLX_V1_IDB_SACK) == 0)
    328   1.1        ad 			break;
    329   1.1        ad 	}
    330   1.1        ad 	if (i == 0)
    331   1.1        ad 		return (-1);
    332   1.1        ad 
    333   1.1        ad 	mlx_outb(mlx, MLX_V1REG_ODB, MLX_V1_ODB_RESET);
    334   1.1        ad 	mlx_outb(mlx, MLX_V1REG_IDB, MLX_V1_IDB_RESET);
    335   1.1        ad 
    336   1.1        ad 	/* Wait up to 5 seconds for the bit to clear... */
    337   1.1        ad 	for (i = 5; i != 0; i--) {
    338   1.1        ad 		delay(1000000);
    339   1.1        ad 		if ((mlx_inb(mlx, MLX_V1REG_IDB) & MLX_V1_IDB_RESET) == 0)
    340   1.1        ad 			break;
    341   1.1        ad 	}
    342   1.1        ad 	if (i == 0)
    343   1.1        ad 		return (-1);
    344   1.1        ad 
    345   1.1        ad 	/* Wait up to 3 seconds for the other bit to clear... */
    346   1.1        ad 	for (i = 5; i != 0; i--) {
    347   1.1        ad 		delay(1000000);
    348   1.1        ad 		if ((mlx_inb(mlx, MLX_V1REG_ODB) & MLX_V1_ODB_RESET) == 0)
    349   1.1        ad 			break;
    350   1.1        ad 	}
    351   1.1        ad 	if (i == 0)
    352   1.1        ad 		return (-1);
    353   1.1        ad 
    354   1.1        ad 	return (0);
    355   1.1        ad }
    356   1.1        ad #endif	/* MLX_RESET */
    357  1.26  pgoyette 
    358  1.26  pgoyette MODULE(MODULE_CLASS_DRIVER, mlx_eisa, "mlx");   /* No eisa module yet! */
    359  1.26  pgoyette 
    360  1.26  pgoyette #ifdef _MODULE
    361  1.26  pgoyette /*
    362  1.26  pgoyette  * XXX Don't allow ioconf.c to redefine the "struct cfdriver cac_cd"
    363  1.26  pgoyette  * XXX it will be defined in the common-code module
    364  1.26  pgoyette  */
    365  1.26  pgoyette #undef  CFDRIVER_DECL
    366  1.26  pgoyette #define CFDRIVER_DECL(name, class, attr)
    367  1.26  pgoyette #include "ioconf.c"
    368  1.26  pgoyette #endif
    369  1.26  pgoyette 
    370  1.26  pgoyette static int
    371  1.26  pgoyette mlx_eisa_modcmd(modcmd_t cmd, void *opaque)
    372  1.26  pgoyette {
    373  1.26  pgoyette 	int error = 0;
    374  1.26  pgoyette 
    375  1.26  pgoyette #ifdef _MODULE
    376  1.26  pgoyette 	switch (cmd) {
    377  1.26  pgoyette 	case MODULE_CMD_INIT:
    378  1.26  pgoyette 		/*
    379  1.26  pgoyette 		 * We skip over the first entry in cfdriver[] array
    380  1.26  pgoyette 		 * since the cfdriver is attached by the common
    381  1.26  pgoyette 		 * (non-attachment-specific) code.
    382  1.26  pgoyette 		 */
    383  1.26  pgoyette 		error = config_init_component(&cfdriver_ioconf_mlx_eisa[1],
    384  1.26  pgoyette 		    cfattach_ioconf_mlx_eisa, cfdata_ioconf_mlx_eisa);
    385  1.26  pgoyette 		break;
    386  1.26  pgoyette 	case MODULE_CMD_FINI:
    387  1.26  pgoyette 		error = config_fini_component(&cfdriver_ioconf_mlx_eisa[1],
    388  1.26  pgoyette 		    cfattach_ioconf_mlx_eisa, cfdata_ioconf_mlx_eisa);
    389  1.26  pgoyette 		break;
    390  1.26  pgoyette 	default:
    391  1.26  pgoyette 		error = ENOTTY;
    392  1.26  pgoyette 		break;
    393  1.26  pgoyette 	}
    394  1.26  pgoyette #endif
    395  1.26  pgoyette 
    396  1.26  pgoyette 	return error;
    397  1.26  pgoyette }
    398