mlx_eisa.c revision 1.10
1 /* $NetBSD: mlx_eisa.c,v 1.10 2002/09/30 21:04:26 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * EISA front-end for mlx(4) driver. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: mlx_eisa.c,v 1.10 2002/09/30 21:04:26 thorpej Exp $"); 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/device.h> 49 50 #include <machine/bus.h> 51 #include <machine/intr.h> 52 53 #include <dev/eisa/eisavar.h> 54 #include <dev/eisa/eisadevs.h> 55 56 #include <dev/ic/mlxreg.h> 57 #include <dev/ic/mlxio.h> 58 #include <dev/ic/mlxvar.h> 59 60 #define MLX_EISA_SLOT_OFFSET 0x0c80 61 #define MLX_EISA_IOSIZE (0x0ce0 - MLX_EISA_SLOT_OFFSET) 62 #define MLX_EISA_IOCONF1 (0x0cc1 - MLX_EISA_SLOT_OFFSET) 63 #define MLX_EISA_IOCONF2 (0x0cc3 - MLX_EISA_SLOT_OFFSET) 64 65 static void mlx_eisa_attach(struct device *, struct device *, void *); 66 static int mlx_eisa_match(struct device *, struct cfdata *, void *); 67 68 static int mlx_v1_submit(struct mlx_softc *, struct mlx_ccb *); 69 static int mlx_v1_findcomplete(struct mlx_softc *, u_int *, u_int *); 70 static void mlx_v1_intaction(struct mlx_softc *, int); 71 static int mlx_v1_fw_handshake(struct mlx_softc *, int *, int *, int *); 72 #ifdef MLX_RESET 73 static int mlx_v1_reset(struct mlx_softc *); 74 #endif 75 76 CFATTACH_DECL(mlx_eisa, sizeof(struct mlx_softc), 77 mlx_eisa_match, mlx_eisa_attach, NULL, NULL) 78 79 struct mlx_eisa_prod { 80 const char *mp_idstr; 81 int mp_nchan; 82 } static const mlx_eisa_prod[] = { 83 { "MLX0070", 1 }, 84 { "MLX0071", 3 }, 85 { "MLX0072", 3 }, 86 { "MLX0073", 2 }, 87 { "MLX0074", 1 }, 88 { "MLX0075", 3 }, 89 { "MLX0076", 2 }, 90 { "MLX0077", 1 }, 91 }; 92 93 static int 94 mlx_eisa_match(struct device *parent, struct cfdata *match, void *aux) 95 { 96 struct eisa_attach_args *ea; 97 int i; 98 99 ea = aux; 100 101 for (i = 0; i < sizeof(mlx_eisa_prod) / sizeof(mlx_eisa_prod[0]); i++) 102 if (strcmp(ea->ea_idstring, mlx_eisa_prod[i].mp_idstr) == 0) 103 return (1); 104 105 return (0); 106 } 107 108 static void 109 mlx_eisa_attach(struct device *parent, struct device *self, void *aux) 110 { 111 struct eisa_attach_args *ea; 112 bus_space_handle_t ioh; 113 eisa_chipset_tag_t ec; 114 eisa_intr_handle_t ih; 115 struct mlx_softc *mlx; 116 bus_space_tag_t iot; 117 const char *intrstr; 118 int irq, le, i; 119 120 ea = aux; 121 mlx = (struct mlx_softc *)self; 122 iot = ea->ea_iot; 123 ec = ea->ea_ec; 124 125 if (bus_space_map(iot, EISA_SLOT_ADDR(ea->ea_slot) + 126 MLX_EISA_SLOT_OFFSET, MLX_EISA_IOSIZE, 0, &ioh)) { 127 printf("can't map i/o space\n"); 128 return; 129 } 130 131 mlx->mlx_iot = iot; 132 mlx->mlx_ioh = ioh; 133 mlx->mlx_dmat = ea->ea_dmat; 134 135 /* 136 * Map and establish the interrupt. 137 */ 138 switch (bus_space_read_1(iot, ioh, MLX_EISA_IOCONF1) & 0xf0) { 139 case 0xa0: 140 irq = 11; 141 break; 142 case 0xc0: 143 irq = 12; 144 break; 145 case 0xe0: 146 irq = 14; 147 break; 148 case 0x80: 149 irq = 15; 150 break; 151 default: 152 printf("controller on invalid IRQ\n"); 153 return; 154 } 155 156 if (eisa_intr_map(ec, irq, &ih)) { 157 printf("can't map interrupt (%d)\n", irq); 158 return; 159 } 160 161 if ((bus_space_read_1(iot, ioh, MLX_EISA_IOCONF1) & 0x08) != 0) 162 le = IST_LEVEL; 163 else 164 le = IST_EDGE; 165 166 intrstr = eisa_intr_string(ec, ih); 167 mlx->mlx_ih = eisa_intr_establish(ec, ih, le, IPL_BIO, mlx_intr, mlx); 168 if (mlx->mlx_ih == NULL) { 169 printf("can't establish interrupt"); 170 if (intrstr != NULL) 171 printf(" at %s", intrstr); 172 printf("\n"); 173 return; 174 } 175 176 for (i = 0; i < sizeof(mlx_eisa_prod) / sizeof(mlx_eisa_prod[0]); i++) 177 if (strcmp(ea->ea_idstring, mlx_eisa_prod[i].mp_idstr) == 0) { 178 mlx->mlx_ci.ci_nchan = mlx_eisa_prod[i].mp_nchan; 179 break; 180 } 181 mlx->mlx_ci.ci_iftype = 1; 182 183 mlx->mlx_submit = mlx_v1_submit; 184 mlx->mlx_findcomplete = mlx_v1_findcomplete; 185 mlx->mlx_intaction = mlx_v1_intaction; 186 mlx->mlx_fw_handshake = mlx_v1_fw_handshake; 187 #ifdef MLX_RESET 188 mlx->mlx_reset = mlx_v1_reset; 189 #endif 190 191 printf(": Mylex RAID\n"); 192 mlx_init(mlx, intrstr); 193 } 194 195 /* 196 * ================= V1 interface linkage ================= 197 */ 198 199 /* 200 * Try to give (mc) to the controller. Returns 1 if successful, 0 on 201 * failure (the controller is not ready to take a command). 202 * 203 * Must be called at splbio or in a fashion that prevents reentry. 204 */ 205 static int 206 mlx_v1_submit(struct mlx_softc *mlx, struct mlx_ccb *mc) 207 { 208 209 /* Ready for our command? */ 210 if ((mlx_inb(mlx, MLX_V1REG_IDB) & MLX_V1_IDB_FULL) == 0) { 211 /* Copy mailbox data to window. */ 212 bus_space_write_region_1(mlx->mlx_iot, mlx->mlx_ioh, 213 MLX_V1REG_MAILBOX, mc->mc_mbox, 13); 214 bus_space_barrier(mlx->mlx_iot, mlx->mlx_ioh, 215 MLX_V1REG_MAILBOX, 13, 216 BUS_SPACE_BARRIER_WRITE); 217 218 /* Post command. */ 219 mlx_outb(mlx, MLX_V1REG_IDB, MLX_V1_IDB_FULL); 220 return (1); 221 } 222 223 return (0); 224 } 225 226 /* 227 * See if a command has been completed, if so acknowledge its completion and 228 * recover the slot number and status code. 229 * 230 * Must be called at splbio or in a fashion that prevents reentry. 231 */ 232 static int 233 mlx_v1_findcomplete(struct mlx_softc *mlx, u_int *slot, u_int *status) 234 { 235 236 /* Status available? */ 237 if ((mlx_inb(mlx, MLX_V1REG_ODB) & MLX_V1_ODB_SAVAIL) != 0) { 238 *slot = mlx_inb(mlx, MLX_V1REG_MAILBOX + 0x0d); 239 *status = mlx_inw(mlx, MLX_V1REG_MAILBOX + 0x0e); 240 241 /* Acknowledge completion. */ 242 mlx_outb(mlx, MLX_V1REG_ODB, MLX_V1_ODB_SAVAIL); 243 mlx_outb(mlx, MLX_V1REG_IDB, MLX_V1_IDB_SACK); 244 return (1); 245 } 246 247 return (0); 248 } 249 250 /* 251 * Enable/disable interrupts as requested. (No acknowledge required) 252 * 253 * Must be called at splbio or in a fashion that prevents reentry. 254 */ 255 static void 256 mlx_v1_intaction(struct mlx_softc *mlx, int action) 257 { 258 259 mlx_outb(mlx, MLX_V1REG_IE, action ? 1 : 0); 260 } 261 262 /* 263 * Poll for firmware error codes during controller initialisation. 264 * 265 * Returns 0 if initialisation is complete, 1 if still in progress but no 266 * error has been fetched, 2 if an error has been retrieved. 267 */ 268 static int 269 mlx_v1_fw_handshake(struct mlx_softc *mlx, int *error, int *param1, int *param2) 270 { 271 u_int8_t fwerror; 272 273 /* 274 * First time around, enable the IDB interrupt and clear any 275 * hardware completion status. 276 */ 277 if ((mlx->mlx_flags & MLXF_FW_INITTED) == 0) { 278 mlx_outb(mlx, MLX_V1REG_ODB_EN, 1); 279 DELAY(1000); 280 mlx_outb(mlx, MLX_V1REG_ODB, 1); 281 DELAY(1000); 282 mlx_outb(mlx, MLX_V1REG_IDB, MLX_V1_IDB_SACK); 283 DELAY(1000); 284 mlx->mlx_flags |= MLXF_FW_INITTED; 285 } 286 287 /* Init in progress? */ 288 if ((mlx_inb(mlx, MLX_V1REG_IDB) & MLX_V1_IDB_INIT_BUSY) == 0) 289 return (0); 290 291 /* Test error value. */ 292 fwerror = mlx_inb(mlx, MLX_V1REG_ODB); 293 294 if ((fwerror & MLX_V1_FWERROR_PEND) == 0) 295 return (1); 296 297 /* XXX Fetch status. */ 298 *error = fwerror & 0xf0; 299 *param1 = -1; 300 *param2 = -1; 301 302 /* Acknowledge. */ 303 mlx_outb(mlx, MLX_V1REG_ODB, fwerror); 304 305 return (2); 306 } 307 308 #ifdef MLX_RESET 309 /* 310 * Reset the controller. Return non-zero on failure. 311 */ 312 static int 313 mlx_v1_reset(struct mlx_softc *mlx) 314 { 315 int i; 316 317 mlx_outb(mlx, MLX_V1REG_IDB, MLX_V1_IDB_SACK); 318 delay(1000000); 319 320 /* Wait up to 2 minutes for the bit to clear. */ 321 for (i = 120; i != 0; i--) { 322 delay(1000000); 323 if ((mlx_inb(mlx, MLX_V1REG_IDB) & MLX_V1_IDB_SACK) == 0) 324 break; 325 } 326 if (i == 0) 327 return (-1); 328 329 mlx_outb(mlx, MLX_V1REG_ODB, MLX_V1_ODB_RESET); 330 mlx_outb(mlx, MLX_V1REG_IDB, MLX_V1_IDB_RESET); 331 332 /* Wait up to 5 seconds for the bit to clear... */ 333 for (i = 5; i != 0; i--) { 334 delay(1000000); 335 if ((mlx_inb(mlx, MLX_V1REG_IDB) & MLX_V1_IDB_RESET) == 0) 336 break; 337 } 338 if (i == 0) 339 return (-1); 340 341 /* Wait up to 3 seconds for the other bit to clear... */ 342 for (i = 5; i != 0; i--) { 343 delay(1000000); 344 if ((mlx_inb(mlx, MLX_V1REG_ODB) & MLX_V1_ODB_RESET) == 0) 345 break; 346 } 347 if (i == 0) 348 return (-1); 349 350 return (0); 351 } 352 #endif /* MLX_RESET */ 353
Indexes created Tue Sep 30 20:09:53 GMT 2025