mlx_eisa.c revision 1.15
1 /* $NetBSD: mlx_eisa.c,v 1.15 2006/03/29 06:32:36 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * EISA front-end for mlx(4) driver. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: mlx_eisa.c,v 1.15 2006/03/29 06:32:36 thorpej Exp $"); 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/device.h> 49 50 #include <machine/bus.h> 51 #include <machine/intr.h> 52 53 #include <dev/eisa/eisavar.h> 54 #include <dev/eisa/eisadevs.h> 55 56 #include <dev/ic/mlxreg.h> 57 #include <dev/ic/mlxio.h> 58 #include <dev/ic/mlxvar.h> 59 60 #define MLX_EISA_SLOT_OFFSET 0x0c80 61 #define MLX_EISA_IOSIZE (0x0ce0 - MLX_EISA_SLOT_OFFSET) 62 #define MLX_EISA_CFG01 (0x0cc0 - MLX_EISA_SLOT_OFFSET) 63 #define MLX_EISA_CFG02 (0x0cc1 - MLX_EISA_SLOT_OFFSET) 64 #define MLX_EISA_CFG03 (0x0cc3 - MLX_EISA_SLOT_OFFSET) 65 #define MLX_EISA_CFG04 (0x0c8d - MLX_EISA_SLOT_OFFSET) 66 #define MLX_EISA_CFG05 (0x0c90 - MLX_EISA_SLOT_OFFSET) 67 #define MLX_EISA_CFG06 (0x0c91 - MLX_EISA_SLOT_OFFSET) 68 #define MLX_EISA_CFG07 (0x0c92 - MLX_EISA_SLOT_OFFSET) 69 #define MLX_EISA_CFG08 (0x0c93 - MLX_EISA_SLOT_OFFSET) 70 #define MLX_EISA_CFG09 (0x0c94 - MLX_EISA_SLOT_OFFSET) 71 #define MLX_EISA_CFG10 (0x0c95 - MLX_EISA_SLOT_OFFSET) 72 73 static void mlx_eisa_attach(struct device *, struct device *, void *); 74 static int mlx_eisa_match(struct device *, struct cfdata *, void *); 75 76 static int mlx_v1_submit(struct mlx_softc *, struct mlx_ccb *); 77 static int mlx_v1_findcomplete(struct mlx_softc *, u_int *, u_int *); 78 static void mlx_v1_intaction(struct mlx_softc *, int); 79 static int mlx_v1_fw_handshake(struct mlx_softc *, int *, int *, int *); 80 #ifdef MLX_RESET 81 static int mlx_v1_reset(struct mlx_softc *); 82 #endif 83 84 CFATTACH_DECL(mlx_eisa, sizeof(struct mlx_softc), 85 mlx_eisa_match, mlx_eisa_attach, NULL, NULL); 86 87 struct mlx_eisa_prod { 88 const char *mp_idstr; 89 int mp_nchan; 90 } static const mlx_eisa_prod[] = { 91 { "MLX0070", 1 }, 92 { "MLX0071", 3 }, 93 { "MLX0072", 3 }, 94 { "MLX0073", 2 }, 95 { "MLX0074", 1 }, 96 { "MLX0075", 3 }, 97 { "MLX0076", 2 }, 98 { "MLX0077", 1 }, 99 }; 100 101 static int 102 mlx_eisa_match(struct device *parent, struct cfdata *match, void *aux) 103 { 104 struct eisa_attach_args *ea; 105 int i; 106 107 ea = aux; 108 109 for (i = 0; i < sizeof(mlx_eisa_prod) / sizeof(mlx_eisa_prod[0]); i++) 110 if (strcmp(ea->ea_idstring, mlx_eisa_prod[i].mp_idstr) == 0) 111 return (1); 112 113 return (0); 114 } 115 116 static void 117 mlx_eisa_attach(struct device *parent, struct device *self, void *aux) 118 { 119 struct eisa_attach_args *ea; 120 bus_space_handle_t ioh; 121 eisa_chipset_tag_t ec; 122 eisa_intr_handle_t ih; 123 struct mlx_softc *mlx; 124 bus_space_tag_t iot; 125 const char *intrstr; 126 int irq, i, icfg; 127 128 ea = aux; 129 mlx = device_private(self); 130 iot = ea->ea_iot; 131 ec = ea->ea_ec; 132 133 if (bus_space_map(iot, EISA_SLOT_ADDR(ea->ea_slot) + 134 MLX_EISA_SLOT_OFFSET, MLX_EISA_IOSIZE, 0, &ioh)) { 135 printf("can't map i/o space\n"); 136 return; 137 } 138 139 mlx->mlx_iot = iot; 140 mlx->mlx_ioh = ioh; 141 mlx->mlx_dmat = ea->ea_dmat; 142 143 /* 144 * Map and establish the interrupt. 145 */ 146 icfg = bus_space_read_1(iot, ioh, MLX_EISA_CFG03); 147 148 switch (icfg & 0xf0) { 149 case 0xa0: 150 irq = 11; 151 break; 152 case 0xc0: 153 irq = 12; 154 break; 155 case 0xe0: 156 irq = 14; 157 break; 158 case 0x80: 159 irq = 15; 160 break; 161 default: 162 printf("controller on invalid IRQ\n"); 163 return; 164 } 165 166 if (eisa_intr_map(ec, irq, &ih)) { 167 printf("can't map interrupt (%d)\n", irq); 168 return; 169 } 170 171 intrstr = eisa_intr_string(ec, ih); 172 mlx->mlx_ih = eisa_intr_establish(ec, ih, 173 ((icfg & 0x08) != 0 ? IST_LEVEL : IST_EDGE), 174 IPL_BIO, mlx_intr, mlx); 175 if (mlx->mlx_ih == NULL) { 176 printf("can't establish interrupt"); 177 if (intrstr != NULL) 178 printf(" at %s", intrstr); 179 printf("\n"); 180 return; 181 } 182 183 for (i = 0; i < sizeof(mlx_eisa_prod) / sizeof(mlx_eisa_prod[0]); i++) 184 if (strcmp(ea->ea_idstring, mlx_eisa_prod[i].mp_idstr) == 0) { 185 mlx->mlx_ci.ci_nchan = mlx_eisa_prod[i].mp_nchan; 186 break; 187 } 188 mlx->mlx_ci.ci_iftype = 1; 189 190 mlx->mlx_submit = mlx_v1_submit; 191 mlx->mlx_findcomplete = mlx_v1_findcomplete; 192 mlx->mlx_intaction = mlx_v1_intaction; 193 mlx->mlx_fw_handshake = mlx_v1_fw_handshake; 194 #ifdef MLX_RESET 195 mlx->mlx_reset = mlx_v1_reset; 196 #endif 197 198 printf(": Mylex RAID\n"); 199 mlx_init(mlx, intrstr); 200 } 201 202 /* 203 * ================= V1 interface linkage ================= 204 */ 205 206 /* 207 * Try to give (mc) to the controller. Returns 1 if successful, 0 on 208 * failure (the controller is not ready to take a command). 209 * 210 * Must be called at splbio or in a fashion that prevents reentry. 211 */ 212 static int 213 mlx_v1_submit(struct mlx_softc *mlx, struct mlx_ccb *mc) 214 { 215 216 /* Ready for our command? */ 217 if ((mlx_inb(mlx, MLX_V1REG_IDB) & MLX_V1_IDB_FULL) == 0) { 218 /* Copy mailbox data to window. */ 219 bus_space_write_region_1(mlx->mlx_iot, mlx->mlx_ioh, 220 MLX_V1REG_MAILBOX, mc->mc_mbox, 13); 221 bus_space_barrier(mlx->mlx_iot, mlx->mlx_ioh, 222 MLX_V1REG_MAILBOX, 13, 223 BUS_SPACE_BARRIER_WRITE); 224 225 /* Post command. */ 226 mlx_outb(mlx, MLX_V1REG_IDB, MLX_V1_IDB_FULL); 227 return (1); 228 } 229 230 return (0); 231 } 232 233 /* 234 * See if a command has been completed, if so acknowledge its completion and 235 * recover the slot number and status code. 236 * 237 * Must be called at splbio or in a fashion that prevents reentry. 238 */ 239 static int 240 mlx_v1_findcomplete(struct mlx_softc *mlx, u_int *slot, u_int *status) 241 { 242 243 /* Status available? */ 244 if ((mlx_inb(mlx, MLX_V1REG_ODB) & MLX_V1_ODB_SAVAIL) != 0) { 245 *slot = mlx_inb(mlx, MLX_V1REG_MAILBOX + 0x0d); 246 *status = mlx_inw(mlx, MLX_V1REG_MAILBOX + 0x0e); 247 248 /* Acknowledge completion. */ 249 mlx_outb(mlx, MLX_V1REG_ODB, MLX_V1_ODB_SAVAIL); 250 mlx_outb(mlx, MLX_V1REG_IDB, MLX_V1_IDB_SACK); 251 return (1); 252 } 253 254 return (0); 255 } 256 257 /* 258 * Enable/disable interrupts as requested. (No acknowledge required) 259 * 260 * Must be called at splbio or in a fashion that prevents reentry. 261 */ 262 static void 263 mlx_v1_intaction(struct mlx_softc *mlx, int action) 264 { 265 266 mlx_outb(mlx, MLX_V1REG_IE, action ? 1 : 0); 267 } 268 269 /* 270 * Poll for firmware error codes during controller initialisation. 271 * 272 * Returns 0 if initialisation is complete, 1 if still in progress but no 273 * error has been fetched, 2 if an error has been retrieved. 274 */ 275 static int 276 mlx_v1_fw_handshake(struct mlx_softc *mlx, int *error, int *param1, int *param2) 277 { 278 u_int8_t fwerror; 279 280 /* 281 * First time around, enable the IDB interrupt and clear any 282 * hardware completion status. 283 */ 284 if ((mlx->mlx_flags & MLXF_FW_INITTED) == 0) { 285 mlx_outb(mlx, MLX_V1REG_ODB_EN, 1); 286 DELAY(1000); 287 mlx_outb(mlx, MLX_V1REG_ODB, 1); 288 DELAY(1000); 289 mlx_outb(mlx, MLX_V1REG_IDB, MLX_V1_IDB_SACK); 290 DELAY(1000); 291 mlx->mlx_flags |= MLXF_FW_INITTED; 292 } 293 294 /* Init in progress? */ 295 if ((mlx_inb(mlx, MLX_V1REG_IDB) & MLX_V1_IDB_INIT_BUSY) == 0) 296 return (0); 297 298 /* Test error value. */ 299 fwerror = mlx_inb(mlx, MLX_V1REG_ODB); 300 301 if ((fwerror & MLX_V1_FWERROR_PEND) == 0) 302 return (1); 303 304 /* XXX Fetch status. */ 305 *error = fwerror & 0xf0; 306 *param1 = -1; 307 *param2 = -1; 308 309 /* Acknowledge. */ 310 mlx_outb(mlx, MLX_V1REG_ODB, fwerror); 311 312 return (2); 313 } 314 315 #ifdef MLX_RESET 316 /* 317 * Reset the controller. Return non-zero on failure. 318 */ 319 static int 320 mlx_v1_reset(struct mlx_softc *mlx) 321 { 322 int i; 323 324 mlx_outb(mlx, MLX_V1REG_IDB, MLX_V1_IDB_SACK); 325 delay(1000000); 326 327 /* Wait up to 2 minutes for the bit to clear. */ 328 for (i = 120; i != 0; i--) { 329 delay(1000000); 330 if ((mlx_inb(mlx, MLX_V1REG_IDB) & MLX_V1_IDB_SACK) == 0) 331 break; 332 } 333 if (i == 0) 334 return (-1); 335 336 mlx_outb(mlx, MLX_V1REG_ODB, MLX_V1_ODB_RESET); 337 mlx_outb(mlx, MLX_V1REG_IDB, MLX_V1_IDB_RESET); 338 339 /* Wait up to 5 seconds for the bit to clear... */ 340 for (i = 5; i != 0; i--) { 341 delay(1000000); 342 if ((mlx_inb(mlx, MLX_V1REG_IDB) & MLX_V1_IDB_RESET) == 0) 343 break; 344 } 345 if (i == 0) 346 return (-1); 347 348 /* Wait up to 3 seconds for the other bit to clear... */ 349 for (i = 5; i != 0; i--) { 350 delay(1000000); 351 if ((mlx_inb(mlx, MLX_V1REG_ODB) & MLX_V1_ODB_RESET) == 0) 352 break; 353 } 354 if (i == 0) 355 return (-1); 356 357 return (0); 358 } 359 #endif /* MLX_RESET */ 360
Indexes created Tue Sep 30 11:09:46 GMT 2025