mlx_eisa.c revision 1.23
1 /* $NetBSD: mlx_eisa.c,v 1.23 2012/10/27 17:18:16 chs Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * EISA front-end for mlx(4) driver. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: mlx_eisa.c,v 1.23 2012/10/27 17:18:16 chs Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/device.h> 42 43 #include <sys/bus.h> 44 #include <sys/intr.h> 45 46 #include <dev/eisa/eisavar.h> 47 #include <dev/eisa/eisadevs.h> 48 49 #include <dev/ic/mlxreg.h> 50 #include <dev/ic/mlxio.h> 51 #include <dev/ic/mlxvar.h> 52 53 #define MLX_EISA_SLOT_OFFSET 0x0c80 54 #define MLX_EISA_IOSIZE (0x0ce0 - MLX_EISA_SLOT_OFFSET) 55 #define MLX_EISA_CFG01 (0x0cc0 - MLX_EISA_SLOT_OFFSET) 56 #define MLX_EISA_CFG02 (0x0cc1 - MLX_EISA_SLOT_OFFSET) 57 #define MLX_EISA_CFG03 (0x0cc3 - MLX_EISA_SLOT_OFFSET) 58 #define MLX_EISA_CFG04 (0x0c8d - MLX_EISA_SLOT_OFFSET) 59 #define MLX_EISA_CFG05 (0x0c90 - MLX_EISA_SLOT_OFFSET) 60 #define MLX_EISA_CFG06 (0x0c91 - MLX_EISA_SLOT_OFFSET) 61 #define MLX_EISA_CFG07 (0x0c92 - MLX_EISA_SLOT_OFFSET) 62 #define MLX_EISA_CFG08 (0x0c93 - MLX_EISA_SLOT_OFFSET) 63 #define MLX_EISA_CFG09 (0x0c94 - MLX_EISA_SLOT_OFFSET) 64 #define MLX_EISA_CFG10 (0x0c95 - MLX_EISA_SLOT_OFFSET) 65 66 static void mlx_eisa_attach(device_t, device_t, void *); 67 static int mlx_eisa_match(device_t, cfdata_t, void *); 68 69 static int mlx_v1_submit(struct mlx_softc *, struct mlx_ccb *); 70 static int mlx_v1_findcomplete(struct mlx_softc *, u_int *, u_int *); 71 static void mlx_v1_intaction(struct mlx_softc *, int); 72 static int mlx_v1_fw_handshake(struct mlx_softc *, int *, int *, int *); 73 #ifdef MLX_RESET 74 static int mlx_v1_reset(struct mlx_softc *); 75 #endif 76 77 CFATTACH_DECL_NEW(mlx_eisa, sizeof(struct mlx_softc), 78 mlx_eisa_match, mlx_eisa_attach, NULL, NULL); 79 80 static struct mlx_eisa_prod { 81 const char *mp_idstr; 82 int mp_nchan; 83 } const mlx_eisa_prod[] = { 84 { "MLX0070", 1 }, 85 { "MLX0071", 3 }, 86 { "MLX0072", 3 }, 87 { "MLX0073", 2 }, 88 { "MLX0074", 1 }, 89 { "MLX0075", 3 }, 90 { "MLX0076", 2 }, 91 { "MLX0077", 1 }, 92 }; 93 94 static int 95 mlx_eisa_match(device_t parent, cfdata_t match, 96 void *aux) 97 { 98 struct eisa_attach_args *ea; 99 int i; 100 101 ea = aux; 102 103 for (i = 0; i < sizeof(mlx_eisa_prod) / sizeof(mlx_eisa_prod[0]); i++) 104 if (strcmp(ea->ea_idstring, mlx_eisa_prod[i].mp_idstr) == 0) 105 return (1); 106 107 return (0); 108 } 109 110 static void 111 mlx_eisa_attach(device_t parent, device_t self, void *aux) 112 { 113 struct eisa_attach_args *ea; 114 bus_space_handle_t ioh; 115 eisa_chipset_tag_t ec; 116 eisa_intr_handle_t ih; 117 struct mlx_softc *mlx; 118 bus_space_tag_t iot; 119 const char *intrstr; 120 int irq, i, icfg; 121 122 ea = aux; 123 mlx = device_private(self); 124 iot = ea->ea_iot; 125 ec = ea->ea_ec; 126 127 if (bus_space_map(iot, EISA_SLOT_ADDR(ea->ea_slot) + 128 MLX_EISA_SLOT_OFFSET, MLX_EISA_IOSIZE, 0, &ioh)) { 129 printf("can't map i/o space\n"); 130 return; 131 } 132 133 mlx->mlx_dv = self; 134 mlx->mlx_iot = iot; 135 mlx->mlx_ioh = ioh; 136 mlx->mlx_dmat = ea->ea_dmat; 137 138 /* 139 * Map and establish the interrupt. 140 */ 141 icfg = bus_space_read_1(iot, ioh, MLX_EISA_CFG03); 142 143 switch (icfg & 0xf0) { 144 case 0xa0: 145 irq = 11; 146 break; 147 case 0xc0: 148 irq = 12; 149 break; 150 case 0xe0: 151 irq = 14; 152 break; 153 case 0x80: 154 irq = 15; 155 break; 156 default: 157 printf("controller on invalid IRQ\n"); 158 return; 159 } 160 161 if (eisa_intr_map(ec, irq, &ih)) { 162 printf("can't map interrupt (%d)\n", irq); 163 return; 164 } 165 166 intrstr = eisa_intr_string(ec, ih); 167 mlx->mlx_ih = eisa_intr_establish(ec, ih, 168 ((icfg & 0x08) != 0 ? IST_LEVEL : IST_EDGE), 169 IPL_BIO, mlx_intr, mlx); 170 if (mlx->mlx_ih == NULL) { 171 printf("can't establish interrupt"); 172 if (intrstr != NULL) 173 printf(" at %s", intrstr); 174 printf("\n"); 175 return; 176 } 177 178 for (i = 0; i < sizeof(mlx_eisa_prod) / sizeof(mlx_eisa_prod[0]); i++) 179 if (strcmp(ea->ea_idstring, mlx_eisa_prod[i].mp_idstr) == 0) { 180 mlx->mlx_ci.ci_nchan = mlx_eisa_prod[i].mp_nchan; 181 break; 182 } 183 mlx->mlx_ci.ci_iftype = 1; 184 185 mlx->mlx_submit = mlx_v1_submit; 186 mlx->mlx_findcomplete = mlx_v1_findcomplete; 187 mlx->mlx_intaction = mlx_v1_intaction; 188 mlx->mlx_fw_handshake = mlx_v1_fw_handshake; 189 #ifdef MLX_RESET 190 mlx->mlx_reset = mlx_v1_reset; 191 #endif 192 193 printf(": Mylex RAID\n"); 194 mlx_init(mlx, intrstr); 195 } 196 197 /* 198 * ================= V1 interface linkage ================= 199 */ 200 201 /* 202 * Try to give (mc) to the controller. Returns 1 if successful, 0 on 203 * failure (the controller is not ready to take a command). 204 * 205 * Must be called at splbio or in a fashion that prevents reentry. 206 */ 207 static int 208 mlx_v1_submit(struct mlx_softc *mlx, struct mlx_ccb *mc) 209 { 210 211 /* Ready for our command? */ 212 if ((mlx_inb(mlx, MLX_V1REG_IDB) & MLX_V1_IDB_FULL) == 0) { 213 /* Copy mailbox data to window. */ 214 bus_space_write_region_1(mlx->mlx_iot, mlx->mlx_ioh, 215 MLX_V1REG_MAILBOX, mc->mc_mbox, 13); 216 bus_space_barrier(mlx->mlx_iot, mlx->mlx_ioh, 217 MLX_V1REG_MAILBOX, 13, 218 BUS_SPACE_BARRIER_WRITE); 219 220 /* Post command. */ 221 mlx_outb(mlx, MLX_V1REG_IDB, MLX_V1_IDB_FULL); 222 return (1); 223 } 224 225 return (0); 226 } 227 228 /* 229 * See if a command has been completed, if so acknowledge its completion and 230 * recover the slot number and status code. 231 * 232 * Must be called at splbio or in a fashion that prevents reentry. 233 */ 234 static int 235 mlx_v1_findcomplete(struct mlx_softc *mlx, u_int *slot, u_int *status) 236 { 237 238 /* Status available? */ 239 if ((mlx_inb(mlx, MLX_V1REG_ODB) & MLX_V1_ODB_SAVAIL) != 0) { 240 *slot = mlx_inb(mlx, MLX_V1REG_MAILBOX + 0x0d); 241 *status = mlx_inw(mlx, MLX_V1REG_MAILBOX + 0x0e); 242 243 /* Acknowledge completion. */ 244 mlx_outb(mlx, MLX_V1REG_ODB, MLX_V1_ODB_SAVAIL); 245 mlx_outb(mlx, MLX_V1REG_IDB, MLX_V1_IDB_SACK); 246 return (1); 247 } 248 249 return (0); 250 } 251 252 /* 253 * Enable/disable interrupts as requested. (No acknowledge required) 254 * 255 * Must be called at splbio or in a fashion that prevents reentry. 256 */ 257 static void 258 mlx_v1_intaction(struct mlx_softc *mlx, int action) 259 { 260 261 mlx_outb(mlx, MLX_V1REG_IE, action ? 1 : 0); 262 } 263 264 /* 265 * Poll for firmware error codes during controller initialisation. 266 * 267 * Returns 0 if initialisation is complete, 1 if still in progress but no 268 * error has been fetched, 2 if an error has been retrieved. 269 */ 270 static int 271 mlx_v1_fw_handshake(struct mlx_softc *mlx, int *error, int *param1, int *param2) 272 { 273 u_int8_t fwerror; 274 275 /* 276 * First time around, enable the IDB interrupt and clear any 277 * hardware completion status. 278 */ 279 if ((mlx->mlx_flags & MLXF_FW_INITTED) == 0) { 280 mlx_outb(mlx, MLX_V1REG_ODB_EN, 1); 281 DELAY(1000); 282 mlx_outb(mlx, MLX_V1REG_ODB, 1); 283 DELAY(1000); 284 mlx_outb(mlx, MLX_V1REG_IDB, MLX_V1_IDB_SACK); 285 DELAY(1000); 286 mlx->mlx_flags |= MLXF_FW_INITTED; 287 } 288 289 /* Init in progress? */ 290 if ((mlx_inb(mlx, MLX_V1REG_IDB) & MLX_V1_IDB_INIT_BUSY) == 0) 291 return (0); 292 293 /* Test error value. */ 294 fwerror = mlx_inb(mlx, MLX_V1REG_ODB); 295 296 if ((fwerror & MLX_V1_FWERROR_PEND) == 0) 297 return (1); 298 299 /* XXX Fetch status. */ 300 *error = fwerror & 0xf0; 301 *param1 = -1; 302 *param2 = -1; 303 304 /* Acknowledge. */ 305 mlx_outb(mlx, MLX_V1REG_ODB, fwerror); 306 307 return (2); 308 } 309 310 #ifdef MLX_RESET 311 /* 312 * Reset the controller. Return non-zero on failure. 313 */ 314 static int 315 mlx_v1_reset(struct mlx_softc *mlx) 316 { 317 int i; 318 319 mlx_outb(mlx, MLX_V1REG_IDB, MLX_V1_IDB_SACK); 320 delay(1000000); 321 322 /* Wait up to 2 minutes for the bit to clear. */ 323 for (i = 120; i != 0; i--) { 324 delay(1000000); 325 if ((mlx_inb(mlx, MLX_V1REG_IDB) & MLX_V1_IDB_SACK) == 0) 326 break; 327 } 328 if (i == 0) 329 return (-1); 330 331 mlx_outb(mlx, MLX_V1REG_ODB, MLX_V1_ODB_RESET); 332 mlx_outb(mlx, MLX_V1REG_IDB, MLX_V1_IDB_RESET); 333 334 /* Wait up to 5 seconds for the bit to clear... */ 335 for (i = 5; i != 0; i--) { 336 delay(1000000); 337 if ((mlx_inb(mlx, MLX_V1REG_IDB) & MLX_V1_IDB_RESET) == 0) 338 break; 339 } 340 if (i == 0) 341 return (-1); 342 343 /* Wait up to 3 seconds for the other bit to clear... */ 344 for (i = 5; i != 0; i--) { 345 delay(1000000); 346 if ((mlx_inb(mlx, MLX_V1REG_ODB) & MLX_V1_ODB_RESET) == 0) 347 break; 348 } 349 if (i == 0) 350 return (-1); 351 352 return (0); 353 } 354 #endif /* MLX_RESET */ 355
Indexes created Tue Sep 30 20:09:53 GMT 2025