mlx_eisa.c revision 1.24
1 /* $NetBSD: mlx_eisa.c,v 1.24 2014/03/29 19:28:24 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * EISA front-end for mlx(4) driver. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: mlx_eisa.c,v 1.24 2014/03/29 19:28:24 christos Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/device.h> 42 43 #include <sys/bus.h> 44 #include <sys/intr.h> 45 46 #include <dev/eisa/eisavar.h> 47 #include <dev/eisa/eisadevs.h> 48 49 #include <dev/ic/mlxreg.h> 50 #include <dev/ic/mlxio.h> 51 #include <dev/ic/mlxvar.h> 52 53 #define MLX_EISA_SLOT_OFFSET 0x0c80 54 #define MLX_EISA_IOSIZE (0x0ce0 - MLX_EISA_SLOT_OFFSET) 55 #define MLX_EISA_CFG01 (0x0cc0 - MLX_EISA_SLOT_OFFSET) 56 #define MLX_EISA_CFG02 (0x0cc1 - MLX_EISA_SLOT_OFFSET) 57 #define MLX_EISA_CFG03 (0x0cc3 - MLX_EISA_SLOT_OFFSET) 58 #define MLX_EISA_CFG04 (0x0c8d - MLX_EISA_SLOT_OFFSET) 59 #define MLX_EISA_CFG05 (0x0c90 - MLX_EISA_SLOT_OFFSET) 60 #define MLX_EISA_CFG06 (0x0c91 - MLX_EISA_SLOT_OFFSET) 61 #define MLX_EISA_CFG07 (0x0c92 - MLX_EISA_SLOT_OFFSET) 62 #define MLX_EISA_CFG08 (0x0c93 - MLX_EISA_SLOT_OFFSET) 63 #define MLX_EISA_CFG09 (0x0c94 - MLX_EISA_SLOT_OFFSET) 64 #define MLX_EISA_CFG10 (0x0c95 - MLX_EISA_SLOT_OFFSET) 65 66 static void mlx_eisa_attach(device_t, device_t, void *); 67 static int mlx_eisa_match(device_t, cfdata_t, void *); 68 69 static int mlx_v1_submit(struct mlx_softc *, struct mlx_ccb *); 70 static int mlx_v1_findcomplete(struct mlx_softc *, u_int *, u_int *); 71 static void mlx_v1_intaction(struct mlx_softc *, int); 72 static int mlx_v1_fw_handshake(struct mlx_softc *, int *, int *, int *); 73 #ifdef MLX_RESET 74 static int mlx_v1_reset(struct mlx_softc *); 75 #endif 76 77 CFATTACH_DECL_NEW(mlx_eisa, sizeof(struct mlx_softc), 78 mlx_eisa_match, mlx_eisa_attach, NULL, NULL); 79 80 static struct mlx_eisa_prod { 81 const char *mp_idstr; 82 int mp_nchan; 83 } const mlx_eisa_prod[] = { 84 { "MLX0070", 1 }, 85 { "MLX0071", 3 }, 86 { "MLX0072", 3 }, 87 { "MLX0073", 2 }, 88 { "MLX0074", 1 }, 89 { "MLX0075", 3 }, 90 { "MLX0076", 2 }, 91 { "MLX0077", 1 }, 92 }; 93 94 static int 95 mlx_eisa_match(device_t parent, cfdata_t match, 96 void *aux) 97 { 98 struct eisa_attach_args *ea; 99 int i; 100 101 ea = aux; 102 103 for (i = 0; i < sizeof(mlx_eisa_prod) / sizeof(mlx_eisa_prod[0]); i++) 104 if (strcmp(ea->ea_idstring, mlx_eisa_prod[i].mp_idstr) == 0) 105 return (1); 106 107 return (0); 108 } 109 110 static void 111 mlx_eisa_attach(device_t parent, device_t self, void *aux) 112 { 113 struct eisa_attach_args *ea; 114 bus_space_handle_t ioh; 115 eisa_chipset_tag_t ec; 116 eisa_intr_handle_t ih; 117 struct mlx_softc *mlx; 118 bus_space_tag_t iot; 119 const char *intrstr; 120 int irq, i, icfg; 121 char intrbuf[EISA_INTRSTR_LEN]; 122 123 ea = aux; 124 mlx = device_private(self); 125 iot = ea->ea_iot; 126 ec = ea->ea_ec; 127 128 if (bus_space_map(iot, EISA_SLOT_ADDR(ea->ea_slot) + 129 MLX_EISA_SLOT_OFFSET, MLX_EISA_IOSIZE, 0, &ioh)) { 130 printf("can't map i/o space\n"); 131 return; 132 } 133 134 mlx->mlx_dv = self; 135 mlx->mlx_iot = iot; 136 mlx->mlx_ioh = ioh; 137 mlx->mlx_dmat = ea->ea_dmat; 138 139 /* 140 * Map and establish the interrupt. 141 */ 142 icfg = bus_space_read_1(iot, ioh, MLX_EISA_CFG03); 143 144 switch (icfg & 0xf0) { 145 case 0xa0: 146 irq = 11; 147 break; 148 case 0xc0: 149 irq = 12; 150 break; 151 case 0xe0: 152 irq = 14; 153 break; 154 case 0x80: 155 irq = 15; 156 break; 157 default: 158 printf("controller on invalid IRQ\n"); 159 return; 160 } 161 162 if (eisa_intr_map(ec, irq, &ih)) { 163 printf("can't map interrupt (%d)\n", irq); 164 return; 165 } 166 167 intrstr = eisa_intr_string(ec, ih, intrbuf, sizeof(intrbuf)); 168 mlx->mlx_ih = eisa_intr_establish(ec, ih, 169 ((icfg & 0x08) != 0 ? IST_LEVEL : IST_EDGE), 170 IPL_BIO, mlx_intr, mlx); 171 if (mlx->mlx_ih == NULL) { 172 printf("can't establish interrupt"); 173 if (intrstr != NULL) 174 printf(" at %s", intrstr); 175 printf("\n"); 176 return; 177 } 178 179 for (i = 0; i < sizeof(mlx_eisa_prod) / sizeof(mlx_eisa_prod[0]); i++) 180 if (strcmp(ea->ea_idstring, mlx_eisa_prod[i].mp_idstr) == 0) { 181 mlx->mlx_ci.ci_nchan = mlx_eisa_prod[i].mp_nchan; 182 break; 183 } 184 mlx->mlx_ci.ci_iftype = 1; 185 186 mlx->mlx_submit = mlx_v1_submit; 187 mlx->mlx_findcomplete = mlx_v1_findcomplete; 188 mlx->mlx_intaction = mlx_v1_intaction; 189 mlx->mlx_fw_handshake = mlx_v1_fw_handshake; 190 #ifdef MLX_RESET 191 mlx->mlx_reset = mlx_v1_reset; 192 #endif 193 194 printf(": Mylex RAID\n"); 195 mlx_init(mlx, intrstr); 196 } 197 198 /* 199 * ================= V1 interface linkage ================= 200 */ 201 202 /* 203 * Try to give (mc) to the controller. Returns 1 if successful, 0 on 204 * failure (the controller is not ready to take a command). 205 * 206 * Must be called at splbio or in a fashion that prevents reentry. 207 */ 208 static int 209 mlx_v1_submit(struct mlx_softc *mlx, struct mlx_ccb *mc) 210 { 211 212 /* Ready for our command? */ 213 if ((mlx_inb(mlx, MLX_V1REG_IDB) & MLX_V1_IDB_FULL) == 0) { 214 /* Copy mailbox data to window. */ 215 bus_space_write_region_1(mlx->mlx_iot, mlx->mlx_ioh, 216 MLX_V1REG_MAILBOX, mc->mc_mbox, 13); 217 bus_space_barrier(mlx->mlx_iot, mlx->mlx_ioh, 218 MLX_V1REG_MAILBOX, 13, 219 BUS_SPACE_BARRIER_WRITE); 220 221 /* Post command. */ 222 mlx_outb(mlx, MLX_V1REG_IDB, MLX_V1_IDB_FULL); 223 return (1); 224 } 225 226 return (0); 227 } 228 229 /* 230 * See if a command has been completed, if so acknowledge its completion and 231 * recover the slot number and status code. 232 * 233 * Must be called at splbio or in a fashion that prevents reentry. 234 */ 235 static int 236 mlx_v1_findcomplete(struct mlx_softc *mlx, u_int *slot, u_int *status) 237 { 238 239 /* Status available? */ 240 if ((mlx_inb(mlx, MLX_V1REG_ODB) & MLX_V1_ODB_SAVAIL) != 0) { 241 *slot = mlx_inb(mlx, MLX_V1REG_MAILBOX + 0x0d); 242 *status = mlx_inw(mlx, MLX_V1REG_MAILBOX + 0x0e); 243 244 /* Acknowledge completion. */ 245 mlx_outb(mlx, MLX_V1REG_ODB, MLX_V1_ODB_SAVAIL); 246 mlx_outb(mlx, MLX_V1REG_IDB, MLX_V1_IDB_SACK); 247 return (1); 248 } 249 250 return (0); 251 } 252 253 /* 254 * Enable/disable interrupts as requested. (No acknowledge required) 255 * 256 * Must be called at splbio or in a fashion that prevents reentry. 257 */ 258 static void 259 mlx_v1_intaction(struct mlx_softc *mlx, int action) 260 { 261 262 mlx_outb(mlx, MLX_V1REG_IE, action ? 1 : 0); 263 } 264 265 /* 266 * Poll for firmware error codes during controller initialisation. 267 * 268 * Returns 0 if initialisation is complete, 1 if still in progress but no 269 * error has been fetched, 2 if an error has been retrieved. 270 */ 271 static int 272 mlx_v1_fw_handshake(struct mlx_softc *mlx, int *error, int *param1, int *param2) 273 { 274 u_int8_t fwerror; 275 276 /* 277 * First time around, enable the IDB interrupt and clear any 278 * hardware completion status. 279 */ 280 if ((mlx->mlx_flags & MLXF_FW_INITTED) == 0) { 281 mlx_outb(mlx, MLX_V1REG_ODB_EN, 1); 282 DELAY(1000); 283 mlx_outb(mlx, MLX_V1REG_ODB, 1); 284 DELAY(1000); 285 mlx_outb(mlx, MLX_V1REG_IDB, MLX_V1_IDB_SACK); 286 DELAY(1000); 287 mlx->mlx_flags |= MLXF_FW_INITTED; 288 } 289 290 /* Init in progress? */ 291 if ((mlx_inb(mlx, MLX_V1REG_IDB) & MLX_V1_IDB_INIT_BUSY) == 0) 292 return (0); 293 294 /* Test error value. */ 295 fwerror = mlx_inb(mlx, MLX_V1REG_ODB); 296 297 if ((fwerror & MLX_V1_FWERROR_PEND) == 0) 298 return (1); 299 300 /* XXX Fetch status. */ 301 *error = fwerror & 0xf0; 302 *param1 = -1; 303 *param2 = -1; 304 305 /* Acknowledge. */ 306 mlx_outb(mlx, MLX_V1REG_ODB, fwerror); 307 308 return (2); 309 } 310 311 #ifdef MLX_RESET 312 /* 313 * Reset the controller. Return non-zero on failure. 314 */ 315 static int 316 mlx_v1_reset(struct mlx_softc *mlx) 317 { 318 int i; 319 320 mlx_outb(mlx, MLX_V1REG_IDB, MLX_V1_IDB_SACK); 321 delay(1000000); 322 323 /* Wait up to 2 minutes for the bit to clear. */ 324 for (i = 120; i != 0; i--) { 325 delay(1000000); 326 if ((mlx_inb(mlx, MLX_V1REG_IDB) & MLX_V1_IDB_SACK) == 0) 327 break; 328 } 329 if (i == 0) 330 return (-1); 331 332 mlx_outb(mlx, MLX_V1REG_ODB, MLX_V1_ODB_RESET); 333 mlx_outb(mlx, MLX_V1REG_IDB, MLX_V1_IDB_RESET); 334 335 /* Wait up to 5 seconds for the bit to clear... */ 336 for (i = 5; i != 0; i--) { 337 delay(1000000); 338 if ((mlx_inb(mlx, MLX_V1REG_IDB) & MLX_V1_IDB_RESET) == 0) 339 break; 340 } 341 if (i == 0) 342 return (-1); 343 344 /* Wait up to 3 seconds for the other bit to clear... */ 345 for (i = 5; i != 0; i--) { 346 delay(1000000); 347 if ((mlx_inb(mlx, MLX_V1REG_ODB) & MLX_V1_ODB_RESET) == 0) 348 break; 349 } 350 if (i == 0) 351 return (-1); 352 353 return (0); 354 } 355 #endif /* MLX_RESET */ 356
Indexes created Tue Sep 30 11:09:46 GMT 2025