mlx_eisa.c revision 1.28
1 /* $NetBSD: mlx_eisa.c,v 1.28 2021/04/24 23:36:53 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * EISA front-end for mlx(4) driver. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: mlx_eisa.c,v 1.28 2021/04/24 23:36:53 thorpej Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/device.h> 42 #include <sys/module.h> 43 #include <sys/bus.h> 44 #include <sys/intr.h> 45 46 #include <dev/eisa/eisavar.h> 47 #include <dev/eisa/eisadevs.h> 48 49 #include <dev/ic/mlxreg.h> 50 #include <dev/ic/mlxio.h> 51 #include <dev/ic/mlxvar.h> 52 53 #include "ioconf.h" 54 55 #define MLX_EISA_SLOT_OFFSET 0x0c80 56 #define MLX_EISA_IOSIZE (0x0ce0 - MLX_EISA_SLOT_OFFSET) 57 #define MLX_EISA_CFG01 (0x0cc0 - MLX_EISA_SLOT_OFFSET) 58 #define MLX_EISA_CFG02 (0x0cc1 - MLX_EISA_SLOT_OFFSET) 59 #define MLX_EISA_CFG03 (0x0cc3 - MLX_EISA_SLOT_OFFSET) 60 #define MLX_EISA_CFG04 (0x0c8d - MLX_EISA_SLOT_OFFSET) 61 #define MLX_EISA_CFG05 (0x0c90 - MLX_EISA_SLOT_OFFSET) 62 #define MLX_EISA_CFG06 (0x0c91 - MLX_EISA_SLOT_OFFSET) 63 #define MLX_EISA_CFG07 (0x0c92 - MLX_EISA_SLOT_OFFSET) 64 #define MLX_EISA_CFG08 (0x0c93 - MLX_EISA_SLOT_OFFSET) 65 #define MLX_EISA_CFG09 (0x0c94 - MLX_EISA_SLOT_OFFSET) 66 #define MLX_EISA_CFG10 (0x0c95 - MLX_EISA_SLOT_OFFSET) 67 68 static void mlx_eisa_attach(device_t, device_t, void *); 69 static int mlx_eisa_match(device_t, cfdata_t, void *); 70 static int mlx_eisa_rescan(device_t, const char *, const int *); 71 72 static int mlx_v1_submit(struct mlx_softc *, struct mlx_ccb *); 73 static int mlx_v1_findcomplete(struct mlx_softc *, u_int *, u_int *); 74 static void mlx_v1_intaction(struct mlx_softc *, int); 75 static int mlx_v1_fw_handshake(struct mlx_softc *, int *, int *, int *); 76 #ifdef MLX_RESET 77 static int mlx_v1_reset(struct mlx_softc *); 78 #endif 79 80 CFATTACH_DECL3_NEW(mlx_eisa, sizeof(struct mlx_softc), 81 mlx_eisa_match, mlx_eisa_attach, NULL, NULL, mlx_eisa_rescan, NULL, 0); 82 83 static const struct device_compatible_entry compat_data[] = { 84 /* nchan */ 85 { .compat = "MLX0070", .value = 1 }, 86 { .compat = "MLX0071", .value = 3 }, 87 { .compat = "MLX0072", .value = 3 }, 88 { .compat = "MLX0073", .value = 2 }, 89 { .compat = "MLX0074", .value = 1 }, 90 { .compat = "MLX0075", .value = 3 }, 91 { .compat = "MLX0076", .value = 2 }, 92 { .compat = "MLX0077", .value = 1 }, 93 DEVICE_COMPAT_EOL 94 }; 95 96 static int 97 mlx_eisa_match(device_t parent, cfdata_t match, 98 void *aux) 99 { 100 struct eisa_attach_args *ea = aux; 101 102 return (eisa_compatible_match(ea, compat_data)); 103 } 104 105 static void 106 mlx_eisa_attach(device_t parent, device_t self, void *aux) 107 { 108 struct eisa_attach_args *ea = aux; 109 const struct device_compatible_entry *dce; 110 bus_space_handle_t ioh; 111 eisa_chipset_tag_t ec; 112 eisa_intr_handle_t ih; 113 struct mlx_softc *mlx; 114 bus_space_tag_t iot; 115 const char *intrstr; 116 int irq, icfg; 117 char intrbuf[EISA_INTRSTR_LEN]; 118 119 mlx = device_private(self); 120 iot = ea->ea_iot; 121 ec = ea->ea_ec; 122 123 if (bus_space_map(iot, EISA_SLOT_ADDR(ea->ea_slot) + 124 MLX_EISA_SLOT_OFFSET, MLX_EISA_IOSIZE, 0, &ioh)) { 125 aprint_error(": can't map i/o space\n"); 126 return; 127 } 128 129 mlx->mlx_dv = self; 130 mlx->mlx_iot = iot; 131 mlx->mlx_ioh = ioh; 132 mlx->mlx_dmat = ea->ea_dmat; 133 134 /* 135 * Map and establish the interrupt. 136 */ 137 icfg = bus_space_read_1(iot, ioh, MLX_EISA_CFG03); 138 139 switch (icfg & 0xf0) { 140 case 0xa0: 141 irq = 11; 142 break; 143 case 0xc0: 144 irq = 12; 145 break; 146 case 0xe0: 147 irq = 14; 148 break; 149 case 0x80: 150 irq = 15; 151 break; 152 default: 153 aprint_error(": controller on invalid IRQ\n"); 154 return; 155 } 156 157 if (eisa_intr_map(ec, irq, &ih)) { 158 aprint_error(": can't map interrupt (%d)\n", irq); 159 return; 160 } 161 162 intrstr = eisa_intr_string(ec, ih, intrbuf, sizeof(intrbuf)); 163 mlx->mlx_ih = eisa_intr_establish(ec, ih, 164 ((icfg & 0x08) != 0 ? IST_LEVEL : IST_EDGE), 165 IPL_BIO, mlx_intr, mlx); 166 if (mlx->mlx_ih == NULL) { 167 aprint_error(": can't establish interrupt"); 168 if (intrstr != NULL) 169 aprint_normal(" at %s", intrstr); 170 aprint_normal("\n"); 171 return; 172 } 173 174 dce = eisa_compatible_lookup(ea, compat_data); 175 KASSERT(dce != NULL); 176 177 mlx->mlx_ci.ci_nchan = (int)dce->value; 178 mlx->mlx_ci.ci_iftype = 1; 179 180 mlx->mlx_submit = mlx_v1_submit; 181 mlx->mlx_findcomplete = mlx_v1_findcomplete; 182 mlx->mlx_intaction = mlx_v1_intaction; 183 mlx->mlx_fw_handshake = mlx_v1_fw_handshake; 184 #ifdef MLX_RESET 185 mlx->mlx_reset = mlx_v1_reset; 186 #endif 187 188 aprint_normal(": Mylex RAID\n"); 189 mlx_init(mlx, intrstr); 190 } 191 192 static int 193 mlx_eisa_rescan(device_t self, const char *ifattr, const int *locs) 194 { 195 196 return mlx_configure(device_private(self), 1); 197 } 198 199 /* 200 * ================= V1 interface linkage ================= 201 */ 202 203 /* 204 * Try to give (mc) to the controller. Returns 1 if successful, 0 on 205 * failure (the controller is not ready to take a command). 206 * 207 * Must be called at splbio or in a fashion that prevents reentry. 208 */ 209 static int 210 mlx_v1_submit(struct mlx_softc *mlx, struct mlx_ccb *mc) 211 { 212 213 /* Ready for our command? */ 214 if ((mlx_inb(mlx, MLX_V1REG_IDB) & MLX_V1_IDB_FULL) == 0) { 215 /* Copy mailbox data to window. */ 216 bus_space_write_region_1(mlx->mlx_iot, mlx->mlx_ioh, 217 MLX_V1REG_MAILBOX, mc->mc_mbox, 13); 218 bus_space_barrier(mlx->mlx_iot, mlx->mlx_ioh, 219 MLX_V1REG_MAILBOX, 13, 220 BUS_SPACE_BARRIER_WRITE); 221 222 /* Post command. */ 223 mlx_outb(mlx, MLX_V1REG_IDB, MLX_V1_IDB_FULL); 224 return (1); 225 } 226 227 return (0); 228 } 229 230 /* 231 * See if a command has been completed, if so acknowledge its completion and 232 * recover the slot number and status code. 233 * 234 * Must be called at splbio or in a fashion that prevents reentry. 235 */ 236 static int 237 mlx_v1_findcomplete(struct mlx_softc *mlx, u_int *slot, u_int *status) 238 { 239 240 /* Status available? */ 241 if ((mlx_inb(mlx, MLX_V1REG_ODB) & MLX_V1_ODB_SAVAIL) != 0) { 242 *slot = mlx_inb(mlx, MLX_V1REG_MAILBOX + 0x0d); 243 *status = mlx_inw(mlx, MLX_V1REG_MAILBOX + 0x0e); 244 245 /* Acknowledge completion. */ 246 mlx_outb(mlx, MLX_V1REG_ODB, MLX_V1_ODB_SAVAIL); 247 mlx_outb(mlx, MLX_V1REG_IDB, MLX_V1_IDB_SACK); 248 return (1); 249 } 250 251 return (0); 252 } 253 254 /* 255 * Enable/disable interrupts as requested. (No acknowledge required) 256 * 257 * Must be called at splbio or in a fashion that prevents reentry. 258 */ 259 static void 260 mlx_v1_intaction(struct mlx_softc *mlx, int action) 261 { 262 263 mlx_outb(mlx, MLX_V1REG_IE, action ? 1 : 0); 264 } 265 266 /* 267 * Poll for firmware error codes during controller initialisation. 268 * 269 * Returns 0 if initialisation is complete, 1 if still in progress but no 270 * error has been fetched, 2 if an error has been retrieved. 271 */ 272 static int 273 mlx_v1_fw_handshake(struct mlx_softc *mlx, int *error, int *param1, int *param2) 274 { 275 u_int8_t fwerror; 276 277 /* 278 * First time around, enable the IDB interrupt and clear any 279 * hardware completion status. 280 */ 281 if ((mlx->mlx_flags & MLXF_FW_INITTED) == 0) { 282 mlx_outb(mlx, MLX_V1REG_ODB_EN, 1); 283 DELAY(1000); 284 mlx_outb(mlx, MLX_V1REG_ODB, 1); 285 DELAY(1000); 286 mlx_outb(mlx, MLX_V1REG_IDB, MLX_V1_IDB_SACK); 287 DELAY(1000); 288 mlx->mlx_flags |= MLXF_FW_INITTED; 289 } 290 291 /* Init in progress? */ 292 if ((mlx_inb(mlx, MLX_V1REG_IDB) & MLX_V1_IDB_INIT_BUSY) == 0) 293 return (0); 294 295 /* Test error value. */ 296 fwerror = mlx_inb(mlx, MLX_V1REG_ODB); 297 298 if ((fwerror & MLX_V1_FWERROR_PEND) == 0) 299 return (1); 300 301 /* XXX Fetch status. */ 302 *error = fwerror & 0xf0; 303 *param1 = -1; 304 *param2 = -1; 305 306 /* Acknowledge. */ 307 mlx_outb(mlx, MLX_V1REG_ODB, fwerror); 308 309 return (2); 310 } 311 312 #ifdef MLX_RESET 313 /* 314 * Reset the controller. Return non-zero on failure. 315 */ 316 static int 317 mlx_v1_reset(struct mlx_softc *mlx) 318 { 319 int i; 320 321 mlx_outb(mlx, MLX_V1REG_IDB, MLX_V1_IDB_SACK); 322 delay(1000000); 323 324 /* Wait up to 2 minutes for the bit to clear. */ 325 for (i = 120; i != 0; i--) { 326 delay(1000000); 327 if ((mlx_inb(mlx, MLX_V1REG_IDB) & MLX_V1_IDB_SACK) == 0) 328 break; 329 } 330 if (i == 0) 331 return (-1); 332 333 mlx_outb(mlx, MLX_V1REG_ODB, MLX_V1_ODB_RESET); 334 mlx_outb(mlx, MLX_V1REG_IDB, MLX_V1_IDB_RESET); 335 336 /* Wait up to 5 seconds for the bit to clear... */ 337 for (i = 5; i != 0; i--) { 338 delay(1000000); 339 if ((mlx_inb(mlx, MLX_V1REG_IDB) & MLX_V1_IDB_RESET) == 0) 340 break; 341 } 342 if (i == 0) 343 return (-1); 344 345 /* Wait up to 3 seconds for the other bit to clear... */ 346 for (i = 5; i != 0; i--) { 347 delay(1000000); 348 if ((mlx_inb(mlx, MLX_V1REG_ODB) & MLX_V1_ODB_RESET) == 0) 349 break; 350 } 351 if (i == 0) 352 return (-1); 353 354 return (0); 355 } 356 #endif /* MLX_RESET */ 357 358 MODULE(MODULE_CLASS_DRIVER, mlx_eisa, "mlx"); /* No eisa module yet! */ 359 360 #ifdef _MODULE 361 /* 362 * XXX Don't allow ioconf.c to redefine the "struct cfdriver cac_cd" 363 * XXX it will be defined in the common-code module 364 */ 365 #undef CFDRIVER_DECL 366 #define CFDRIVER_DECL(name, class, attr) 367 #include "ioconf.c" 368 #endif 369 370 static int 371 mlx_eisa_modcmd(modcmd_t cmd, void *opaque) 372 { 373 int error = 0; 374 375 #ifdef _MODULE 376 switch (cmd) { 377 case MODULE_CMD_INIT: 378 /* 379 * We skip over the first entry in cfdriver[] array 380 * since the cfdriver is attached by the common 381 * (non-attachment-specific) code. 382 */ 383 error = config_init_component(&cfdriver_ioconf_mlx_eisa[1], 384 cfattach_ioconf_mlx_eisa, cfdata_ioconf_mlx_eisa); 385 break; 386 case MODULE_CMD_FINI: 387 error = config_fini_component(&cfdriver_ioconf_mlx_eisa[1], 388 cfattach_ioconf_mlx_eisa, cfdata_ioconf_mlx_eisa); 389 break; 390 default: 391 error = ENOTTY; 392 break; 393 } 394 #endif 395 396 return error; 397 } 398
Indexes created Tue Sep 30 11:09:46 GMT 2025