mlx_eisa.c revision 1.30
1 /* $NetBSD: mlx_eisa.c,v 1.30 2022/07/12 02:12:26 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * EISA front-end for mlx(4) driver. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: mlx_eisa.c,v 1.30 2022/07/12 02:12:26 thorpej Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/device.h> 42 #include <sys/module.h> 43 #include <sys/bus.h> 44 #include <sys/intr.h> 45 46 #include <dev/eisa/eisavar.h> 47 #include <dev/eisa/eisadevs.h> 48 49 #include <dev/ic/mlxreg.h> 50 #include <dev/ic/mlxio.h> 51 #include <dev/ic/mlxvar.h> 52 53 #include "ioconf.h" 54 55 #define MLX_EISA_SLOT_OFFSET 0x0c80 56 #define MLX_EISA_IOSIZE (0x0ce0 - MLX_EISA_SLOT_OFFSET) 57 #define MLX_EISA_CFG01 (0x0cc0 - MLX_EISA_SLOT_OFFSET) 58 #define MLX_EISA_CFG02 (0x0cc1 - MLX_EISA_SLOT_OFFSET) 59 #define MLX_EISA_CFG03 (0x0cc3 - MLX_EISA_SLOT_OFFSET) 60 #define MLX_EISA_CFG04 (0x0c8d - MLX_EISA_SLOT_OFFSET) 61 #define MLX_EISA_CFG05 (0x0c90 - MLX_EISA_SLOT_OFFSET) 62 #define MLX_EISA_CFG06 (0x0c91 - MLX_EISA_SLOT_OFFSET) 63 #define MLX_EISA_CFG07 (0x0c92 - MLX_EISA_SLOT_OFFSET) 64 #define MLX_EISA_CFG08 (0x0c93 - MLX_EISA_SLOT_OFFSET) 65 #define MLX_EISA_CFG09 (0x0c94 - MLX_EISA_SLOT_OFFSET) 66 #define MLX_EISA_CFG10 (0x0c95 - MLX_EISA_SLOT_OFFSET) 67 68 static void mlx_eisa_attach(device_t, device_t, void *); 69 static int mlx_eisa_match(device_t, cfdata_t, void *); 70 static int mlx_eisa_rescan(device_t, const char *, const int *); 71 72 static int mlx_v1_submit(struct mlx_softc *, struct mlx_ccb *); 73 static int mlx_v1_findcomplete(struct mlx_softc *, u_int *, u_int *); 74 static void mlx_v1_intaction(struct mlx_softc *, int); 75 static int mlx_v1_fw_handshake(struct mlx_softc *, int *, int *, int *); 76 #ifdef MLX_RESET 77 static int mlx_v1_reset(struct mlx_softc *); 78 #endif 79 80 CFATTACH_DECL3_NEW(mlx_eisa, sizeof(struct mlx_softc), 81 mlx_eisa_match, mlx_eisa_attach, NULL, NULL, mlx_eisa_rescan, NULL, 0); 82 83 static const struct device_compatible_entry compat_data[] = { 84 /* nchan */ 85 { .compat = "MLX0070", .value = 1 }, 86 { .compat = "MLX0071", .value = 3 }, 87 { .compat = "MLX0072", .value = 3 }, 88 { .compat = "MLX0073", .value = 2 }, 89 { .compat = "MLX0074", .value = 1 }, 90 { .compat = "MLX0075", .value = 3 }, 91 { .compat = "MLX0076", .value = 2 }, 92 { .compat = "MLX0077", .value = 1 }, 93 DEVICE_COMPAT_EOL 94 }; 95 96 static int 97 mlx_eisa_match(device_t parent, cfdata_t match, 98 void *aux) 99 { 100 struct eisa_attach_args *ea = aux; 101 102 return (eisa_compatible_match(ea, compat_data)); 103 } 104 105 static void 106 mlx_eisa_attach(device_t parent, device_t self, void *aux) 107 { 108 struct eisa_attach_args *ea = aux; 109 const struct device_compatible_entry *dce; 110 bus_space_handle_t ioh; 111 eisa_chipset_tag_t ec; 112 eisa_intr_handle_t ih; 113 struct mlx_softc *mlx; 114 bus_space_tag_t iot; 115 const char *intrstr; 116 int irq, ist, icfg; 117 char intrbuf[EISA_INTRSTR_LEN]; 118 119 mlx = device_private(self); 120 iot = ea->ea_iot; 121 ec = ea->ea_ec; 122 123 dce = eisa_compatible_lookup(ea, compat_data); 124 KASSERT(dce != NULL); 125 126 mlx->mlx_ci.ci_nchan = (int)dce->value; 127 mlx->mlx_ci.ci_iftype = 1; 128 129 mlx->mlx_submit = mlx_v1_submit; 130 mlx->mlx_findcomplete = mlx_v1_findcomplete; 131 mlx->mlx_intaction = mlx_v1_intaction; 132 mlx->mlx_fw_handshake = mlx_v1_fw_handshake; 133 #ifdef MLX_RESET 134 mlx->mlx_reset = mlx_v1_reset; 135 #endif 136 137 aprint_normal(": Mylex RAID\n"); 138 139 if (bus_space_map(iot, EISA_SLOT_ADDR(ea->ea_slot) + 140 MLX_EISA_SLOT_OFFSET, MLX_EISA_IOSIZE, 0, &ioh)) { 141 aprint_error_dev(self, "can't map i/o space\n"); 142 return; 143 } 144 145 mlx->mlx_dv = self; 146 mlx->mlx_iot = iot; 147 mlx->mlx_ioh = ioh; 148 mlx->mlx_dmat = ea->ea_dmat; 149 150 /* 151 * Map and establish the interrupt. 152 */ 153 icfg = bus_space_read_1(iot, ioh, MLX_EISA_CFG03); 154 155 switch (icfg & 0xf0) { 156 case 0xa0: 157 irq = 11; 158 break; 159 case 0xc0: 160 irq = 12; 161 break; 162 case 0xe0: 163 irq = 14; 164 break; 165 case 0x80: 166 irq = 15; 167 break; 168 default: 169 aprint_error_dev(self, 170 "controller on invalid IRQ (icfg=0x%02x)\n", icfg); 171 return; 172 } 173 174 ist = (icfg & 0x08) != 0 ? IST_LEVEL : IST_EDGE; 175 176 if (eisa_intr_map(ec, irq, &ih)) { 177 aprint_error_dev(self, "can't map interrupt (%d)\n", irq); 178 return; 179 } 180 181 intrstr = eisa_intr_string(ec, ih, intrbuf, sizeof(intrbuf)); 182 mlx->mlx_ih = eisa_intr_establish(ec, ih, ist, IPL_BIO, mlx_intr, mlx); 183 if (mlx->mlx_ih == NULL) { 184 aprint_error_dev(self, "can't establish interrupt"); 185 if (intrstr != NULL) 186 aprint_error(" at %s", intrstr); 187 aprint_error("\n"); 188 return; 189 } 190 if (intrstr != NULL) { 191 aprint_normal_dev(self, "interrupting at %s (%s trigger)\n", 192 ist == IST_EDGE ? "edge" : "level", intrstr); 193 } 194 195 mlx_init(mlx, intrstr); 196 } 197 198 static int 199 mlx_eisa_rescan(device_t self, const char *ifattr, const int *locs) 200 { 201 202 return mlx_configure(device_private(self), 1); 203 } 204 205 /* 206 * ================= V1 interface linkage ================= 207 */ 208 209 /* 210 * Try to give (mc) to the controller. Returns 1 if successful, 0 on 211 * failure (the controller is not ready to take a command). 212 * 213 * Must be called at splbio or in a fashion that prevents reentry. 214 */ 215 static int 216 mlx_v1_submit(struct mlx_softc *mlx, struct mlx_ccb *mc) 217 { 218 219 /* Ready for our command? */ 220 if ((mlx_inb(mlx, MLX_V1REG_IDB) & MLX_V1_IDB_FULL) == 0) { 221 /* Copy mailbox data to window. */ 222 bus_space_write_region_1(mlx->mlx_iot, mlx->mlx_ioh, 223 MLX_V1REG_MAILBOX, mc->mc_mbox, 13); 224 225 /* Post command. */ 226 mlx_outb(mlx, MLX_V1REG_IDB, MLX_V1_IDB_FULL); 227 return (1); 228 } 229 230 return (0); 231 } 232 233 /* 234 * See if a command has been completed, if so acknowledge its completion and 235 * recover the slot number and status code. 236 * 237 * Must be called at splbio or in a fashion that prevents reentry. 238 */ 239 static int 240 mlx_v1_findcomplete(struct mlx_softc *mlx, u_int *slot, u_int *status) 241 { 242 243 /* Status available? */ 244 if ((mlx_inb(mlx, MLX_V1REG_ODB) & MLX_V1_ODB_SAVAIL) != 0) { 245 *slot = mlx_inb(mlx, MLX_V1REG_MAILBOX + 0x0d); 246 *status = mlx_inw(mlx, MLX_V1REG_MAILBOX + 0x0e); 247 248 /* Acknowledge completion. */ 249 mlx_outb(mlx, MLX_V1REG_ODB, MLX_V1_ODB_SAVAIL); 250 mlx_outb(mlx, MLX_V1REG_IDB, MLX_V1_IDB_SACK); 251 return (1); 252 } 253 254 return (0); 255 } 256 257 /* 258 * Enable/disable interrupts as requested. (No acknowledge required) 259 * 260 * Must be called at splbio or in a fashion that prevents reentry. 261 */ 262 static void 263 mlx_v1_intaction(struct mlx_softc *mlx, int action) 264 { 265 266 mlx_outb(mlx, MLX_V1REG_IE, action ? 1 : 0); 267 } 268 269 /* 270 * Poll for firmware error codes during controller initialisation. 271 * 272 * Returns 0 if initialisation is complete, 1 if still in progress but no 273 * error has been fetched, 2 if an error has been retrieved. 274 */ 275 static int 276 mlx_v1_fw_handshake(struct mlx_softc *mlx, int *error, int *param1, int *param2) 277 { 278 u_int8_t fwerror; 279 280 /* 281 * First time around, enable the IDB interrupt and clear any 282 * hardware completion status. 283 */ 284 if ((mlx->mlx_flags & MLXF_FW_INITTED) == 0) { 285 mlx_outb(mlx, MLX_V1REG_ODB_EN, 1); 286 DELAY(1000); 287 mlx_outb(mlx, MLX_V1REG_ODB, 1); 288 DELAY(1000); 289 mlx_outb(mlx, MLX_V1REG_IDB, MLX_V1_IDB_SACK); 290 DELAY(1000); 291 mlx->mlx_flags |= MLXF_FW_INITTED; 292 } 293 294 /* Init in progress? */ 295 if ((mlx_inb(mlx, MLX_V1REG_IDB) & MLX_V1_IDB_INIT_BUSY) == 0) 296 return (0); 297 298 /* Test error value. */ 299 fwerror = mlx_inb(mlx, MLX_V1REG_ODB); 300 301 if ((fwerror & MLX_V1_FWERROR_PEND) == 0) 302 return (1); 303 304 /* XXX Fetch status. */ 305 *error = fwerror & 0xf0; 306 *param1 = -1; 307 *param2 = -1; 308 309 /* Acknowledge. */ 310 mlx_outb(mlx, MLX_V1REG_ODB, fwerror); 311 312 return (2); 313 } 314 315 #ifdef MLX_RESET 316 /* 317 * Reset the controller. Return non-zero on failure. 318 */ 319 static int 320 mlx_v1_reset(struct mlx_softc *mlx) 321 { 322 int i; 323 324 mlx_outb(mlx, MLX_V1REG_IDB, MLX_V1_IDB_SACK); 325 delay(1000000); 326 327 /* Wait up to 2 minutes for the bit to clear. */ 328 for (i = 120; i != 0; i--) { 329 delay(1000000); 330 if ((mlx_inb(mlx, MLX_V1REG_IDB) & MLX_V1_IDB_SACK) == 0) 331 break; 332 } 333 if (i == 0) 334 return (-1); 335 336 mlx_outb(mlx, MLX_V1REG_ODB, MLX_V1_ODB_RESET); 337 mlx_outb(mlx, MLX_V1REG_IDB, MLX_V1_IDB_RESET); 338 339 /* Wait up to 5 seconds for the bit to clear... */ 340 for (i = 5; i != 0; i--) { 341 delay(1000000); 342 if ((mlx_inb(mlx, MLX_V1REG_IDB) & MLX_V1_IDB_RESET) == 0) 343 break; 344 } 345 if (i == 0) 346 return (-1); 347 348 /* Wait up to 3 seconds for the other bit to clear... */ 349 for (i = 5; i != 0; i--) { 350 delay(1000000); 351 if ((mlx_inb(mlx, MLX_V1REG_ODB) & MLX_V1_ODB_RESET) == 0) 352 break; 353 } 354 if (i == 0) 355 return (-1); 356 357 return (0); 358 } 359 #endif /* MLX_RESET */ 360 361 MODULE(MODULE_CLASS_DRIVER, mlx_eisa, "mlx"); /* No eisa module yet! */ 362 363 #ifdef _MODULE 364 /* 365 * XXX Don't allow ioconf.c to redefine the "struct cfdriver cac_cd" 366 * XXX it will be defined in the common-code module 367 */ 368 #undef CFDRIVER_DECL 369 #define CFDRIVER_DECL(name, class, attr) 370 #include "ioconf.c" 371 #endif 372 373 static int 374 mlx_eisa_modcmd(modcmd_t cmd, void *opaque) 375 { 376 int error = 0; 377 378 #ifdef _MODULE 379 switch (cmd) { 380 case MODULE_CMD_INIT: 381 /* 382 * We skip over the first entry in cfdriver[] array 383 * since the cfdriver is attached by the common 384 * (non-attachment-specific) code. 385 */ 386 error = config_init_component(&cfdriver_ioconf_mlx_eisa[1], 387 cfattach_ioconf_mlx_eisa, cfdata_ioconf_mlx_eisa); 388 break; 389 case MODULE_CMD_FINI: 390 error = config_fini_component(&cfdriver_ioconf_mlx_eisa[1], 391 cfattach_ioconf_mlx_eisa, cfdata_ioconf_mlx_eisa); 392 break; 393 default: 394 error = ENOTTY; 395 break; 396 } 397 #endif 398 399 return error; 400 } 401
Indexes created Tue Sep 30 11:09:46 GMT 2025