uha_eisa.c revision 1.3
1 /* $NetBSD: uha_eisa.c,v 1.3 1996/10/10 19:54:14 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1994, 1996 Charles M. Hannum. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Charles M. Hannum. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/types.h> 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/device.h> 36 #include <sys/kernel.h> 37 #include <sys/proc.h> 38 #include <sys/user.h> 39 40 #include <machine/bus.h> 41 #include <machine/intr.h> 42 43 #include <scsi/scsi_all.h> 44 #include <scsi/scsiconf.h> 45 46 #include <dev/eisa/eisavar.h> 47 #include <dev/eisa/eisadevs.h> 48 49 #include <dev/ic/uhareg.h> 50 #include <dev/ic/uhavar.h> 51 52 #define UHA_EISA_SLOT_OFFSET 0xc80 53 #define UHA_EISA_IOSIZE 0x020 54 55 int uha_eisa_match __P((struct device *, void *, void *)); 56 void uha_eisa_attach __P((struct device *, struct device *, void *)); 57 58 struct cfattach uha_eisa_ca = { 59 sizeof(struct uha_softc), uha_eisa_match, uha_eisa_attach 60 }; 61 62 #define KVTOPHYS(x) vtophys(x) 63 64 int u24_find __P((bus_chipset_tag_t, bus_io_handle_t, struct uha_softc *)); 65 void u24_start_mbox __P((struct uha_softc *, struct uha_mscp *)); 66 int u24_poll __P((struct uha_softc *, struct scsi_xfer *, int)); 67 int u24_intr __P((void *)); 68 void u24_init __P((struct uha_softc *)); 69 70 /* 71 * Check the slots looking for a board we recognise 72 * If we find one, note it's address (slot) and call 73 * the actual probe routine to check it out. 74 */ 75 int 76 uha_eisa_match(parent, match, aux) 77 struct device *parent; 78 void *match, *aux; 79 { 80 struct eisa_attach_args *ea = aux; 81 bus_chipset_tag_t bc = ea->ea_bc; 82 bus_io_handle_t ioh; 83 int rv; 84 85 /* must match one of our known ID strings */ 86 if (strncmp(ea->ea_idstring, "USC024", 6)) 87 return (0); 88 89 if (bus_io_map(bc, EISA_SLOT_ADDR(ea->ea_slot) + UHA_EISA_SLOT_OFFSET, 90 UHA_EISA_IOSIZE, &ioh)) 91 return (0); 92 93 rv = u24_find(bc, ioh, NULL); 94 95 bus_io_unmap(bc, ioh, UHA_EISA_IOSIZE); 96 97 return (rv); 98 } 99 100 /* 101 * Attach all the sub-devices we can find 102 */ 103 void 104 uha_eisa_attach(parent, self, aux) 105 struct device *parent, *self; 106 void *aux; 107 { 108 struct eisa_attach_args *ea = aux; 109 struct uha_softc *sc = (void *)self; 110 bus_chipset_tag_t bc = ea->ea_bc; 111 bus_io_handle_t ioh; 112 eisa_chipset_tag_t ec = ea->ea_ec; 113 eisa_intr_handle_t ih; 114 const char *model, *intrstr; 115 116 if (!strncmp(ea->ea_idstring, "USC024", 6)) 117 model = EISA_PRODUCT_USC0240; 118 else 119 model = "unknown model!"; 120 kprintf(": %s\n", model); 121 122 if (bus_io_map(bc, EISA_SLOT_ADDR(ea->ea_slot) + UHA_EISA_SLOT_OFFSET, 123 UHA_EISA_IOSIZE, &ioh)) 124 panic("uha_attach: could not map I/O addresses"); 125 126 sc->sc_bc = bc; 127 sc->sc_ioh = ioh; 128 if (!u24_find(bc, ioh, sc)) 129 panic("uha_attach: u24_find failed!"); 130 131 if (eisa_intr_map(ec, sc->sc_irq, &ih)) { 132 kprintf("%s: couldn't map interrupt (%d)\n", 133 sc->sc_dev.dv_xname, sc->sc_irq); 134 return; 135 } 136 intrstr = eisa_intr_string(ec, ih); 137 sc->sc_ih = eisa_intr_establish(ec, ih, IST_LEVEL, IPL_BIO, 138 u24_intr, sc); 139 if (sc->sc_ih == NULL) { 140 kprintf("%s: couldn't establish interrupt", 141 sc->sc_dev.dv_xname); 142 if (intrstr != NULL) 143 kprintf(" at %s", intrstr); 144 kprintf("\n"); 145 return; 146 } 147 kprintf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 148 149 /* Save function pointers for later use. */ 150 sc->start_mbox = u24_start_mbox; 151 sc->poll = u24_poll; 152 sc->init = u24_init; 153 154 uha_attach(sc); 155 } 156 157 int 158 u24_find(bc, ioh, sc) 159 bus_chipset_tag_t bc; 160 bus_io_handle_t ioh; 161 struct uha_softc *sc; 162 { 163 u_int8_t config0, config1, config2; 164 int irq, drq; 165 int resetcount = 4000; /* 4 secs? */ 166 167 config0 = bus_io_read_1(bc, ioh, U24_CONFIG + 0); 168 config1 = bus_io_read_1(bc, ioh, U24_CONFIG + 1); 169 config2 = bus_io_read_1(bc, ioh, U24_CONFIG + 2); 170 if ((config0 & U24_MAGIC1) == 0 || 171 (config1 & U24_MAGIC2) == 0) 172 return (0); 173 174 drq = -1; 175 176 switch (config0 & U24_IRQ_MASK) { 177 case U24_IRQ10: 178 irq = 10; 179 break; 180 case U24_IRQ11: 181 irq = 11; 182 break; 183 case U24_IRQ14: 184 irq = 14; 185 break; 186 case U24_IRQ15: 187 irq = 15; 188 break; 189 default: 190 kprintf("u24_find: illegal irq setting %x\n", 191 config0 & U24_IRQ_MASK); 192 return (0); 193 } 194 195 bus_io_write_1(bc, ioh, U24_LINT, UHA_ASRST); 196 197 while (--resetcount) { 198 if (bus_io_read_1(bc, ioh, U24_LINT)) 199 break; 200 delay(1000); /* 1 mSec per loop */ 201 } 202 if (!resetcount) { 203 kprintf("u24_find: board timed out during reset\n"); 204 return (0); 205 } 206 207 /* if we want to fill in softc, do so now */ 208 if (sc != NULL) { 209 sc->sc_irq = irq; 210 sc->sc_drq = drq; 211 sc->sc_scsi_dev = config2 & U24_HOSTID_MASK; 212 } 213 214 return (1); 215 } 216 217 void 218 u24_start_mbox(sc, mscp) 219 struct uha_softc *sc; 220 struct uha_mscp *mscp; 221 { 222 bus_chipset_tag_t bc = sc->sc_bc; 223 bus_io_handle_t ioh = sc->sc_ioh; 224 int spincount = 100000; /* 1s should be enough */ 225 226 while (--spincount) { 227 if ((bus_io_read_1(bc, ioh, U24_LINT) & U24_LDIP) == 0) 228 break; 229 delay(100); 230 } 231 if (!spincount) { 232 kprintf("%s: uha_start_mbox, board not responding\n", 233 sc->sc_dev.dv_xname); 234 Debugger(); 235 } 236 237 bus_io_write_4(bc, ioh, U24_OGMPTR, KVTOPHYS(mscp)); 238 if (mscp->flags & MSCP_ABORT) 239 bus_io_write_1(bc, ioh, U24_OGMCMD, 0x80); 240 else 241 bus_io_write_1(bc, ioh, U24_OGMCMD, 0x01); 242 bus_io_write_1(bc, ioh, U24_LINT, U24_OGMFULL); 243 244 if ((mscp->xs->flags & SCSI_POLL) == 0) 245 timeout(uha_timeout, mscp, (mscp->timeout * hz) / 1000); 246 } 247 248 int 249 u24_poll(sc, xs, count) 250 struct uha_softc *sc; 251 struct scsi_xfer *xs; 252 int count; 253 { 254 bus_chipset_tag_t bc = sc->sc_bc; 255 bus_io_handle_t ioh = sc->sc_ioh; 256 257 while (count) { 258 /* 259 * If we had interrupts enabled, would we 260 * have got an interrupt? 261 */ 262 if (bus_io_read_1(bc, ioh, U24_SINT) & U24_SDIP) 263 u24_intr(sc); 264 if (xs->flags & ITSDONE) 265 return (0); 266 delay(1000); 267 count--; 268 } 269 return (1); 270 } 271 272 int 273 u24_intr(arg) 274 void *arg; 275 { 276 struct uha_softc *sc = arg; 277 bus_chipset_tag_t bc = sc->sc_bc; 278 bus_io_handle_t ioh = sc->sc_ioh; 279 struct uha_mscp *mscp; 280 u_char uhastat; 281 u_long mboxval; 282 283 #ifdef UHADEBUG 284 kprintf("%s: uhaintr ", sc->sc_dev.dv_xname); 285 #endif /*UHADEBUG */ 286 287 if ((bus_io_read_1(bc, ioh, U24_SINT) & U24_SDIP) == 0) 288 return (0); 289 290 for (;;) { 291 /* 292 * First get all the information and then 293 * acknowledge the interrupt 294 */ 295 uhastat = bus_io_read_1(bc, ioh, U24_SINT); 296 mboxval = bus_io_read_4(bc, ioh, U24_ICMPTR); 297 bus_io_write_1(bc, ioh, U24_SINT, U24_ICM_ACK); 298 bus_io_write_1(bc, ioh, U24_ICMCMD, 0); 299 300 #ifdef UHADEBUG 301 kprintf("status = 0x%x ", uhastat); 302 #endif /*UHADEBUG*/ 303 304 /* 305 * Process the completed operation 306 */ 307 mscp = uha_mscp_phys_kv(sc, mboxval); 308 if (!mscp) { 309 kprintf("%s: BAD MSCP RETURNED!\n", 310 sc->sc_dev.dv_xname); 311 continue; /* whatever it was, it'll timeout */ 312 } 313 untimeout(uha_timeout, mscp); 314 uha_done(sc, mscp); 315 316 if ((bus_io_read_1(bc, ioh, U24_SINT) & U24_SDIP) == 0) 317 return (1); 318 } 319 } 320 321 void 322 u24_init(sc) 323 struct uha_softc *sc; 324 { 325 bus_chipset_tag_t bc = sc->sc_bc; 326 bus_io_handle_t ioh = sc->sc_ioh; 327 328 /* free OGM and ICM */ 329 bus_io_write_1(bc, ioh, U24_OGMCMD, 0); 330 bus_io_write_1(bc, ioh, U24_ICMCMD, 0); 331 /* make sure interrupts are enabled */ 332 #ifdef UHADEBUG 333 kprintf("u24_init: lmask=%02x, smask=%02x\n", 334 bus_io_read_1(bc, ioh, U24_LMASK), 335 bus_io_read_1(bc, ioh, U24_SMASK)); 336 #endif 337 bus_io_write_1(bc, ioh, U24_LMASK, 0xd2); /* XXX */ 338 bus_io_write_1(bc, ioh, U24_SMASK, 0x92); /* XXX */ 339 } 340
Indexes created Fri Sep 26 08:10:20 GMT 2025