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fixedfactorclock.c revision 1.1.4.2 
      1 /* $NetBSD: fixedfactorclock.c,v 1.1.4.2 2017/07/18 19:13:09 snj Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca>
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  * SUCH DAMAGE.
     27  */
     28 
     29 #include <sys/cdefs.h>
     30 __KERNEL_RCSID(0, "$NetBSD: fixedfactorclock.c,v 1.1.4.2 2017/07/18 19:13:09 snj Exp $");
     31 
     32 #include <sys/param.h>
     33 #include <sys/systm.h>
     34 #include <sys/device.h>
     35 #include <sys/kmem.h>
     36 #include <sys/bus.h>
     37 
     38 #include <dev/clk/clk_backend.h>
     39 
     40 #include <dev/fdt/fdtvar.h>
     41 
     42 static int	fixedfactorclock_match(device_t, cfdata_t, void *);
     43 static void	fixedfactorclock_attach(device_t, device_t, void *);
     44 
     45 static struct clk *fixedfactorclock_decode(device_t, const void *, size_t);
     46 
     47 static const struct fdtbus_clock_controller_func fixedfactorclock_fdt_funcs = {
     48 	.decode = fixedfactorclock_decode
     49 };
     50 
     51 static struct clk *fixedfactorclock_get(void *, const char *);
     52 static void	fixedfactorclock_put(void *, struct clk *);
     53 static u_int	fixedfactorclock_get_rate(void *, struct clk *);
     54 
     55 static const struct clk_funcs fixedfactorclock_clk_funcs = {
     56 	.get = fixedfactorclock_get,
     57 	.put = fixedfactorclock_put,
     58 	.get_rate = fixedfactorclock_get_rate,
     59 };
     60 
     61 struct fixedfactorclock_clk {
     62 	struct clk	base;
     63 
     64 	u_int		div;
     65 	u_int		mult;
     66 };
     67 
     68 struct fixedfactorclock_softc {
     69 	device_t	sc_dev;
     70 	int		sc_phandle;
     71 
     72 	struct clk_domain sc_clkdom;
     73 	struct fixedfactorclock_clk sc_clk;
     74 };
     75 
     76 CFATTACH_DECL_NEW(ffclock, sizeof(struct fixedfactorclock_softc),
     77     fixedfactorclock_match, fixedfactorclock_attach, NULL, NULL);
     78 
     79 static int
     80 fixedfactorclock_match(device_t parent, cfdata_t cf, void *aux)
     81 {
     82 	const char * const compatible[] = { "fixed-factor-clock", NULL };
     83 	const struct fdt_attach_args *faa = aux;
     84 
     85 	return of_match_compatible(faa->faa_phandle, compatible);
     86 }
     87 
     88 static void
     89 fixedfactorclock_attach(device_t parent, device_t self, void *aux)
     90 {
     91 	struct fixedfactorclock_softc * const sc = device_private(self);
     92 	const struct fdt_attach_args *faa = aux;
     93 	const int phandle = faa->faa_phandle;
     94 	const char *name;
     95 
     96 	sc->sc_dev = self;
     97 	sc->sc_phandle = phandle;
     98 	sc->sc_clkdom.funcs = &fixedfactorclock_clk_funcs;
     99 	sc->sc_clkdom.priv = sc;
    100 
    101 	of_getprop_uint32(phandle, "clock-div", &sc->sc_clk.div);
    102 	of_getprop_uint32(phandle, "clock-mult", &sc->sc_clk.mult);
    103 
    104 	if (sc->sc_clk.div == 0 || sc->sc_clk.mult == 0) {
    105 		aprint_error(": invalid properties\n");
    106 		return;
    107 	}
    108 
    109 	name = fdtbus_get_string(phandle, "clock-output-names");
    110 	if (name == NULL)
    111 		name = faa->faa_name;
    112 
    113 	sc->sc_clk.base.domain = &sc->sc_clkdom;
    114 	sc->sc_clk.base.name = name;
    115 
    116 	aprint_naive("\n");
    117 	aprint_normal(": x%u /%u fixed-factor clock\n",
    118 	    sc->sc_clk.mult, sc->sc_clk.div);
    119 
    120 	fdtbus_register_clock_controller(self, phandle,
    121 	    &fixedfactorclock_fdt_funcs);
    122 }
    123 
    124 static struct clk *
    125 fixedfactorclock_decode(device_t dev, const void *data, size_t len)
    126 {
    127 	struct fixedfactorclock_softc * const sc = device_private(dev);
    128 
    129 	/* #clock-cells for a fixed factor clock is always 0 */
    130 	if (len != 0)
    131 		return NULL;
    132 
    133 	return &sc->sc_clk.base;
    134 }
    135 
    136 static struct clk *
    137 fixedfactorclock_get(void *priv, const char *name)
    138 {
    139 	struct fixedfactorclock_softc * const sc = priv;
    140 
    141 	if (strcmp(name, sc->sc_clk.base.name) != 0)
    142 		return NULL;
    143 
    144 	return &sc->sc_clk.base;
    145 }
    146 
    147 static void
    148 fixedfactorclock_put(void *priv, struct clk *clk)
    149 {
    150 }
    151 
    152 static u_int
    153 fixedfactorclock_get_rate(void *priv, struct clk *clk)
    154 {
    155 	struct fixedfactorclock_softc * const sc = priv;
    156 	struct fixedfactorclock_clk *fclk = (struct fixedfactorclock_clk *)clk;
    157 	struct clk *clkp_parent;
    158 
    159 	clkp_parent = fdtbus_clock_get_index(sc->sc_phandle, 0);
    160 	if (clkp_parent == NULL)
    161 		return 0;
    162 
    163 	return (clk_get_rate(clkp_parent) * fclk->mult) / fclk->div;
    164 }
    165