gpio.c revision 1.66 1 /* $NetBSD: gpio.c,v 1.66 2021/08/07 16:19:10 thorpej Exp $ */
2 /* $OpenBSD: gpio.c,v 1.6 2006/01/14 12:33:49 grange Exp $ */
3
4 /*
5 * Copyright (c) 2008, 2009, 2010, 2011 Marc Balmer <marc (at) msys.ch>
6 * Copyright (c) 2004, 2006 Alexander Yurchenko <grange (at) openbsd.org>
7 *
8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 */
20
21 #include <sys/cdefs.h>
22 __KERNEL_RCSID(0, "$NetBSD: gpio.c,v 1.66 2021/08/07 16:19:10 thorpej Exp $");
23
24 /*
25 * General Purpose Input/Output framework.
26 */
27
28 #include <sys/param.h>
29 #include <sys/callout.h>
30 #include <sys/systm.h>
31 #include <sys/conf.h>
32 #include <sys/device.h>
33 #include <sys/fcntl.h>
34 #include <sys/ioctl.h>
35 #include <sys/gpio.h>
36 #include <sys/kernel.h>
37 #include <sys/vnode.h>
38 #include <sys/kmem.h>
39 #include <sys/mutex.h>
40 #include <sys/condvar.h>
41 #include <sys/queue.h>
42 #include <sys/kauth.h>
43 #include <sys/module.h>
44 #include <dev/gpio/gpiovar.h>
45
46 #include "ioconf.h"
47 #include "locators.h"
48
49 #ifdef GPIO_DEBUG
50 #define DPRINTFN(n, x) do { if (gpiodebug > (n)) printf x; } while (0)
51 int gpiodebug = 0;
52 #else
53 #define DPRINTFN(n, x)
54 #endif
55 #define DPRINTF(x) DPRINTFN(0, x)
56
57 struct gpio_softc {
58 device_t sc_dev;
59
60 gpio_chipset_tag_t sc_gc; /* GPIO controller */
61 gpio_pin_t *sc_pins; /* pins array */
62 int sc_npins; /* number of pins */
63
64 kmutex_t sc_mtx;
65 kcondvar_t sc_ioctl; /* ioctl in progress */
66 int sc_ioctl_busy; /* ioctl is busy */
67 kcondvar_t sc_attach; /* attach/detach in progress */
68 int sc_attach_busy;/* busy in attach/detach */
69 #ifdef COMPAT_50
70 LIST_HEAD(, gpio_dev) sc_devs; /* devices */
71 #endif
72 LIST_HEAD(, gpio_name) sc_names; /* named pins */
73 };
74
75 static int gpio_match(device_t, cfdata_t, void *);
76 int gpio_submatch(device_t, cfdata_t, const int *, void *);
77 static void gpio_attach(device_t, device_t, void *);
78 static int gpio_rescan(device_t, const char *, const int *);
79 static void gpio_childdetached(device_t, device_t);
80 static bool gpio_resume(device_t, const pmf_qual_t *);
81 static int gpio_detach(device_t, int);
82 static int gpio_search(device_t, cfdata_t, const int *, void *);
83 static int gpio_print(void *, const char *);
84 static int gpio_pinbyname(struct gpio_softc *, char *);
85 static int gpio_ioctl(struct gpio_softc *, u_long, void *, int,
86 struct lwp *);
87
88 #ifdef COMPAT_50
89 /* Old API */
90 static int gpio_ioctl_oapi(struct gpio_softc *, u_long, void *, int,
91 kauth_cred_t);
92 #endif
93
94 CFATTACH_DECL3_NEW(gpio, sizeof(struct gpio_softc),
95 gpio_match, gpio_attach, gpio_detach, NULL, gpio_rescan,
96 gpio_childdetached, DVF_DETACH_SHUTDOWN);
97
98 dev_type_open(gpioopen);
99 dev_type_close(gpioclose);
100 dev_type_ioctl(gpioioctl);
101 dev_type_ioctl(gpioioctl_locked);
102
103 const struct cdevsw gpio_cdevsw = {
104 .d_open = gpioopen,
105 .d_close = gpioclose,
106 .d_read = noread,
107 .d_write = nowrite,
108 .d_ioctl = gpioioctl,
109 .d_stop = nostop,
110 .d_tty = notty,
111 .d_poll = nopoll,
112 .d_mmap = nommap,
113 .d_kqfilter = nokqfilter,
114 .d_discard = nodiscard,
115 .d_flag = D_OTHER | D_MPSAFE
116 };
117
118 static int
119 gpio_match(device_t parent, cfdata_t cf, void *aux)
120 {
121 return 1;
122 }
123
124 int
125 gpio_submatch(device_t parent, cfdata_t cf, const int *ip, void *aux)
126 {
127 struct gpio_attach_args *ga = aux;
128
129 if (ga->ga_offset == -1)
130 return 0;
131
132 return strcmp(ga->ga_dvname, cf->cf_name) == 0;
133 }
134
135 static bool
136 gpio_resume(device_t self, const pmf_qual_t *qual)
137 {
138 struct gpio_softc *sc = device_private(self);
139 int pin;
140
141 for (pin = 0; pin < sc->sc_npins; pin++) {
142 gpiobus_pin_ctl(sc->sc_gc, pin, sc->sc_pins[pin].pin_flags);
143 gpiobus_pin_write(sc->sc_gc, pin, sc->sc_pins[pin].pin_state);
144 }
145 return true;
146 }
147
148 static void
149 gpio_childdetached(device_t self, device_t child)
150 {
151 #ifdef COMPAT_50
152 struct gpio_dev *gdev;
153 struct gpio_softc *sc;
154 int error;
155
156 /*
157 * gpio_childetached is serialized because it can be entered in
158 * different ways concurrently, e.g. via the GPIODETACH ioctl and
159 * drvctl(8) or modunload(8).
160 */
161 sc = device_private(self);
162 error = 0;
163 mutex_enter(&sc->sc_mtx);
164 while (sc->sc_attach_busy) {
165 error = cv_wait_sig(&sc->sc_attach, &sc->sc_mtx);
166 if (error)
167 break;
168 }
169 if (!error)
170 sc->sc_attach_busy = 1;
171 mutex_exit(&sc->sc_mtx);
172 if (error)
173 return;
174
175 LIST_FOREACH(gdev, &sc->sc_devs, sc_next)
176 if (gdev->sc_dev == child) {
177 LIST_REMOVE(gdev, sc_next);
178 kmem_free(gdev, sizeof(struct gpio_dev));
179 break;
180 }
181
182 mutex_enter(&sc->sc_mtx);
183 sc->sc_attach_busy = 0;
184 cv_signal(&sc->sc_attach);
185 mutex_exit(&sc->sc_mtx);
186 #endif
187 }
188
189 static int
190 gpio_rescan(device_t self, const char *ifattr, const int *locators)
191 {
192
193 config_search(self, NULL,
194 CFARGS(.search = gpio_search));
195
196 return 0;
197 }
198
199 static void
200 gpio_attach(device_t parent, device_t self, void *aux)
201 {
202 struct gpio_softc *sc = device_private(self);
203 struct gpiobus_attach_args *gba = aux;
204 struct gpio_name *nm;
205 int pin;
206
207 sc->sc_dev = self;
208 sc->sc_gc = gba->gba_gc;
209 sc->sc_pins = gba->gba_pins;
210 sc->sc_npins = gba->gba_npins;
211
212 aprint_normal(": %d pins\n", sc->sc_npins);
213 aprint_naive("\n");
214
215 /* Configure default pin names */
216 for (pin = 0; pin < sc->sc_npins; pin++) {
217 if (sc->sc_pins[pin].pin_defname[0] == '\0')
218 continue;
219 nm = kmem_alloc(sizeof(*nm), KM_SLEEP);
220 strlcpy(nm->gp_name, sc->sc_pins[pin].pin_defname,
221 sizeof(nm->gp_name));
222 nm->gp_pin = pin;
223 LIST_INSERT_HEAD(&sc->sc_names, nm, gp_next);
224 }
225
226 if (!pmf_device_register(self, NULL, gpio_resume))
227 aprint_error_dev(self, "couldn't establish power handler\n");
228 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_VM);
229 cv_init(&sc->sc_ioctl, "gpioctl");
230 cv_init(&sc->sc_attach, "gpioatch");
231 /*
232 * Attach all devices that can be connected to the GPIO pins
233 * described in the kernel configuration file.
234 */
235 gpio_rescan(self, "gpio", NULL);
236 }
237
238 static int
239 gpio_detach(device_t self, int flags)
240 {
241 struct gpio_softc *sc;
242 int rc;
243
244 sc = device_private(self);
245
246 if ((rc = config_detach_children(self, flags)) != 0)
247 return rc;
248 mutex_destroy(&sc->sc_mtx);
249 cv_destroy(&sc->sc_ioctl);
250 #if 0
251 int maj, mn;
252
253 /* Locate the major number */
254 for (maj = 0; maj < nchrdev; maj++)
255 if (cdevsw[maj].d_open == gpioopen)
256 break;
257
258 /* Nuke the vnodes for any open instances (calls close) */
259 mn = device_unit(self);
260 vdevgone(maj, mn, mn, VCHR);
261 #endif
262 return 0;
263 }
264
265 static int
266 gpio_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux)
267 {
268 struct gpio_attach_args ga;
269 size_t namlen;
270
271 ga.ga_gpio = device_private(parent);
272 ga.ga_offset = cf->cf_loc[GPIOCF_OFFSET];
273 ga.ga_mask = cf->cf_loc[GPIOCF_MASK];
274 ga.ga_flags = cf->cf_loc[GPIOCF_FLAG];
275 namlen = strlen(cf->cf_name) + 1;
276 ga.ga_dvname = kmem_alloc(namlen, KM_SLEEP);
277 strcpy(ga.ga_dvname, cf->cf_name);
278
279 if (config_probe(parent, cf, &ga))
280 config_attach(parent, cf, &ga, gpio_print, CFARGS_NONE);
281 kmem_free(ga.ga_dvname, namlen);
282 return 0;
283 }
284
285 int
286 gpio_print(void *aux, const char *pnp)
287 {
288 struct gpio_attach_args *ga = aux;
289 int i;
290
291 aprint_normal(" pins");
292 for (i = 0; i < 32; i++)
293 if (ga->ga_mask & (1 << i))
294 aprint_normal(" %d", ga->ga_offset + i);
295
296 return UNCONF;
297 }
298
299 int
300 gpiobus_print(void *aux, const char *pnp)
301 {
302 #if 0
303 struct gpiobus_attach_args *gba = aux;
304 #endif
305 if (pnp != NULL)
306 aprint_normal("gpiobus at %s", pnp);
307
308 return UNCONF;
309 }
310
311 void *
312 gpio_find_device(const char *name)
313 {
314 device_t gpio_dev;
315 gpio_dev = device_find_by_xname(name);
316 if (gpio_dev == NULL)
317 return NULL;
318 return device_private(gpio_dev);
319 }
320
321 const char *
322 gpio_get_name(void *gpio)
323 {
324 struct gpio_softc *sc = gpio;
325 return device_xname(sc->sc_dev);
326 }
327
328 /* return 1 if all pins can be mapped, 0 if not */
329 int
330 gpio_pin_can_map(void *gpio, int offset, uint32_t mask)
331 {
332 struct gpio_softc *sc = gpio;
333 int npins, pin, i;
334
335 npins = gpio_npins(mask);
336 if (npins > sc->sc_npins)
337 return 0;
338
339 for (npins = 0, i = 0; i < 32; i++)
340 if (mask & (1 << i)) {
341 pin = offset + i;
342 if (pin < 0 || pin >= sc->sc_npins)
343 return 0;
344 if (sc->sc_pins[pin].pin_mapped)
345 return 0;
346 }
347
348 return 1;
349 }
350
351 int
352 gpio_pin_map(void *gpio, int offset, uint32_t mask, struct gpio_pinmap *map)
353 {
354 struct gpio_softc *sc = gpio;
355 int npins, pin, i;
356
357 npins = gpio_npins(mask);
358 if (npins > sc->sc_npins)
359 return 1;
360
361 for (npins = 0, i = 0; i < 32; i++)
362 if (mask & (1 << i)) {
363 pin = offset + i;
364 if (pin < 0 || pin >= sc->sc_npins)
365 return 1;
366 if (sc->sc_pins[pin].pin_mapped)
367 return 1;
368 sc->sc_pins[pin].pin_mapped = 1;
369 map->pm_map[npins++] = pin;
370 }
371 map->pm_size = npins;
372
373 return 0;
374 }
375
376 void
377 gpio_pin_unmap(void *gpio, struct gpio_pinmap *map)
378 {
379 struct gpio_softc *sc = gpio;
380 int pin, i;
381
382 for (i = 0; i < map->pm_size; i++) {
383 pin = map->pm_map[i];
384 sc->sc_pins[pin].pin_mapped = 0;
385 }
386 }
387
388 int
389 gpio_pin_read(void *gpio, struct gpio_pinmap *map, int pin)
390 {
391 struct gpio_softc *sc = gpio;
392
393 return gpiobus_pin_read(sc->sc_gc, map->pm_map[pin]);
394 }
395
396 void
397 gpio_pin_write(void *gpio, struct gpio_pinmap *map, int pin, int value)
398 {
399 struct gpio_softc *sc = gpio;
400
401 gpiobus_pin_write(sc->sc_gc, map->pm_map[pin], value);
402 sc->sc_pins[map->pm_map[pin]].pin_state = value;
403 }
404
405 int
406 gpio_pin_get_conf(void *gpio, struct gpio_pinmap *map, int pin)
407 {
408 struct gpio_softc *sc = gpio;
409 int rv;
410
411 mutex_enter(&sc->sc_mtx);
412 rv = sc->sc_pins[map->pm_map[pin]].pin_flags;
413 mutex_exit(&sc->sc_mtx);
414
415 return (rv);
416 }
417
418 bool
419 gpio_pin_set_conf(void *gpio, struct gpio_pinmap *map, int pin, int flags)
420 {
421 struct gpio_softc *sc = gpio;
422 int checkflags = flags & GPIO_PIN_HWCAPS;
423
424 if ((sc->sc_pins[map->pm_map[pin]].pin_caps & checkflags) != checkflags)
425 return (false);
426
427 gpio_pin_ctl(gpio, map, pin, flags);
428
429 return (true);
430 }
431
432 void
433 gpio_pin_ctl(void *gpio, struct gpio_pinmap *map, int pin, int flags)
434 {
435 struct gpio_softc *sc = gpio;
436
437 /* loosey-goosey version of gpio_pin_set_conf(). */
438
439 mutex_enter(&sc->sc_mtx);
440 gpiobus_pin_ctl(sc->sc_gc, map->pm_map[pin], flags);
441 sc->sc_pins[map->pm_map[pin]].pin_flags = flags;
442 mutex_exit(&sc->sc_mtx);
443 }
444
445 int
446 gpio_pin_caps(void *gpio, struct gpio_pinmap *map, int pin)
447 {
448 struct gpio_softc *sc = gpio;
449
450 return sc->sc_pins[map->pm_map[pin]].pin_caps;
451 }
452
453 int
454 gpio_pin_intrcaps(void *gpio, struct gpio_pinmap *map, int pin)
455 {
456 struct gpio_softc *sc = gpio;
457
458 return sc->sc_pins[map->pm_map[pin]].pin_intrcaps;
459 }
460
461 static int
462 gpio_irqmode_sanitize(int irqmode)
463 {
464 int has_edge, has_level;
465
466 has_edge = irqmode & GPIO_INTR_EDGE_MASK;
467 has_level = irqmode & GPIO_INTR_LEVEL_MASK;
468
469 /* Must specify an interrupt mode. */
470 if ((irqmode & GPIO_INTR_MODE_MASK) == 0)
471 return (0);
472
473 /* Can't specify edge and level together */
474 if (has_level && has_edge)
475 return (0);
476
477 /* "Be liberal in what you accept..." */
478 if (has_edge) {
479 if (irqmode & GPIO_INTR_DOUBLE_EDGE) {
480 /* if DOUBLE is set, just pass through DOUBLE */
481 irqmode = (irqmode & ~GPIO_INTR_EDGE_MASK) |
482 GPIO_INTR_DOUBLE_EDGE;
483 } else if ((irqmode ^
484 (GPIO_INTR_POS_EDGE | GPIO_INTR_NEG_EDGE)) == 0) {
485 /* both POS and NEG set; treat as DOUBLE */
486 irqmode = (irqmode & ~GPIO_INTR_EDGE_MASK) |
487 GPIO_INTR_DOUBLE_EDGE;
488 }
489 } else {
490 /* Can't specify both levels together. */
491 if (has_level == GPIO_INTR_LEVEL_MASK)
492 return (0);
493 }
494
495 return (irqmode);
496 }
497
498 bool
499 gpio_pin_irqmode_issupported(void *gpio, struct gpio_pinmap *map,
500 int pin, int irqmode)
501 {
502 struct gpio_softc *sc = gpio;
503 int match;
504
505 irqmode = gpio_irqmode_sanitize(irqmode) & GPIO_INTR_MODE_MASK;
506
507 /* Make sure the pin can do what is being asked. */
508 match = sc->sc_pins[map->pm_map[pin]].pin_intrcaps & irqmode;
509
510 return (irqmode && irqmode == match);
511 }
512
513 void *
514 gpio_intr_establish(void *gpio, struct gpio_pinmap *map, int pin, int ipl,
515 int irqmode, int (*func)(void *), void *arg)
516 {
517 struct gpio_softc *sc = gpio;
518
519 if (sc->sc_gc->gp_intr_establish == NULL)
520 return (NULL);
521
522 irqmode = gpio_irqmode_sanitize(irqmode);
523 if (irqmode == 0)
524 return (NULL);
525
526 if (! gpio_pin_irqmode_issupported(gpio, map, pin, irqmode))
527 return (NULL);
528
529 /* XXX Right now, everything has to be at IPL_VM. */
530 if (ipl != IPL_VM)
531 return (NULL);
532
533 return ((*sc->sc_gc->gp_intr_establish)(sc->sc_gc->gp_cookie,
534 sc->sc_pins[map->pm_map[pin]].pin_num, ipl, irqmode, func, arg));
535 }
536
537 void
538 gpio_intr_disestablish(void *gpio, void *ih)
539 {
540 struct gpio_softc *sc = gpio;
541
542 if (sc->sc_gc->gp_intr_disestablish != NULL && ih != NULL)
543 (*sc->sc_gc->gp_intr_disestablish)(sc->sc_gc->gp_cookie, ih);
544 }
545
546 bool
547 gpio_intr_str(void *gpio, struct gpio_pinmap *map, int pin, int irqmode,
548 char *intrstr, size_t intrstrlen)
549 {
550 struct gpio_softc *sc = gpio;
551 const char *mode;
552 char hwstr[64];
553
554 if (sc->sc_gc->gp_intr_str == NULL)
555 return (false);
556
557 irqmode = gpio_irqmode_sanitize(irqmode);
558 if (irqmode == 0)
559 return (false);
560
561 if (irqmode & GPIO_INTR_DOUBLE_EDGE)
562 mode = "double edge";
563 else if (irqmode & GPIO_INTR_POS_EDGE)
564 mode = "positive edge";
565 else if (irqmode & GPIO_INTR_NEG_EDGE)
566 mode = "negative edge";
567 else if (irqmode & GPIO_INTR_HIGH_LEVEL)
568 mode = "high level";
569 else if (irqmode & GPIO_INTR_LOW_LEVEL)
570 mode = "low level";
571 else
572 return (false);
573
574 if (! (*sc->sc_gc->gp_intr_str)(sc->sc_gc->gp_cookie,
575 sc->sc_pins[map->pm_map[pin]].pin_num,
576 irqmode, hwstr, sizeof(hwstr)))
577 return (false);
578
579 (void) snprintf(intrstr, intrstrlen, "%s (%s)", hwstr, mode);
580
581 return (true);
582 }
583
584 int
585 gpio_npins(uint32_t mask)
586 {
587 int npins, i;
588
589 for (npins = 0, i = 0; i < 32; i++)
590 if (mask & (1 << i))
591 npins++;
592
593 return npins;
594 }
595
596 int
597 gpio_lock(void *data)
598 {
599 struct gpio_softc *sc;
600 int error;
601
602 error = 0;
603 sc = data;
604 mutex_enter(&sc->sc_mtx);
605 while (sc->sc_ioctl_busy) {
606 error = cv_wait_sig(&sc->sc_ioctl, &sc->sc_mtx);
607 if (error)
608 break;
609 }
610 if (!error)
611 sc->sc_ioctl_busy = 1;
612 mutex_exit(&sc->sc_mtx);
613 return error;
614 }
615
616 void
617 gpio_unlock(void *data)
618 {
619 struct gpio_softc *sc;
620
621 sc = data;
622 mutex_enter(&sc->sc_mtx);
623 sc->sc_ioctl_busy = 0;
624 cv_signal(&sc->sc_ioctl);
625 mutex_exit(&sc->sc_mtx);
626 }
627
628 int
629 gpioopen(dev_t dev, int flag, int mode, struct lwp *l)
630 {
631 struct gpio_softc *sc;
632
633 sc = device_lookup_private(&gpio_cd, minor(dev));
634 if (sc == NULL)
635 return ENXIO;
636
637 return gpiobus_open(sc->sc_gc, sc->sc_dev);
638 }
639
640 int
641 gpioclose(dev_t dev, int flag, int mode, struct lwp *l)
642 {
643 struct gpio_softc *sc;
644
645 sc = device_lookup_private(&gpio_cd, minor(dev));
646 return gpiobus_close(sc->sc_gc, sc->sc_dev);
647 }
648
649 static int
650 gpio_pinbyname(struct gpio_softc *sc, char *gp_name)
651 {
652 struct gpio_name *nm;
653
654 LIST_FOREACH(nm, &sc->sc_names, gp_next)
655 if (!strcmp(nm->gp_name, gp_name))
656 return nm->gp_pin;
657 return -1;
658 }
659
660 int
661 gpioioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l)
662 {
663 int error;
664 struct gpio_softc *sc;
665
666 sc = device_lookup_private(&gpio_cd, minor(dev));
667
668 error = gpio_lock(sc);
669 if (error)
670 return error;
671
672 error = gpio_ioctl(sc, cmd, data, flag, l);
673 gpio_unlock(sc);
674 return error;
675 }
676
677 static int
678 gpio_ioctl(struct gpio_softc *sc, u_long cmd, void *data, int flag,
679 struct lwp *l)
680 {
681 gpio_chipset_tag_t gc;
682 struct gpio_info *info;
683 struct gpio_attach *attach;
684 struct gpio_attach_args ga;
685 struct gpio_req *req;
686 struct gpio_name *nm;
687 struct gpio_set *set;
688 #ifdef COMPAT_50
689 struct gpio_dev *gdev;
690 #endif
691 device_t dv;
692 cfdata_t cf;
693 kauth_cred_t cred;
694 int locs[GPIOCF_NLOCS];
695 int error, pin, value, flags, npins;
696
697 gc = sc->sc_gc;
698 ga.ga_flags = 0;
699
700 if (cmd != GPIOINFO && !device_is_active(sc->sc_dev)) {
701 DPRINTF(("%s: device is not active\n",
702 device_xname(sc->sc_dev)));
703 return EBUSY;
704 }
705
706 cred = kauth_cred_get();
707
708 switch (cmd) {
709 case GPIOINFO:
710 info = data;
711 if (!kauth_authorize_device(cred, KAUTH_DEVICE_GPIO_PINSET,
712 NULL, NULL, NULL, NULL))
713 info->gpio_npins = sc->sc_npins;
714 else {
715 for (pin = npins = 0; pin < sc->sc_npins; pin++)
716 if (sc->sc_pins[pin].pin_flags & GPIO_PIN_SET)
717 ++npins;
718 info->gpio_npins = npins;
719 }
720 break;
721 case GPIOREAD:
722 req = data;
723
724 if (req->gp_name[0] != '\0')
725 req->gp_pin = gpio_pinbyname(sc, req->gp_name);
726 pin = req->gp_pin;
727
728 if (pin < 0 || pin >= sc->sc_npins)
729 return EINVAL;
730
731 if (!(sc->sc_pins[pin].pin_flags & GPIO_PIN_SET) &&
732 kauth_authorize_device(cred, KAUTH_DEVICE_GPIO_PINSET,
733 NULL, NULL, NULL, NULL))
734 return EPERM;
735
736 /* return read value */
737 req->gp_value = gpiobus_pin_read(gc, pin);
738 LIST_FOREACH(nm, &sc->sc_names, gp_next)
739 if (nm->gp_pin == pin) {
740 strlcpy(req->gp_name, nm->gp_name, GPIOMAXNAME);
741 break;
742 }
743 break;
744 case GPIOWRITE:
745 if ((flag & FWRITE) == 0)
746 return EBADF;
747
748 req = data;
749
750 if (req->gp_name[0] != '\0')
751 pin = gpio_pinbyname(sc, req->gp_name);
752 else
753 pin = req->gp_pin;
754
755 if (pin < 0 || pin >= sc->sc_npins)
756 return EINVAL;
757
758 if (sc->sc_pins[pin].pin_mapped)
759 return EBUSY;
760
761 if (!(sc->sc_pins[pin].pin_flags & GPIO_PIN_SET) &&
762 kauth_authorize_device(cred, KAUTH_DEVICE_GPIO_PINSET,
763 NULL, NULL, NULL, NULL))
764 return EPERM;
765
766 value = req->gp_value;
767 if (value != GPIO_PIN_LOW && value != GPIO_PIN_HIGH)
768 return EINVAL;
769
770 /* return old value */
771 req->gp_value = gpiobus_pin_read(gc, pin);
772 gpiobus_pin_write(gc, pin, value);
773 /* update current value */
774 sc->sc_pins[pin].pin_state = value;
775 break;
776 case GPIOTOGGLE:
777 if ((flag & FWRITE) == 0)
778 return EBADF;
779
780 req = data;
781
782 if (req->gp_name[0] != '\0')
783 pin = gpio_pinbyname(sc, req->gp_name);
784 else
785 pin = req->gp_pin;
786
787 if (pin < 0 || pin >= sc->sc_npins)
788 return EINVAL;
789
790 if (sc->sc_pins[pin].pin_mapped)
791 return EBUSY;
792
793 if (!(sc->sc_pins[pin].pin_flags & GPIO_PIN_SET) &&
794 kauth_authorize_device(cred, KAUTH_DEVICE_GPIO_PINSET,
795 NULL, NULL, NULL, NULL))
796 return EPERM;
797
798 value = (sc->sc_pins[pin].pin_state == GPIO_PIN_LOW ?
799 GPIO_PIN_HIGH : GPIO_PIN_LOW);
800 gpiobus_pin_write(gc, pin, value);
801 /* return old value */
802 req->gp_value = sc->sc_pins[pin].pin_state;
803 /* update current value */
804 sc->sc_pins[pin].pin_state = value;
805 break;
806 case GPIOATTACH:
807 attach = data;
808 ga.ga_flags = attach->ga_flags;
809 #ifdef COMPAT_50
810 /* FALLTHROUGH */
811 case GPIOATTACH50:
812 /*
813 * The double assignment to 'attach' in case of GPIOATTACH
814 * and COMPAT_50 is on purpose. It ensures backward
815 * compatability in case we are called through the old
816 * GPIOATTACH50 ioctl(2), which had not the ga_flags field
817 * in struct gpio_attach.
818 */
819 attach = data;
820 #endif
821 if (kauth_authorize_device(cred, KAUTH_DEVICE_GPIO_PINSET,
822 NULL, NULL, NULL, NULL))
823 return EPERM;
824
825 /* do not try to attach if the pins are already mapped */
826 if (!gpio_pin_can_map(sc, attach->ga_offset, attach->ga_mask))
827 return EBUSY;
828
829 error = 0;
830 mutex_enter(&sc->sc_mtx);
831 while (sc->sc_attach_busy) {
832 error = cv_wait_sig(&sc->sc_attach, &sc->sc_mtx);
833 if (error)
834 break;
835 }
836 if (!error)
837 sc->sc_attach_busy = 1;
838 mutex_exit(&sc->sc_mtx);
839 if (error)
840 return EBUSY;
841
842 ga.ga_gpio = sc;
843 /* Don't access attach->ga_flags here. */
844 ga.ga_dvname = attach->ga_dvname;
845 ga.ga_offset = attach->ga_offset;
846 ga.ga_mask = attach->ga_mask;
847 DPRINTF(("%s: attach %s with offset %d, mask "
848 "0x%02x, and flags 0x%02x\n", device_xname(sc->sc_dev),
849 ga.ga_dvname, ga.ga_offset, ga.ga_mask, ga.ga_flags));
850
851 locs[GPIOCF_OFFSET] = ga.ga_offset;
852 locs[GPIOCF_MASK] = ga.ga_mask;
853 locs[GPIOCF_FLAG] = ga.ga_flags;
854
855 cf = config_search(sc->sc_dev, &ga,
856 CFARGS(.locators = locs));
857 if (cf != NULL) {
858 dv = config_attach(sc->sc_dev, cf, &ga,
859 gpiobus_print,
860 CFARGS(.locators = locs));
861 #ifdef COMPAT_50
862 if (dv != NULL) {
863 gdev = kmem_alloc(sizeof(struct gpio_dev),
864 KM_SLEEP);
865 gdev->sc_dev = dv;
866 LIST_INSERT_HEAD(&sc->sc_devs, gdev, sc_next);
867 } else
868 error = EINVAL;
869 #else
870 if (dv == NULL)
871 error = EINVAL;
872 #endif
873 } else
874 error = EINVAL;
875 mutex_enter(&sc->sc_mtx);
876 sc->sc_attach_busy = 0;
877 cv_signal(&sc->sc_attach);
878 mutex_exit(&sc->sc_mtx);
879 return error;
880 case GPIOSET:
881 if (kauth_authorize_device(cred, KAUTH_DEVICE_GPIO_PINSET,
882 NULL, NULL, NULL, NULL))
883 return EPERM;
884
885 set = data;
886
887 if (set->gp_name[0] != '\0')
888 pin = gpio_pinbyname(sc, set->gp_name);
889 else
890 pin = set->gp_pin;
891
892 if (pin < 0 || pin >= sc->sc_npins)
893 return EINVAL;
894 flags = set->gp_flags;
895
896 /* check that the controller supports all requested flags */
897 if ((flags & sc->sc_pins[pin].pin_caps) != flags)
898 return ENODEV;
899 flags = set->gp_flags;
900
901 set->gp_caps = sc->sc_pins[pin].pin_caps;
902 /* return old value */
903 set->gp_flags = sc->sc_pins[pin].pin_flags;
904
905 if (flags > 0) {
906 flags |= GPIO_PIN_SET;
907 gpiobus_pin_ctl(gc, pin, flags);
908 /* update current value */
909 sc->sc_pins[pin].pin_flags = flags;
910 }
911
912 /* rename pin or new pin? */
913 if (set->gp_name2[0] != '\0') {
914 struct gpio_name *gnm;
915
916 gnm = NULL;
917 LIST_FOREACH(nm, &sc->sc_names, gp_next) {
918 if (!strcmp(nm->gp_name, set->gp_name2) &&
919 nm->gp_pin != pin)
920 return EINVAL; /* duplicate name */
921 if (nm->gp_pin == pin)
922 gnm = nm;
923 }
924 if (gnm != NULL)
925 strlcpy(gnm->gp_name, set->gp_name2,
926 sizeof(gnm->gp_name));
927 else {
928 nm = kmem_alloc(sizeof(struct gpio_name),
929 KM_SLEEP);
930 strlcpy(nm->gp_name, set->gp_name2,
931 sizeof(nm->gp_name));
932 nm->gp_pin = set->gp_pin;
933 LIST_INSERT_HEAD(&sc->sc_names, nm, gp_next);
934 }
935 }
936 break;
937 case GPIOUNSET:
938 if (kauth_authorize_device(cred, KAUTH_DEVICE_GPIO_PINSET,
939 NULL, NULL, NULL, NULL))
940 return EPERM;
941
942 set = data;
943 if (set->gp_name[0] != '\0')
944 pin = gpio_pinbyname(sc, set->gp_name);
945 else
946 pin = set->gp_pin;
947
948 if (pin < 0 || pin >= sc->sc_npins)
949 return EINVAL;
950 if (sc->sc_pins[pin].pin_mapped)
951 return EBUSY;
952 if (!(sc->sc_pins[pin].pin_flags & GPIO_PIN_SET))
953 return EINVAL;
954
955 LIST_FOREACH(nm, &sc->sc_names, gp_next) {
956 if (nm->gp_pin == pin) {
957 LIST_REMOVE(nm, gp_next);
958 kmem_free(nm, sizeof(struct gpio_name));
959 break;
960 }
961 }
962 sc->sc_pins[pin].pin_flags &= ~GPIO_PIN_SET;
963 break;
964 default:
965 #ifdef COMPAT_50
966 /* Try the old API */
967 DPRINTF(("%s: trying the old API\n", device_xname(sc->sc_dev)));
968 return gpio_ioctl_oapi(sc, cmd, data, flag, cred);
969 #else
970 return ENOTTY;
971 #endif
972 }
973 return 0;
974 }
975
976 #ifdef COMPAT_50
977 static int
978 gpio_ioctl_oapi(struct gpio_softc *sc, u_long cmd, void *data, int flag,
979 kauth_cred_t cred)
980 {
981 gpio_chipset_tag_t gc;
982 struct gpio_pin_op *op;
983 struct gpio_pin_ctl *ctl;
984 struct gpio_attach *attach;
985 struct gpio_dev *gdev;
986
987 int error, pin, value, flags;
988
989 gc = sc->sc_gc;
990
991 switch (cmd) {
992 case GPIOPINREAD:
993 op = data;
994
995 pin = op->gp_pin;
996
997 if (pin < 0 || pin >= sc->sc_npins)
998 return EINVAL;
999
1000 if (!(sc->sc_pins[pin].pin_flags & GPIO_PIN_SET) &&
1001 kauth_authorize_device(cred, KAUTH_DEVICE_GPIO_PINSET,
1002 NULL, NULL, NULL, NULL))
1003 return EPERM;
1004
1005 /* return read value */
1006 op->gp_value = gpiobus_pin_read(gc, pin);
1007 break;
1008 case GPIOPINWRITE:
1009 if ((flag & FWRITE) == 0)
1010 return EBADF;
1011
1012 op = data;
1013
1014 pin = op->gp_pin;
1015
1016 if (pin < 0 || pin >= sc->sc_npins)
1017 return EINVAL;
1018
1019 if (sc->sc_pins[pin].pin_mapped)
1020 return EBUSY;
1021
1022 if (!(sc->sc_pins[pin].pin_flags & GPIO_PIN_SET) &&
1023 kauth_authorize_device(cred, KAUTH_DEVICE_GPIO_PINSET,
1024 NULL, NULL, NULL, NULL))
1025 return EPERM;
1026
1027 value = op->gp_value;
1028 if (value != GPIO_PIN_LOW && value != GPIO_PIN_HIGH)
1029 return EINVAL;
1030
1031 gpiobus_pin_write(gc, pin, value);
1032 /* return old value */
1033 op->gp_value = sc->sc_pins[pin].pin_state;
1034 /* update current value */
1035 sc->sc_pins[pin].pin_state = value;
1036 break;
1037 case GPIOPINTOGGLE:
1038 if ((flag & FWRITE) == 0)
1039 return EBADF;
1040
1041 op = data;
1042
1043 pin = op->gp_pin;
1044
1045 if (pin < 0 || pin >= sc->sc_npins)
1046 return EINVAL;
1047
1048 if (sc->sc_pins[pin].pin_mapped)
1049 return EBUSY;
1050
1051 if (!(sc->sc_pins[pin].pin_flags & GPIO_PIN_SET) &&
1052 kauth_authorize_device(cred, KAUTH_DEVICE_GPIO_PINSET,
1053 NULL, NULL, NULL, NULL))
1054 return EPERM;
1055
1056 value = (sc->sc_pins[pin].pin_state == GPIO_PIN_LOW ?
1057 GPIO_PIN_HIGH : GPIO_PIN_LOW);
1058 gpiobus_pin_write(gc, pin, value);
1059 /* return old value */
1060 op->gp_value = sc->sc_pins[pin].pin_state;
1061 /* update current value */
1062 sc->sc_pins[pin].pin_state = value;
1063 break;
1064 case GPIOPINCTL:
1065 ctl = data;
1066
1067 if (kauth_authorize_device(cred, KAUTH_DEVICE_GPIO_PINSET,
1068 NULL, NULL, NULL, NULL))
1069 return EPERM;
1070
1071 pin = ctl->gp_pin;
1072
1073 if (pin < 0 || pin >= sc->sc_npins)
1074 return EINVAL;
1075 if (sc->sc_pins[pin].pin_mapped)
1076 return EBUSY;
1077 flags = ctl->gp_flags;
1078
1079 /* check that the controller supports all requested flags */
1080 if ((flags & sc->sc_pins[pin].pin_caps) != flags)
1081 return ENODEV;
1082
1083 ctl->gp_caps = sc->sc_pins[pin].pin_caps;
1084 /* return old value */
1085 ctl->gp_flags = sc->sc_pins[pin].pin_flags;
1086 if (flags > 0) {
1087 gpiobus_pin_ctl(gc, pin, flags);
1088 /* update current value */
1089 sc->sc_pins[pin].pin_flags = flags;
1090 }
1091 break;
1092 case GPIODETACH50:
1093 /* FALLTHOUGH */
1094 case GPIODETACH:
1095 if (kauth_authorize_device(cred, KAUTH_DEVICE_GPIO_PINSET,
1096 NULL, NULL, NULL, NULL))
1097 return EPERM;
1098
1099 error = 0;
1100 mutex_enter(&sc->sc_mtx);
1101 while (sc->sc_attach_busy) {
1102 error = cv_wait_sig(&sc->sc_attach, &sc->sc_mtx);
1103 if (error)
1104 break;
1105 }
1106 if (!error)
1107 sc->sc_attach_busy = 1;
1108 mutex_exit(&sc->sc_mtx);
1109 if (error)
1110 return EBUSY;
1111
1112 attach = data;
1113 LIST_FOREACH(gdev, &sc->sc_devs, sc_next) {
1114 if (strcmp(device_xname(gdev->sc_dev),
1115 attach->ga_dvname) == 0) {
1116 mutex_enter(&sc->sc_mtx);
1117 sc->sc_attach_busy = 0;
1118 cv_signal(&sc->sc_attach);
1119 mutex_exit(&sc->sc_mtx);
1120
1121 if (config_detach(gdev->sc_dev, 0) == 0)
1122 return 0;
1123 break;
1124 }
1125 }
1126 if (gdev == NULL) {
1127 mutex_enter(&sc->sc_mtx);
1128 sc->sc_attach_busy = 0;
1129 cv_signal(&sc->sc_attach);
1130 mutex_exit(&sc->sc_mtx);
1131 }
1132 return EINVAL;
1133
1134 default:
1135 return ENOTTY;
1136 }
1137 return 0;
1138 }
1139 #endif /* COMPAT_50 */
1140
1141 MODULE(MODULE_CLASS_DRIVER, gpio, NULL);
1142
1143 #ifdef _MODULE
1144 #include "ioconf.c"
1145 #endif
1146
1147 static int
1148 gpio_modcmd(modcmd_t cmd, void *opaque)
1149 {
1150 #ifdef _MODULE
1151 devmajor_t cmajor = NODEVMAJOR, bmajor = NODEVMAJOR;
1152 int error;
1153 #endif
1154 switch (cmd) {
1155 case MODULE_CMD_INIT:
1156 #ifdef _MODULE
1157 error = config_init_component(cfdriver_ioconf_gpio,
1158 cfattach_ioconf_gpio, cfdata_ioconf_gpio);
1159 if (error) {
1160 aprint_error("%s: unable to init component\n",
1161 gpio_cd.cd_name);
1162 return error;
1163 }
1164 error = devsw_attach(gpio_cd.cd_name, NULL, &bmajor,
1165 &gpio_cdevsw, &cmajor);
1166 if (error) {
1167 aprint_error("%s: unable to register devsw\n",
1168 gpio_cd.cd_name);
1169 return config_fini_component(cfdriver_ioconf_gpio,
1170 cfattach_ioconf_gpio, cfdata_ioconf_gpio);
1171 }
1172 #endif
1173 return 0;
1174 case MODULE_CMD_FINI:
1175 #ifdef _MODULE
1176 config_fini_component(cfdriver_ioconf_gpio,
1177 cfattach_ioconf_gpio, cfdata_ioconf_gpio);
1178 devsw_detach(NULL, &gpio_cdevsw);
1179 #endif
1180 return 0;
1181 default:
1182 return ENOTTY;
1183 }
1184 }
1185