axppmic.c revision 1.17
1 /* $NetBSD: axppmic.c,v 1.17 2019/01/02 17:28:55 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2014-2018 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: axppmic.c,v 1.17 2019/01/02 17:28:55 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/device.h> 36 #include <sys/atomic.h> 37 #include <sys/conf.h> 38 #include <sys/bus.h> 39 #include <sys/kmem.h> 40 41 #include <dev/i2c/i2cvar.h> 42 43 #include <dev/sysmon/sysmonvar.h> 44 #include <dev/sysmon/sysmon_taskq.h> 45 46 #include <dev/fdt/fdtvar.h> 47 48 #define AXP_POWER_SOURCE_REG 0x00 49 #define AXP_POWER_SOURCE_ACIN_PRESENT __BIT(7) 50 #define AXP_POWER_SOURCE_VBUS_PRESENT __BIT(5) 51 #define AXP_POWER_SOURCE_CHARGE_DIRECTION __BIT(2) 52 53 #define AXP_POWER_MODE_REG 0x01 54 #define AXP_POWER_MODE_BATT_VALID __BIT(4) 55 #define AXP_POWER_MODE_BATT_PRESENT __BIT(5) 56 #define AXP_POWER_MODE_BATT_CHARGING __BIT(6) 57 58 #define AXP_POWER_DISABLE_REG 0x32 59 #define AXP_POWER_DISABLE_CTRL __BIT(7) 60 61 #define AXP_IRQ_ENABLE_REG(n) (0x40 + (n) - 1) 62 #define AXP_IRQ1_ACIN_RAISE __BIT(6) 63 #define AXP_IRQ1_ACIN_LOWER __BIT(5) 64 #define AXP_IRQ1_VBUS_RAISE __BIT(3) 65 #define AXP_IRQ1_VBUS_LOWER __BIT(2) 66 #define AXP_IRQ_STATUS_REG(n) (0x48 + (n) - 1) 67 68 #define AXP_BATSENSE_HI_REG 0x78 69 #define AXP_BATSENSE_LO_REG 0x79 70 71 #define AXP_BATTCHG_HI_REG 0x7a 72 #define AXP_BATTCHG_LO_REG 0x7b 73 74 #define AXP_BATTDISCHG_HI_REG 0x7c 75 #define AXP_BATTDISCHG_LO_REG 0x7d 76 77 #define AXP_ADC_RAW(_hi, _lo) \ 78 (((u_int)(_hi) << 4) | ((_lo) & 0xf)) 79 80 #define AXP_FUEL_GAUGE_CTRL_REG 0xb8 81 #define AXP_FUEL_GAUGE_CTRL_EN __BIT(7) 82 83 #define AXP_BATT_CAP_REG 0xb9 84 #define AXP_BATT_CAP_VALID __BIT(7) 85 #define AXP_BATT_CAP_PERCENT __BITS(6,0) 86 87 #define AXP_BATT_MAX_CAP_HI_REG 0xe0 88 #define AXP_BATT_MAX_CAP_VALID __BIT(7) 89 #define AXP_BATT_MAX_CAP_LO_REG 0xe1 90 91 #define AXP_BATT_COULOMB_HI_REG 0xe2 92 #define AXP_BATT_COULOMB_VALID __BIT(7) 93 #define AXP_BATT_COULOMB_LO_REG 0xe3 94 95 #define AXP_COULOMB_RAW(_hi, _lo) \ 96 (((u_int)(_hi & ~__BIT(7)) << 8) | (_lo)) 97 98 #define AXP_BATT_CAP_WARN_REG 0xe6 99 #define AXP_BATT_CAP_WARN_LV1 __BITS(7,4) 100 #define AXP_BATT_CAP_WARN_LV2 __BITS(3,0) 101 102 struct axppmic_ctrl { 103 device_t c_dev; 104 105 const char * c_name; 106 u_int c_min; 107 u_int c_max; 108 u_int c_step1; 109 u_int c_step1cnt; 110 u_int c_step2; 111 u_int c_step2cnt; 112 113 uint8_t c_enable_reg; 114 uint8_t c_enable_mask; 115 116 uint8_t c_voltage_reg; 117 uint8_t c_voltage_mask; 118 }; 119 120 #define AXP_CTRL(name, min, max, step, ereg, emask, vreg, vmask) \ 121 { .c_name = (name), .c_min = (min), .c_max = (max), \ 122 .c_step1 = (step), .c_step1cnt = (((max) - (min)) / (step)) + 1, \ 123 .c_step2 = 0, .c_step2cnt = 0, \ 124 .c_enable_reg = (ereg), .c_enable_mask = (emask), \ 125 .c_voltage_reg = (vreg), .c_voltage_mask = (vmask) } 126 127 #define AXP_CTRL2(name, min, max, step1, step1cnt, step2, step2cnt, ereg, emask, vreg, vmask) \ 128 { .c_name = (name), .c_min = (min), .c_max = (max), \ 129 .c_step1 = (step1), .c_step1cnt = (step1cnt), \ 130 .c_step2 = (step2), .c_step2cnt = (step2cnt), \ 131 .c_enable_reg = (ereg), .c_enable_mask = (emask), \ 132 .c_voltage_reg = (vreg), .c_voltage_mask = (vmask) } 133 134 static const struct axppmic_ctrl axp803_ctrls[] = { 135 AXP_CTRL("dldo1", 700, 3300, 100, 136 0x12, __BIT(3), 0x15, __BITS(4,0)), 137 AXP_CTRL2("dldo2", 700, 4200, 100, 28, 200, 4, 138 0x12, __BIT(4), 0x16, __BITS(4,0)), 139 AXP_CTRL("dldo3", 700, 3300, 100, 140 0x12, __BIT(5), 0x17, __BITS(4,0)), 141 AXP_CTRL("dldo4", 700, 3300, 100, 142 0x12, __BIT(6), 0x18, __BITS(4,0)), 143 AXP_CTRL("eldo1", 700, 1900, 50, 144 0x12, __BIT(0), 0x19, __BITS(4,0)), 145 AXP_CTRL("eldo2", 700, 1900, 50, 146 0x12, __BIT(1), 0x1a, __BITS(4,0)), 147 AXP_CTRL("eldo3", 700, 1900, 50, 148 0x12, __BIT(2), 0x1b, __BITS(4,0)), 149 AXP_CTRL("fldo1", 700, 1450, 50, 150 0x13, __BIT(2), 0x1c, __BITS(3,0)), 151 AXP_CTRL("fldo2", 700, 1450, 50, 152 0x13, __BIT(3), 0x1d, __BITS(3,0)), 153 AXP_CTRL("dcdc1", 1600, 3400, 100, 154 0x10, __BIT(0), 0x20, __BITS(4,0)), 155 AXP_CTRL2("dcdc2", 500, 1300, 10, 70, 20, 5, 156 0x10, __BIT(1), 0x21, __BITS(6,0)), 157 AXP_CTRL2("dcdc3", 500, 1300, 10, 70, 20, 5, 158 0x10, __BIT(2), 0x22, __BITS(6,0)), 159 AXP_CTRL2("dcdc4", 500, 1300, 10, 70, 20, 5, 160 0x10, __BIT(3), 0x23, __BITS(6,0)), 161 AXP_CTRL2("dcdc5", 800, 1840, 10, 33, 20, 36, 162 0x10, __BIT(4), 0x24, __BITS(6,0)), 163 AXP_CTRL2("dcdc6", 600, 1520, 10, 51, 20, 21, 164 0x10, __BIT(5), 0x25, __BITS(6,0)), 165 AXP_CTRL("aldo1", 700, 3300, 100, 166 0x13, __BIT(5), 0x28, __BITS(4,0)), 167 AXP_CTRL("aldo2", 700, 3300, 100, 168 0x13, __BIT(6), 0x29, __BITS(4,0)), 169 AXP_CTRL("aldo3", 700, 3300, 100, 170 0x13, __BIT(7), 0x2a, __BITS(4,0)), 171 }; 172 173 static const struct axppmic_ctrl axp805_ctrls[] = { 174 AXP_CTRL2("dcdca", 600, 1520, 10, 51, 20, 21, 175 0x10, __BIT(0), 0x12, __BITS(6,0)), 176 AXP_CTRL("dcdcb", 1000, 2550, 50, 177 0x10, __BIT(1), 0x13, __BITS(4,0)), 178 AXP_CTRL2("dcdcc", 600, 1520, 10, 51, 20, 21, 179 0x10, __BIT(2), 0x14, __BITS(6,0)), 180 AXP_CTRL2("dcdcd", 600, 3300, 20, 46, 100, 18, 181 0x10, __BIT(3), 0x15, __BITS(5,0)), 182 AXP_CTRL("dcdce", 1100, 3400, 100, 183 0x10, __BIT(4), 0x16, __BITS(4,0)), 184 AXP_CTRL("aldo1", 700, 3300, 100, 185 0x10, __BIT(5), 0x17, __BITS(4,0)), 186 AXP_CTRL("aldo2", 700, 3400, 100, 187 0x10, __BIT(6), 0x18, __BITS(4,0)), 188 AXP_CTRL("aldo3", 700, 3300, 100, 189 0x10, __BIT(7), 0x19, __BITS(4,0)), 190 AXP_CTRL("bldo1", 700, 1900, 100, 191 0x11, __BIT(0), 0x20, __BITS(3,0)), 192 AXP_CTRL("bldo2", 700, 1900, 100, 193 0x11, __BIT(1), 0x21, __BITS(3,0)), 194 AXP_CTRL("bldo3", 700, 1900, 100, 195 0x11, __BIT(2), 0x22, __BITS(3,0)), 196 AXP_CTRL("bldo4", 700, 1900, 100, 197 0x11, __BIT(3), 0x23, __BITS(3,0)), 198 AXP_CTRL("cldo1", 700, 3300, 100, 199 0x11, __BIT(4), 0x24, __BITS(4,0)), 200 AXP_CTRL2("cldo2", 700, 4200, 100, 28, 200, 4, 201 0x11, __BIT(5), 0x25, __BITS(4,0)), 202 AXP_CTRL("cldo3", 700, 3300, 100, 203 0x11, __BIT(6), 0x26, __BITS(4,0)), 204 }; 205 206 static const struct axppmic_ctrl axp813_ctrls[] = { 207 AXP_CTRL("dldo1", 700, 3300, 100, 208 0x12, __BIT(3), 0x15, __BITS(4,0)), 209 AXP_CTRL2("dldo2", 700, 4200, 100, 28, 200, 4, 210 0x12, __BIT(4), 0x16, __BITS(4,0)), 211 AXP_CTRL("dldo3", 700, 3300, 100, 212 0x12, __BIT(5), 0x17, __BITS(4,0)), 213 AXP_CTRL("dldo4", 700, 3300, 100, 214 0x12, __BIT(6), 0x18, __BITS(4,0)), 215 AXP_CTRL("eldo1", 700, 1900, 50, 216 0x12, __BIT(0), 0x19, __BITS(4,0)), 217 AXP_CTRL("eldo2", 700, 1900, 50, 218 0x12, __BIT(1), 0x1a, __BITS(4,0)), 219 AXP_CTRL("eldo3", 700, 1900, 50, 220 0x12, __BIT(2), 0x1b, __BITS(4,0)), 221 AXP_CTRL("fldo1", 700, 1450, 50, 222 0x13, __BIT(2), 0x1c, __BITS(3,0)), 223 AXP_CTRL("fldo2", 700, 1450, 50, 224 0x13, __BIT(3), 0x1d, __BITS(3,0)), 225 AXP_CTRL("dcdc1", 1600, 3400, 100, 226 0x10, __BIT(0), 0x20, __BITS(4,0)), 227 AXP_CTRL2("dcdc2", 500, 1300, 10, 70, 20, 5, 228 0x10, __BIT(1), 0x21, __BITS(6,0)), 229 AXP_CTRL2("dcdc3", 500, 1300, 10, 70, 20, 5, 230 0x10, __BIT(2), 0x22, __BITS(6,0)), 231 AXP_CTRL2("dcdc4", 500, 1300, 10, 70, 20, 5, 232 0x10, __BIT(3), 0x23, __BITS(6,0)), 233 AXP_CTRL2("dcdc5", 800, 1840, 10, 33, 20, 36, 234 0x10, __BIT(4), 0x24, __BITS(6,0)), 235 AXP_CTRL2("dcdc6", 600, 1520, 10, 51, 20, 21, 236 0x10, __BIT(5), 0x25, __BITS(6,0)), 237 AXP_CTRL2("dcdc7", 600, 1520, 10, 51, 20, 21, 238 0x10, __BIT(6), 0x26, __BITS(6,0)), 239 AXP_CTRL("aldo1", 700, 3300, 100, 240 0x13, __BIT(5), 0x28, __BITS(4,0)), 241 AXP_CTRL("aldo2", 700, 3300, 100, 242 0x13, __BIT(6), 0x29, __BITS(4,0)), 243 AXP_CTRL("aldo3", 700, 3300, 100, 244 0x13, __BIT(7), 0x2a, __BITS(4,0)), 245 }; 246 247 struct axppmic_irq { 248 u_int reg; 249 uint8_t mask; 250 }; 251 252 #define AXPPMIC_IRQ(_reg, _mask) \ 253 { .reg = (_reg), .mask = (_mask) } 254 255 struct axppmic_config { 256 const char *name; 257 const struct axppmic_ctrl *controls; 258 u_int ncontrols; 259 u_int irq_regs; 260 bool has_battery; 261 bool has_fuel_gauge; 262 struct axppmic_irq poklirq; 263 struct axppmic_irq acinirq; 264 struct axppmic_irq vbusirq; 265 struct axppmic_irq battirq; 266 struct axppmic_irq chargeirq; 267 struct axppmic_irq chargestirq; 268 u_int batsense_step; /* uV */ 269 u_int charge_step; /* uA */ 270 u_int discharge_step; /* uA */ 271 u_int maxcap_step; /* uAh */ 272 u_int coulomb_step; /* uAh */ 273 }; 274 275 enum axppmic_sensor { 276 AXP_SENSOR_ACIN_PRESENT, 277 AXP_SENSOR_VBUS_PRESENT, 278 AXP_SENSOR_BATT_PRESENT, 279 AXP_SENSOR_BATT_CHARGING, 280 AXP_SENSOR_BATT_CHARGE_STATE, 281 AXP_SENSOR_BATT_VOLTAGE, 282 AXP_SENSOR_BATT_CHARGE_CURRENT, 283 AXP_SENSOR_BATT_DISCHARGE_CURRENT, 284 AXP_SENSOR_BATT_CAPACITY_PERCENT, 285 AXP_SENSOR_BATT_MAXIMUM_CAPACITY, 286 AXP_SENSOR_BATT_CURRENT_CAPACITY, 287 AXP_NSENSORS 288 }; 289 290 struct axppmic_softc { 291 device_t sc_dev; 292 i2c_tag_t sc_i2c; 293 i2c_addr_t sc_addr; 294 int sc_phandle; 295 296 const struct axppmic_config *sc_conf; 297 298 struct sysmon_pswitch sc_smpsw; 299 300 struct sysmon_envsys *sc_sme; 301 302 envsys_data_t sc_sensor[AXP_NSENSORS]; 303 304 u_int sc_warn_thres; 305 u_int sc_shut_thres; 306 }; 307 308 struct axpreg_softc { 309 device_t sc_dev; 310 i2c_tag_t sc_i2c; 311 i2c_addr_t sc_addr; 312 const struct axppmic_ctrl *sc_ctrl; 313 u_int sc_inuse; 314 }; 315 316 struct axpreg_attach_args { 317 const struct axppmic_ctrl *reg_ctrl; 318 int reg_phandle; 319 i2c_tag_t reg_i2c; 320 i2c_addr_t reg_addr; 321 }; 322 323 static const struct axppmic_config axp803_config = { 324 .name = "AXP803", 325 .controls = axp803_ctrls, 326 .ncontrols = __arraycount(axp803_ctrls), 327 .irq_regs = 6, 328 .has_battery = true, 329 .has_fuel_gauge = true, 330 .batsense_step = 1100, 331 .charge_step = 1000, 332 .discharge_step = 1000, 333 .maxcap_step = 1456, 334 .coulomb_step = 1456, 335 .poklirq = AXPPMIC_IRQ(5, __BIT(3)), 336 .acinirq = AXPPMIC_IRQ(1, __BITS(6,5)), 337 .vbusirq = AXPPMIC_IRQ(1, __BITS(3,2)), 338 .battirq = AXPPMIC_IRQ(2, __BITS(7,6)), 339 .chargeirq = AXPPMIC_IRQ(2, __BITS(3,2)), 340 .chargestirq = AXPPMIC_IRQ(4, __BITS(1,0)), 341 }; 342 343 static const struct axppmic_config axp805_config = { 344 .name = "AXP805/806", 345 .controls = axp805_ctrls, 346 .ncontrols = __arraycount(axp805_ctrls), 347 .irq_regs = 2, 348 .poklirq = AXPPMIC_IRQ(2, __BIT(0)), 349 }; 350 351 static const struct axppmic_config axp813_config = { 352 .name = "AXP813", 353 .controls = axp813_ctrls, 354 .ncontrols = __arraycount(axp813_ctrls), 355 .irq_regs = 6, 356 .has_battery = true, 357 .has_fuel_gauge = true, 358 .batsense_step = 1100, 359 .charge_step = 1000, 360 .discharge_step = 1000, 361 .maxcap_step = 1456, 362 .coulomb_step = 1456, 363 .poklirq = AXPPMIC_IRQ(5, __BIT(3)), 364 .acinirq = AXPPMIC_IRQ(1, __BITS(6,5)), 365 .vbusirq = AXPPMIC_IRQ(1, __BITS(3,2)), 366 .battirq = AXPPMIC_IRQ(2, __BITS(7,6)), 367 .chargeirq = AXPPMIC_IRQ(2, __BITS(3,2)), 368 .chargestirq = AXPPMIC_IRQ(4, __BITS(1,0)), 369 }; 370 371 static const struct device_compatible_entry compat_data[] = { 372 { "x-powers,axp803", (uintptr_t)&axp803_config }, 373 { "x-powers,axp805", (uintptr_t)&axp805_config }, 374 { "x-powers,axp806", (uintptr_t)&axp805_config }, 375 { "x-powers,axp813", (uintptr_t)&axp813_config }, 376 { NULL, 0 } 377 }; 378 379 static int 380 axppmic_read(i2c_tag_t tag, i2c_addr_t addr, uint8_t reg, uint8_t *val, int flags) 381 { 382 return iic_smbus_read_byte(tag, addr, reg, val, flags); 383 } 384 385 static int 386 axppmic_write(i2c_tag_t tag, i2c_addr_t addr, uint8_t reg, uint8_t val, int flags) 387 { 388 return iic_smbus_write_byte(tag, addr, reg, val, flags); 389 } 390 391 static int 392 axppmic_set_voltage(i2c_tag_t tag, i2c_addr_t addr, const struct axppmic_ctrl *c, u_int min, u_int max) 393 { 394 const int flags = (cold ? I2C_F_POLL : 0); 395 u_int vol, reg_val; 396 int nstep, error; 397 uint8_t val; 398 399 if (!c->c_voltage_mask) 400 return EINVAL; 401 402 if (min < c->c_min || min > c->c_max) 403 return EINVAL; 404 405 reg_val = 0; 406 nstep = 1; 407 vol = c->c_min; 408 409 for (nstep = 0; nstep < c->c_step1cnt && vol < min; nstep++) { 410 ++reg_val; 411 vol += c->c_step1; 412 } 413 for (nstep = 0; nstep < c->c_step2cnt && vol < min; nstep++) { 414 ++reg_val; 415 vol += c->c_step2; 416 } 417 418 if (vol > max) 419 return EINVAL; 420 421 iic_acquire_bus(tag, flags); 422 if ((error = axppmic_read(tag, addr, c->c_voltage_reg, &val, flags)) == 0) { 423 val &= ~c->c_voltage_mask; 424 val |= __SHIFTIN(reg_val, c->c_voltage_mask); 425 error = axppmic_write(tag, addr, c->c_voltage_reg, val, flags); 426 } 427 iic_release_bus(tag, flags); 428 429 return error; 430 } 431 432 static int 433 axppmic_get_voltage(i2c_tag_t tag, i2c_addr_t addr, const struct axppmic_ctrl *c, u_int *pvol) 434 { 435 const int flags = (cold ? I2C_F_POLL : 0); 436 int reg_val, error; 437 uint8_t val; 438 439 if (!c->c_voltage_mask) 440 return EINVAL; 441 442 iic_acquire_bus(tag, flags); 443 error = axppmic_read(tag, addr, c->c_voltage_reg, &val, flags); 444 iic_release_bus(tag, flags); 445 if (error) 446 return error; 447 448 reg_val = __SHIFTOUT(val, c->c_voltage_mask); 449 if (reg_val < c->c_step1cnt) { 450 *pvol = c->c_min + reg_val * c->c_step1; 451 } else { 452 *pvol = c->c_min + (c->c_step1cnt * c->c_step1) + 453 ((reg_val - c->c_step1cnt) * c->c_step2); 454 } 455 456 return 0; 457 } 458 459 static void 460 axppmic_power_poweroff(device_t dev) 461 { 462 struct axppmic_softc *sc = device_private(dev); 463 464 delay(1000000); 465 466 iic_acquire_bus(sc->sc_i2c, I2C_F_POLL); 467 axppmic_write(sc->sc_i2c, sc->sc_addr, AXP_POWER_DISABLE_REG, AXP_POWER_DISABLE_CTRL, I2C_F_POLL); 468 iic_release_bus(sc->sc_i2c, I2C_F_POLL); 469 } 470 471 static struct fdtbus_power_controller_func axppmic_power_funcs = { 472 .poweroff = axppmic_power_poweroff, 473 }; 474 475 static void 476 axppmic_task_shut(void *priv) 477 { 478 struct axppmic_softc *sc = priv; 479 480 sysmon_pswitch_event(&sc->sc_smpsw, PSWITCH_EVENT_PRESSED); 481 } 482 483 static void 484 axppmic_sensor_update(struct sysmon_envsys *sme, envsys_data_t *e) 485 { 486 struct axppmic_softc *sc = sme->sme_cookie; 487 const struct axppmic_config *c = sc->sc_conf; 488 const int flags = I2C_F_POLL; 489 uint8_t val, lo, hi; 490 491 e->state = ENVSYS_SINVALID; 492 493 const bool battery_present = 494 sc->sc_sensor[AXP_SENSOR_BATT_PRESENT].state == ENVSYS_SVALID && 495 sc->sc_sensor[AXP_SENSOR_BATT_PRESENT].value_cur == 1; 496 497 switch (e->private) { 498 case AXP_SENSOR_ACIN_PRESENT: 499 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_SOURCE_REG, &val, flags) == 0) { 500 e->state = ENVSYS_SVALID; 501 e->value_cur = !!(val & AXP_POWER_SOURCE_ACIN_PRESENT); 502 } 503 break; 504 case AXP_SENSOR_VBUS_PRESENT: 505 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_SOURCE_REG, &val, flags) == 0) { 506 e->state = ENVSYS_SVALID; 507 e->value_cur = !!(val & AXP_POWER_SOURCE_VBUS_PRESENT); 508 } 509 break; 510 case AXP_SENSOR_BATT_PRESENT: 511 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_MODE_REG, &val, flags) == 0) { 512 if (val & AXP_POWER_MODE_BATT_VALID) { 513 e->state = ENVSYS_SVALID; 514 e->value_cur = !!(val & AXP_POWER_MODE_BATT_PRESENT); 515 } 516 } 517 break; 518 case AXP_SENSOR_BATT_CHARGING: 519 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_MODE_REG, &val, flags) == 0) { 520 e->state = ENVSYS_SVALID; 521 e->value_cur = !!(val & AXP_POWER_MODE_BATT_CHARGING); 522 } 523 break; 524 case AXP_SENSOR_BATT_CHARGE_STATE: 525 if (battery_present && 526 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_CAP_REG, &val, flags) == 0 && 527 (val & AXP_BATT_CAP_VALID) != 0) { 528 const u_int batt_val = __SHIFTOUT(val, AXP_BATT_CAP_PERCENT); 529 if (batt_val <= sc->sc_shut_thres) { 530 e->state = ENVSYS_SCRITICAL; 531 e->value_cur = ENVSYS_BATTERY_CAPACITY_CRITICAL; 532 } else if (batt_val <= sc->sc_warn_thres) { 533 e->state = ENVSYS_SWARNUNDER; 534 e->value_cur = ENVSYS_BATTERY_CAPACITY_WARNING; 535 } else { 536 e->state = ENVSYS_SVALID; 537 e->value_cur = ENVSYS_BATTERY_CAPACITY_NORMAL; 538 } 539 } 540 break; 541 case AXP_SENSOR_BATT_CAPACITY_PERCENT: 542 if (battery_present && 543 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_CAP_REG, &val, flags) == 0 && 544 (val & AXP_BATT_CAP_VALID) != 0) { 545 e->state = ENVSYS_SVALID; 546 e->value_cur = __SHIFTOUT(val, AXP_BATT_CAP_PERCENT); 547 } 548 break; 549 case AXP_SENSOR_BATT_VOLTAGE: 550 if (battery_present && 551 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATSENSE_HI_REG, &hi, flags) == 0 && 552 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATSENSE_LO_REG, &lo, flags) == 0) { 553 e->state = ENVSYS_SVALID; 554 e->value_cur = AXP_ADC_RAW(hi, lo) * c->batsense_step; 555 } 556 break; 557 case AXP_SENSOR_BATT_CHARGE_CURRENT: 558 if (battery_present && 559 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_SOURCE_REG, &val, flags) == 0 && 560 (val & AXP_POWER_SOURCE_CHARGE_DIRECTION) != 0 && 561 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATTCHG_HI_REG, &hi, flags) == 0 && 562 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATTCHG_LO_REG, &lo, flags) == 0) { 563 e->state = ENVSYS_SVALID; 564 e->value_cur = AXP_ADC_RAW(hi, lo) * c->charge_step; 565 } 566 break; 567 case AXP_SENSOR_BATT_DISCHARGE_CURRENT: 568 if (battery_present && 569 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_SOURCE_REG, &val, flags) == 0 && 570 (val & AXP_POWER_SOURCE_CHARGE_DIRECTION) == 0 && 571 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATTDISCHG_HI_REG, &hi, flags) == 0 && 572 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATTDISCHG_LO_REG, &lo, flags) == 0) { 573 e->state = ENVSYS_SVALID; 574 e->value_cur = AXP_ADC_RAW(hi, lo) * c->discharge_step; 575 } 576 break; 577 case AXP_SENSOR_BATT_MAXIMUM_CAPACITY: 578 if (battery_present && 579 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_MAX_CAP_HI_REG, &hi, flags) == 0 && 580 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_MAX_CAP_LO_REG, &lo, flags) == 0) { 581 e->state = (hi & AXP_BATT_MAX_CAP_VALID) ? ENVSYS_SVALID : ENVSYS_SINVALID; 582 e->value_cur = AXP_COULOMB_RAW(hi, lo) * c->maxcap_step; 583 } 584 break; 585 case AXP_SENSOR_BATT_CURRENT_CAPACITY: 586 if (battery_present && 587 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_COULOMB_HI_REG, &hi, flags) == 0 && 588 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_COULOMB_LO_REG, &lo, flags) == 0) { 589 e->state = (hi & AXP_BATT_COULOMB_VALID) ? ENVSYS_SVALID : ENVSYS_SINVALID; 590 e->value_cur = AXP_COULOMB_RAW(hi, lo) * c->coulomb_step; 591 } 592 break; 593 } 594 } 595 596 static void 597 axppmic_sensor_refresh(struct sysmon_envsys *sme, envsys_data_t *e) 598 { 599 struct axppmic_softc *sc = sme->sme_cookie; 600 const int flags = I2C_F_POLL; 601 602 switch (e->private) { 603 case AXP_SENSOR_BATT_CAPACITY_PERCENT: 604 case AXP_SENSOR_BATT_VOLTAGE: 605 case AXP_SENSOR_BATT_CHARGE_CURRENT: 606 case AXP_SENSOR_BATT_DISCHARGE_CURRENT: 607 /* Always update battery capacity and ADCs */ 608 iic_acquire_bus(sc->sc_i2c, flags); 609 axppmic_sensor_update(sme, e); 610 iic_release_bus(sc->sc_i2c, flags); 611 break; 612 default: 613 /* Refresh if the sensor is not in valid state */ 614 if (e->state != ENVSYS_SVALID) { 615 iic_acquire_bus(sc->sc_i2c, flags); 616 axppmic_sensor_update(sme, e); 617 iic_release_bus(sc->sc_i2c, flags); 618 } 619 break; 620 } 621 } 622 623 static int 624 axppmic_intr(void *priv) 625 { 626 struct axppmic_softc *sc = priv; 627 const struct axppmic_config *c = sc->sc_conf; 628 const int flags = I2C_F_POLL; 629 uint8_t stat; 630 u_int n; 631 632 iic_acquire_bus(sc->sc_i2c, flags); 633 for (n = 1; n <= c->irq_regs; n++) { 634 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_IRQ_STATUS_REG(n), &stat, flags) == 0) { 635 if (n == c->poklirq.reg && (stat & c->poklirq.mask) != 0) 636 sysmon_task_queue_sched(0, axppmic_task_shut, sc); 637 if (n == c->acinirq.reg && (stat & c->acinirq.mask) != 0) 638 axppmic_sensor_update(sc->sc_sme, &sc->sc_sensor[AXP_SENSOR_ACIN_PRESENT]); 639 if (n == c->vbusirq.reg && (stat & c->vbusirq.mask) != 0) 640 axppmic_sensor_update(sc->sc_sme, &sc->sc_sensor[AXP_SENSOR_VBUS_PRESENT]); 641 if (n == c->battirq.reg && (stat & c->battirq.mask) != 0) 642 axppmic_sensor_update(sc->sc_sme, &sc->sc_sensor[AXP_SENSOR_BATT_PRESENT]); 643 if (n == c->chargeirq.reg && (stat & c->chargeirq.mask) != 0) 644 axppmic_sensor_update(sc->sc_sme, &sc->sc_sensor[AXP_SENSOR_BATT_CHARGING]); 645 if (n == c->chargestirq.reg && (stat & c->chargestirq.mask) != 0) 646 axppmic_sensor_update(sc->sc_sme, &sc->sc_sensor[AXP_SENSOR_BATT_CHARGE_STATE]); 647 648 if (stat != 0) 649 axppmic_write(sc->sc_i2c, sc->sc_addr, 650 AXP_IRQ_STATUS_REG(n), stat, flags); 651 } 652 } 653 iic_release_bus(sc->sc_i2c, flags); 654 655 return 1; 656 } 657 658 static void 659 axppmic_attach_acadapter(struct axppmic_softc *sc) 660 { 661 envsys_data_t *e; 662 663 e = &sc->sc_sensor[AXP_SENSOR_ACIN_PRESENT]; 664 e->private = AXP_SENSOR_ACIN_PRESENT; 665 e->units = ENVSYS_INDICATOR; 666 e->state = ENVSYS_SINVALID; 667 strlcpy(e->desc, "ACIN present", sizeof(e->desc)); 668 sysmon_envsys_sensor_attach(sc->sc_sme, e); 669 670 e = &sc->sc_sensor[AXP_SENSOR_VBUS_PRESENT]; 671 e->private = AXP_SENSOR_VBUS_PRESENT; 672 e->units = ENVSYS_INDICATOR; 673 e->state = ENVSYS_SINVALID; 674 strlcpy(e->desc, "VBUS present", sizeof(e->desc)); 675 sysmon_envsys_sensor_attach(sc->sc_sme, e); 676 } 677 678 static void 679 axppmic_attach_battery(struct axppmic_softc *sc) 680 { 681 const struct axppmic_config *c = sc->sc_conf; 682 envsys_data_t *e; 683 uint8_t val; 684 685 iic_acquire_bus(sc->sc_i2c, I2C_F_POLL); 686 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_CAP_WARN_REG, &val, I2C_F_POLL) == 0) { 687 sc->sc_warn_thres = __SHIFTOUT(val, AXP_BATT_CAP_WARN_LV1) + 5; 688 sc->sc_shut_thres = __SHIFTOUT(val, AXP_BATT_CAP_WARN_LV2); 689 } 690 iic_release_bus(sc->sc_i2c, I2C_F_POLL); 691 692 e = &sc->sc_sensor[AXP_SENSOR_BATT_PRESENT]; 693 e->private = AXP_SENSOR_BATT_PRESENT; 694 e->units = ENVSYS_INDICATOR; 695 e->state = ENVSYS_SINVALID; 696 strlcpy(e->desc, "battery present", sizeof(e->desc)); 697 sysmon_envsys_sensor_attach(sc->sc_sme, e); 698 699 e = &sc->sc_sensor[AXP_SENSOR_BATT_CHARGING]; 700 e->private = AXP_SENSOR_BATT_CHARGING; 701 e->units = ENVSYS_BATTERY_CHARGE; 702 e->state = ENVSYS_SINVALID; 703 strlcpy(e->desc, "charging", sizeof(e->desc)); 704 sysmon_envsys_sensor_attach(sc->sc_sme, e); 705 706 e = &sc->sc_sensor[AXP_SENSOR_BATT_CHARGE_STATE]; 707 e->private = AXP_SENSOR_BATT_CHARGE_STATE; 708 e->units = ENVSYS_BATTERY_CAPACITY; 709 e->flags = ENVSYS_FMONSTCHANGED; 710 e->state = ENVSYS_SINVALID; 711 e->value_cur = ENVSYS_BATTERY_CAPACITY_NORMAL; 712 strlcpy(e->desc, "charge state", sizeof(e->desc)); 713 sysmon_envsys_sensor_attach(sc->sc_sme, e); 714 715 if (c->batsense_step) { 716 e = &sc->sc_sensor[AXP_SENSOR_BATT_VOLTAGE]; 717 e->private = AXP_SENSOR_BATT_VOLTAGE; 718 e->units = ENVSYS_SVOLTS_DC; 719 e->state = ENVSYS_SINVALID; 720 strlcpy(e->desc, "battery voltage", sizeof(e->desc)); 721 sysmon_envsys_sensor_attach(sc->sc_sme, e); 722 } 723 724 if (c->charge_step) { 725 e = &sc->sc_sensor[AXP_SENSOR_BATT_CHARGE_CURRENT]; 726 e->private = AXP_SENSOR_BATT_CHARGE_CURRENT; 727 e->units = ENVSYS_SAMPS; 728 e->state = ENVSYS_SINVALID; 729 strlcpy(e->desc, "battery charge current", sizeof(e->desc)); 730 sysmon_envsys_sensor_attach(sc->sc_sme, e); 731 } 732 733 if (c->discharge_step) { 734 e = &sc->sc_sensor[AXP_SENSOR_BATT_DISCHARGE_CURRENT]; 735 e->private = AXP_SENSOR_BATT_DISCHARGE_CURRENT; 736 e->units = ENVSYS_SAMPS; 737 e->state = ENVSYS_SINVALID; 738 strlcpy(e->desc, "battery discharge current", sizeof(e->desc)); 739 sysmon_envsys_sensor_attach(sc->sc_sme, e); 740 } 741 742 if (c->has_fuel_gauge) { 743 e = &sc->sc_sensor[AXP_SENSOR_BATT_CAPACITY_PERCENT]; 744 e->private = AXP_SENSOR_BATT_CAPACITY_PERCENT; 745 e->units = ENVSYS_INTEGER; 746 e->state = ENVSYS_SINVALID; 747 e->flags = ENVSYS_FPERCENT; 748 strlcpy(e->desc, "battery percent", sizeof(e->desc)); 749 sysmon_envsys_sensor_attach(sc->sc_sme, e); 750 } 751 752 if (c->maxcap_step) { 753 e = &sc->sc_sensor[AXP_SENSOR_BATT_MAXIMUM_CAPACITY]; 754 e->private = AXP_SENSOR_BATT_MAXIMUM_CAPACITY; 755 e->units = ENVSYS_SAMPHOUR; 756 e->state = ENVSYS_SINVALID; 757 strlcpy(e->desc, "battery maximum capacity", sizeof(e->desc)); 758 sysmon_envsys_sensor_attach(sc->sc_sme, e); 759 } 760 761 if (c->coulomb_step) { 762 e = &sc->sc_sensor[AXP_SENSOR_BATT_CURRENT_CAPACITY]; 763 e->private = AXP_SENSOR_BATT_CURRENT_CAPACITY; 764 e->units = ENVSYS_SAMPHOUR; 765 e->state = ENVSYS_SINVALID; 766 strlcpy(e->desc, "battery current capacity", sizeof(e->desc)); 767 sysmon_envsys_sensor_attach(sc->sc_sme, e); 768 } 769 } 770 771 static void 772 axppmic_attach_sensors(struct axppmic_softc *sc) 773 { 774 if (sc->sc_conf->has_battery) { 775 sc->sc_sme = sysmon_envsys_create(); 776 sc->sc_sme->sme_name = device_xname(sc->sc_dev); 777 sc->sc_sme->sme_cookie = sc; 778 sc->sc_sme->sme_refresh = axppmic_sensor_refresh; 779 sc->sc_sme->sme_class = SME_CLASS_BATTERY; 780 sc->sc_sme->sme_flags = SME_INIT_REFRESH; 781 782 axppmic_attach_acadapter(sc); 783 axppmic_attach_battery(sc); 784 785 sysmon_envsys_register(sc->sc_sme); 786 } 787 } 788 789 790 static int 791 axppmic_match(device_t parent, cfdata_t match, void *aux) 792 { 793 struct i2c_attach_args *ia = aux; 794 int match_result; 795 796 if (iic_use_direct_match(ia, match, compat_data, &match_result)) 797 return match_result; 798 799 /* This device is direct-config only. */ 800 801 return 0; 802 } 803 804 static void 805 axppmic_attach(device_t parent, device_t self, void *aux) 806 { 807 struct axppmic_softc *sc = device_private(self); 808 const struct device_compatible_entry *dce = NULL; 809 const struct axppmic_config *c; 810 struct axpreg_attach_args aaa; 811 struct i2c_attach_args *ia = aux; 812 int phandle, child, i; 813 uint32_t irq_mask; 814 void *ih; 815 816 (void) iic_compatible_match(ia, compat_data, &dce); 817 KASSERT(dce != NULL); 818 c = (void *)dce->data; 819 820 sc->sc_dev = self; 821 sc->sc_i2c = ia->ia_tag; 822 sc->sc_addr = ia->ia_addr; 823 sc->sc_phandle = ia->ia_cookie; 824 sc->sc_conf = c; 825 826 aprint_naive("\n"); 827 aprint_normal(": %s\n", c->name); 828 829 sc->sc_smpsw.smpsw_name = device_xname(self); 830 sc->sc_smpsw.smpsw_type = PSWITCH_TYPE_POWER; 831 sysmon_pswitch_register(&sc->sc_smpsw); 832 833 iic_acquire_bus(sc->sc_i2c, I2C_F_POLL); 834 for (i = 1; i <= c->irq_regs; i++) { 835 irq_mask = 0; 836 if (i == c->poklirq.reg) 837 irq_mask |= c->poklirq.mask; 838 if (i == c->acinirq.reg) 839 irq_mask |= c->acinirq.mask; 840 if (i == c->vbusirq.reg) 841 irq_mask |= c->vbusirq.mask; 842 if (i == c->battirq.reg) 843 irq_mask |= c->battirq.mask; 844 if (i == c->chargeirq.reg) 845 irq_mask |= c->chargeirq.mask; 846 if (i == c->chargestirq.reg) 847 irq_mask |= c->chargestirq.mask; 848 axppmic_write(sc->sc_i2c, sc->sc_addr, AXP_IRQ_ENABLE_REG(i), irq_mask, I2C_F_POLL); 849 } 850 iic_release_bus(sc->sc_i2c, I2C_F_POLL); 851 852 ih = fdtbus_intr_establish(sc->sc_phandle, 0, IPL_VM, FDT_INTR_MPSAFE, 853 axppmic_intr, sc); 854 if (ih == NULL) { 855 aprint_error_dev(self, "WARNING: couldn't establish interrupt handler\n"); 856 } 857 858 fdtbus_register_power_controller(sc->sc_dev, sc->sc_phandle, 859 &axppmic_power_funcs); 860 861 phandle = of_find_firstchild_byname(sc->sc_phandle, "regulators"); 862 if (phandle > 0) { 863 aaa.reg_i2c = sc->sc_i2c; 864 aaa.reg_addr = sc->sc_addr; 865 for (i = 0; i < c->ncontrols; i++) { 866 const struct axppmic_ctrl *ctrl = &c->controls[i]; 867 child = of_find_firstchild_byname(phandle, ctrl->c_name); 868 if (child <= 0) 869 continue; 870 aaa.reg_ctrl = ctrl; 871 aaa.reg_phandle = child; 872 config_found(sc->sc_dev, &aaa, NULL); 873 } 874 } 875 876 if (c->has_battery) 877 axppmic_attach_sensors(sc); 878 } 879 880 static int 881 axpreg_acquire(device_t dev) 882 { 883 struct axpreg_softc *sc = device_private(dev); 884 885 if (atomic_cas_uint(&sc->sc_inuse, 0, 1) != 0) 886 return EBUSY; 887 888 return 0; 889 } 890 891 static void 892 axpreg_release(device_t dev) 893 { 894 struct axpreg_softc *sc = device_private(dev); 895 896 atomic_swap_uint(&sc->sc_inuse, 0); 897 } 898 899 static int 900 axpreg_enable(device_t dev, bool enable) 901 { 902 struct axpreg_softc *sc = device_private(dev); 903 const struct axppmic_ctrl *c = sc->sc_ctrl; 904 const int flags = (cold ? I2C_F_POLL : 0); 905 uint8_t val; 906 int error; 907 908 if (!c->c_enable_mask) 909 return EINVAL; 910 911 iic_acquire_bus(sc->sc_i2c, flags); 912 if ((error = axppmic_read(sc->sc_i2c, sc->sc_addr, c->c_enable_reg, &val, flags)) == 0) { 913 if (enable) 914 val |= c->c_enable_mask; 915 else 916 val &= ~c->c_enable_mask; 917 error = axppmic_write(sc->sc_i2c, sc->sc_addr, c->c_enable_reg, val, flags); 918 } 919 iic_release_bus(sc->sc_i2c, flags); 920 921 return error; 922 } 923 924 static int 925 axpreg_set_voltage(device_t dev, u_int min_uvol, u_int max_uvol) 926 { 927 struct axpreg_softc *sc = device_private(dev); 928 const struct axppmic_ctrl *c = sc->sc_ctrl; 929 930 return axppmic_set_voltage(sc->sc_i2c, sc->sc_addr, c, 931 min_uvol / 1000, max_uvol / 1000); 932 } 933 934 static int 935 axpreg_get_voltage(device_t dev, u_int *puvol) 936 { 937 struct axpreg_softc *sc = device_private(dev); 938 const struct axppmic_ctrl *c = sc->sc_ctrl; 939 int error; 940 u_int vol; 941 942 error = axppmic_get_voltage(sc->sc_i2c, sc->sc_addr, c, &vol); 943 if (error) 944 return error; 945 946 *puvol = vol * 1000; 947 return 0; 948 } 949 950 static struct fdtbus_regulator_controller_func axpreg_funcs = { 951 .acquire = axpreg_acquire, 952 .release = axpreg_release, 953 .enable = axpreg_enable, 954 .set_voltage = axpreg_set_voltage, 955 .get_voltage = axpreg_get_voltage, 956 }; 957 958 static int 959 axpreg_match(device_t parent, cfdata_t match, void *aux) 960 { 961 return 1; 962 } 963 964 static void 965 axpreg_attach(device_t parent, device_t self, void *aux) 966 { 967 struct axpreg_softc *sc = device_private(self); 968 struct axpreg_attach_args *aaa = aux; 969 const int phandle = aaa->reg_phandle; 970 const char *name; 971 972 sc->sc_dev = self; 973 sc->sc_i2c = aaa->reg_i2c; 974 sc->sc_addr = aaa->reg_addr; 975 sc->sc_ctrl = aaa->reg_ctrl; 976 977 fdtbus_register_regulator_controller(self, phandle, 978 &axpreg_funcs); 979 980 aprint_naive("\n"); 981 name = fdtbus_get_string(phandle, "regulator-name"); 982 if (name) 983 aprint_normal(": %s\n", name); 984 else 985 aprint_normal("\n"); 986 } 987 988 CFATTACH_DECL_NEW(axppmic, sizeof(struct axppmic_softc), 989 axppmic_match, axppmic_attach, NULL, NULL); 990 991 CFATTACH_DECL_NEW(axpreg, sizeof(struct axpreg_softc), 992 axpreg_match, axpreg_attach, NULL, NULL); 993
Indexes created Fri Oct 03 02:09:57 GMT 2025