axppmic.c revision 1.40
1 /* $NetBSD: axppmic.c,v 1.40 2025/01/05 08:45:08 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2014-2018 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: axppmic.c,v 1.40 2025/01/05 08:45:08 skrll Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/device.h> 36 #include <sys/conf.h> 37 #include <sys/bus.h> 38 #include <sys/kmem.h> 39 #include <sys/workqueue.h> 40 41 #include <dev/i2c/i2cvar.h> 42 43 #include <dev/sysmon/sysmonvar.h> 44 #include <dev/sysmon/sysmon_taskq.h> 45 46 #include <dev/fdt/fdtvar.h> 47 48 #define AXP_POWER_SOURCE_REG 0x00 49 #define AXP_POWER_SOURCE_ACIN_PRESENT __BIT(7) 50 #define AXP_POWER_SOURCE_VBUS_PRESENT __BIT(5) 51 #define AXP_POWER_SOURCE_CHARGE_DIRECTION __BIT(2) 52 53 #define AXP_POWER_MODE_REG 0x01 54 #define AXP_POWER_MODE_BATT_VALID __BIT(4) 55 #define AXP_POWER_MODE_BATT_PRESENT __BIT(5) 56 #define AXP_POWER_MODE_BATT_CHARGING __BIT(6) 57 58 #define AXP_CHIP_ID_REG 0x03 59 60 #define AXP_POWER_DISABLE_REG 0x32 61 #define AXP_POWER_DISABLE_CTRL __BIT(7) 62 63 #define AXP_IRQ_ENABLE_REG(n) (0x40 + (n) - 1) 64 #define AXP_IRQ1_ACIN_RAISE __BIT(6) 65 #define AXP_IRQ1_ACIN_LOWER __BIT(5) 66 #define AXP_IRQ1_VBUS_RAISE __BIT(3) 67 #define AXP_IRQ1_VBUS_LOWER __BIT(2) 68 #define AXP_IRQ_STATUS_REG(n) (0x48 + (n) - 1) 69 70 #define AXP_BATSENSE_HI_REG 0x78 71 #define AXP_BATSENSE_LO_REG 0x79 72 73 #define AXP_BATTCHG_HI_REG 0x7a 74 #define AXP_BATTCHG_LO_REG 0x7b 75 76 #define AXP_BATTDISCHG_HI_REG 0x7c 77 #define AXP_BATTDISCHG_LO_REG 0x7d 78 79 #define AXP_ADC_RAW(_hi, _lo) \ 80 (((u_int)(_hi) << 4) | ((_lo) & 0xf)) 81 82 #define AXP_GPIO_CTRL_REG(pin) (0x90 + (pin) * 2) 83 #define AXP_GPIO_CTRL_FUNC_MASK __BITS(2,0) 84 #define AXP_GPIO_CTRL_FUNC_LOW 0 85 #define AXP_GPIO_CTRL_FUNC_HIGH 1 86 #define AXP_GPIO_CTRL_FUNC_INPUT 2 87 #define AXP_GPIO_SIGNAL_REG 0x94 88 89 #define AXP_FUEL_GAUGE_CTRL_REG 0xb8 90 #define AXP_FUEL_GAUGE_CTRL_EN __BIT(7) 91 92 #define AXP_BATT_CAP_REG 0xb9 93 #define AXP_BATT_CAP_VALID __BIT(7) 94 #define AXP_BATT_CAP_PERCENT __BITS(6,0) 95 96 #define AXP_BATT_MAX_CAP_HI_REG 0xe0 97 #define AXP_BATT_MAX_CAP_VALID __BIT(7) 98 #define AXP_BATT_MAX_CAP_LO_REG 0xe1 99 100 #define AXP_BATT_COULOMB_HI_REG 0xe2 101 #define AXP_BATT_COULOMB_VALID __BIT(7) 102 #define AXP_BATT_COULOMB_LO_REG 0xe3 103 104 #define AXP_COULOMB_RAW(_hi, _lo) \ 105 (((u_int)(_hi & ~__BIT(7)) << 8) | (_lo)) 106 107 #define AXP_BATT_CAP_WARN_REG 0xe6 108 #define AXP_BATT_CAP_WARN_LV1 __BITS(7,4) 109 #define AXP_BATT_CAP_WARN_LV2 __BITS(3,0) 110 111 #define AXP_ADDR_EXT_REG 0xff /* AXP806 */ 112 #define AXP_ADDR_EXT_MASTER 0 113 #define AXP_ADDR_EXT_SLAVE __BIT(4) 114 115 struct axppmic_ctrl { 116 device_t c_dev; 117 118 const char * c_name; 119 u_int c_min; 120 u_int c_max; 121 u_int c_step1; 122 u_int c_step1cnt; 123 u_int c_step2; 124 u_int c_step2cnt; 125 u_int c_step2start; 126 127 uint8_t c_enable_reg; 128 uint8_t c_enable_mask; 129 uint8_t c_enable_val; 130 uint8_t c_disable_val; 131 132 uint8_t c_voltage_reg; 133 uint8_t c_voltage_mask; 134 }; 135 136 #define AXP_CTRL(name, min, max, step, ereg, emask, vreg, vmask) \ 137 { .c_name = (name), .c_min = (min), .c_max = (max), \ 138 .c_step1 = (step), .c_step1cnt = (((max) - (min)) / (step)) + 1, \ 139 .c_step2 = 0, .c_step2cnt = 0, \ 140 .c_enable_reg = (ereg), .c_enable_mask = (emask), \ 141 .c_enable_val = (emask), .c_disable_val = 0, \ 142 .c_voltage_reg = (vreg), .c_voltage_mask = (vmask) } 143 144 #define AXP_CTRL2(name, min, max, step1, step1cnt, step2, step2cnt, ereg, emask, vreg, vmask) \ 145 { .c_name = (name), .c_min = (min), .c_max = (max), \ 146 .c_step1 = (step1), .c_step1cnt = (step1cnt), \ 147 .c_step2 = (step2), .c_step2cnt = (step2cnt), \ 148 .c_enable_reg = (ereg), .c_enable_mask = (emask), \ 149 .c_enable_val = (emask), .c_disable_val = 0, \ 150 .c_voltage_reg = (vreg), .c_voltage_mask = (vmask) } 151 152 #define AXP_CTRL2_RANGE(name, min, max, step1, step1cnt, step2start, step2, step2cnt, ereg, emask, vreg, vmask) \ 153 { .c_name = (name), .c_min = (min), .c_max = (max), \ 154 .c_step1 = (step1), .c_step1cnt = (step1cnt), \ 155 .c_step2start = (step2start), \ 156 .c_step2 = (step2), .c_step2cnt = (step2cnt), \ 157 .c_enable_reg = (ereg), .c_enable_mask = (emask), \ 158 .c_enable_val = (emask), .c_disable_val = 0, \ 159 .c_voltage_reg = (vreg), .c_voltage_mask = (vmask) } 160 161 #define AXP_CTRL_IO(name, min, max, step, ereg, emask, eval, dval, vreg, vmask) \ 162 { .c_name = (name), .c_min = (min), .c_max = (max), \ 163 .c_step1 = (step), .c_step1cnt = (((max) - (min)) / (step)) + 1, \ 164 .c_step2 = 0, .c_step2cnt = 0, \ 165 .c_enable_reg = (ereg), .c_enable_mask = (emask), \ 166 .c_enable_val = (eval), .c_disable_val = (dval), \ 167 .c_voltage_reg = (vreg), .c_voltage_mask = (vmask) } 168 169 #define AXP_CTRL_SW(name, ereg, emask) \ 170 { .c_name = (name), \ 171 .c_enable_reg = (ereg), .c_enable_mask = (emask), \ 172 .c_enable_val = (emask), .c_disable_val = 0 } 173 174 static const struct axppmic_ctrl axp803_ctrls[] = { 175 AXP_CTRL("dldo1", 700, 3300, 100, 176 0x12, __BIT(3), 0x15, __BITS(4,0)), 177 AXP_CTRL2("dldo2", 700, 4200, 100, 28, 200, 4, 178 0x12, __BIT(4), 0x16, __BITS(4,0)), 179 AXP_CTRL("dldo3", 700, 3300, 100, 180 0x12, __BIT(5), 0x17, __BITS(4,0)), 181 AXP_CTRL("dldo4", 700, 3300, 100, 182 0x12, __BIT(6), 0x18, __BITS(4,0)), 183 AXP_CTRL("eldo1", 700, 1900, 50, 184 0x12, __BIT(0), 0x19, __BITS(4,0)), 185 AXP_CTRL("eldo2", 700, 1900, 50, 186 0x12, __BIT(1), 0x1a, __BITS(4,0)), 187 AXP_CTRL("eldo3", 700, 1900, 50, 188 0x12, __BIT(2), 0x1b, __BITS(4,0)), 189 AXP_CTRL("fldo1", 700, 1450, 50, 190 0x13, __BIT(2), 0x1c, __BITS(3,0)), 191 AXP_CTRL("fldo2", 700, 1450, 50, 192 0x13, __BIT(3), 0x1d, __BITS(3,0)), 193 AXP_CTRL("dcdc1", 1600, 3400, 100, 194 0x10, __BIT(0), 0x20, __BITS(4,0)), 195 AXP_CTRL2("dcdc2", 500, 1300, 10, 70, 20, 5, 196 0x10, __BIT(1), 0x21, __BITS(6,0)), 197 AXP_CTRL2("dcdc3", 500, 1300, 10, 70, 20, 5, 198 0x10, __BIT(2), 0x22, __BITS(6,0)), 199 AXP_CTRL2("dcdc4", 500, 1300, 10, 70, 20, 5, 200 0x10, __BIT(3), 0x23, __BITS(6,0)), 201 AXP_CTRL2("dcdc5", 800, 1840, 10, 33, 20, 36, 202 0x10, __BIT(4), 0x24, __BITS(6,0)), 203 AXP_CTRL2("dcdc6", 600, 1520, 10, 51, 20, 21, 204 0x10, __BIT(5), 0x25, __BITS(6,0)), 205 AXP_CTRL("aldo1", 700, 3300, 100, 206 0x13, __BIT(5), 0x28, __BITS(4,0)), 207 AXP_CTRL("aldo2", 700, 3300, 100, 208 0x13, __BIT(6), 0x29, __BITS(4,0)), 209 AXP_CTRL("aldo3", 700, 3300, 100, 210 0x13, __BIT(7), 0x2a, __BITS(4,0)), 211 }; 212 213 static const struct axppmic_ctrl axp805_ctrls[] = { 214 AXP_CTRL2("dcdca", 600, 1520, 10, 51, 20, 21, 215 0x10, __BIT(0), 0x12, __BITS(6,0)), 216 AXP_CTRL("dcdcb", 1000, 2550, 50, 217 0x10, __BIT(1), 0x13, __BITS(4,0)), 218 AXP_CTRL2("dcdcc", 600, 1520, 10, 51, 20, 21, 219 0x10, __BIT(2), 0x14, __BITS(6,0)), 220 AXP_CTRL2("dcdcd", 600, 3300, 20, 46, 100, 18, 221 0x10, __BIT(3), 0x15, __BITS(5,0)), 222 AXP_CTRL("dcdce", 1100, 3400, 100, 223 0x10, __BIT(4), 0x16, __BITS(4,0)), 224 AXP_CTRL("aldo1", 700, 3300, 100, 225 0x10, __BIT(5), 0x17, __BITS(4,0)), 226 AXP_CTRL("aldo2", 700, 3400, 100, 227 0x10, __BIT(6), 0x18, __BITS(4,0)), 228 AXP_CTRL("aldo3", 700, 3300, 100, 229 0x10, __BIT(7), 0x19, __BITS(4,0)), 230 AXP_CTRL("bldo1", 700, 1900, 100, 231 0x11, __BIT(0), 0x20, __BITS(3,0)), 232 AXP_CTRL("bldo2", 700, 1900, 100, 233 0x11, __BIT(1), 0x21, __BITS(3,0)), 234 AXP_CTRL("bldo3", 700, 1900, 100, 235 0x11, __BIT(2), 0x22, __BITS(3,0)), 236 AXP_CTRL("bldo4", 700, 1900, 100, 237 0x11, __BIT(3), 0x23, __BITS(3,0)), 238 AXP_CTRL("cldo1", 700, 3300, 100, 239 0x11, __BIT(4), 0x24, __BITS(4,0)), 240 AXP_CTRL2("cldo2", 700, 4200, 100, 28, 200, 4, 241 0x11, __BIT(5), 0x25, __BITS(4,0)), 242 AXP_CTRL("cldo3", 700, 3300, 100, 243 0x11, __BIT(6), 0x26, __BITS(4,0)), 244 }; 245 246 static const struct axppmic_ctrl axp809_ctrls[] = { 247 AXP_CTRL("dc5ldo", 700, 1400, 100, 248 0x10, __BIT(0), 0x1c, __BITS(2,0)), 249 AXP_CTRL("dcdc1", 1600, 3400, 100, 250 0x10, __BIT(1), 0x21, __BITS(4,0)), 251 AXP_CTRL("dcdc2", 600, 1540, 20, 252 0x10, __BIT(2), 0x22, __BITS(5,0)), 253 AXP_CTRL("dcdc3", 600, 1860, 20, 254 0x10, __BIT(3), 0x23, __BITS(5,0)), 255 AXP_CTRL2_RANGE("dcdc4", 600, 2600, 20, 47, 1800, 100, 9, 256 0x10, __BIT(4), 0x24, __BITS(5,0)), 257 AXP_CTRL("dcdc5", 1000, 2550, 50, 258 0x10, __BIT(5), 0x25, __BITS(4,0)), 259 AXP_CTRL("aldo1", 700, 3300, 100, 260 0x10, __BIT(6), 0x28, __BITS(4,0)), 261 AXP_CTRL("aldo2", 700, 3300, 100, 262 0x10, __BIT(7), 0x29, __BITS(4,0)), 263 AXP_CTRL("eldo1", 700, 3300, 100, 264 0x12, __BIT(0), 0x19, __BITS(4,0)), 265 AXP_CTRL("eldo2", 700, 3300, 100, 266 0x12, __BIT(1), 0x1a, __BITS(4,0)), 267 AXP_CTRL("eldo3", 700, 3300, 100, 268 0x12, __BIT(2), 0x1b, __BITS(4,0)), 269 AXP_CTRL2_RANGE("dldo1", 700, 4000, 100, 26, 3400, 200, 4, 270 0x12, __BIT(3), 0x15, __BITS(4,0)), 271 AXP_CTRL("dldo2", 700, 3300, 100, 272 0x12, __BIT(4), 0x16, __BITS(4,0)), 273 AXP_CTRL("aldo3", 700, 3300, 100, 274 0x12, __BIT(5), 0x2a, __BITS(4,0)), 275 AXP_CTRL_SW("sw", 276 0x12, __BIT(6)), 277 /* dc1sw is another switch for dcdc1 */ 278 AXP_CTRL("dc1sw", 1600, 3400, 100, 279 0x12, __BIT(7), 0x21, __BITS(4,0)), 280 AXP_CTRL_IO("ldo_io0", 700, 3300, 100, 281 0x90, __BITS(3,0), 0x3, 0x7, 0x91, __BITS(4,0)), 282 AXP_CTRL_IO("ldo_io1", 700, 3300, 100, 283 0x92, __BITS(3,0), 0x3, 0x7, 0x93, __BITS(4,0)), 284 }; 285 286 static const struct axppmic_ctrl axp813_ctrls[] = { 287 AXP_CTRL("dldo1", 700, 3300, 100, 288 0x12, __BIT(3), 0x15, __BITS(4,0)), 289 AXP_CTRL2("dldo2", 700, 4200, 100, 28, 200, 4, 290 0x12, __BIT(4), 0x16, __BITS(4,0)), 291 AXP_CTRL("dldo3", 700, 3300, 100, 292 0x12, __BIT(5), 0x17, __BITS(4,0)), 293 AXP_CTRL("dldo4", 700, 3300, 100, 294 0x12, __BIT(6), 0x18, __BITS(4,0)), 295 AXP_CTRL("eldo1", 700, 1900, 50, 296 0x12, __BIT(0), 0x19, __BITS(4,0)), 297 AXP_CTRL("eldo2", 700, 1900, 50, 298 0x12, __BIT(1), 0x1a, __BITS(4,0)), 299 AXP_CTRL("eldo3", 700, 1900, 50, 300 0x12, __BIT(2), 0x1b, __BITS(4,0)), 301 AXP_CTRL("fldo1", 700, 1450, 50, 302 0x13, __BIT(2), 0x1c, __BITS(3,0)), 303 AXP_CTRL("fldo2", 700, 1450, 50, 304 0x13, __BIT(3), 0x1d, __BITS(3,0)), 305 AXP_CTRL("dcdc1", 1600, 3400, 100, 306 0x10, __BIT(0), 0x20, __BITS(4,0)), 307 AXP_CTRL2("dcdc2", 500, 1300, 10, 70, 20, 5, 308 0x10, __BIT(1), 0x21, __BITS(6,0)), 309 AXP_CTRL2("dcdc3", 500, 1300, 10, 70, 20, 5, 310 0x10, __BIT(2), 0x22, __BITS(6,0)), 311 AXP_CTRL2("dcdc4", 500, 1300, 10, 70, 20, 5, 312 0x10, __BIT(3), 0x23, __BITS(6,0)), 313 AXP_CTRL2("dcdc5", 800, 1840, 10, 33, 20, 36, 314 0x10, __BIT(4), 0x24, __BITS(6,0)), 315 AXP_CTRL2("dcdc6", 600, 1520, 10, 51, 20, 21, 316 0x10, __BIT(5), 0x25, __BITS(6,0)), 317 AXP_CTRL2("dcdc7", 600, 1520, 10, 51, 20, 21, 318 0x10, __BIT(6), 0x26, __BITS(6,0)), 319 AXP_CTRL("aldo1", 700, 3300, 100, 320 0x13, __BIT(5), 0x28, __BITS(4,0)), 321 AXP_CTRL("aldo2", 700, 3300, 100, 322 0x13, __BIT(6), 0x29, __BITS(4,0)), 323 AXP_CTRL("aldo3", 700, 3300, 100, 324 0x13, __BIT(7), 0x2a, __BITS(4,0)), 325 }; 326 327 static const struct axppmic_ctrl axp15060_ctrls[] = { 328 AXP_CTRL( "dcdc1", 1500, 3400, 100, 329 0x13, __BITS(4, 0), 330 0x10, __BIT(0)), 331 // DCDC2: 0.5~1.2V, 10mV/step, 1.22~1.54V, 20mV/step, IMAX=3.5A, DVM 332 AXP_CTRL2_RANGE("dcdc2", 333 500, 1540, 70, 10, 1220, 16 , 20, 334 0x14, __BITS(6, 0), 335 0x10, __BIT(1)), 336 // DCDC3: 0.5~1.2V, 10mV/step, 1.22~1.54V, 20mV/step, IMAX=3.5A, DVM 337 AXP_CTRL2_RANGE("dcdc3", 338 500, 1540, 70, 10, 1220, 16 , 20, 339 0x15, __BITS(6, 0), 340 0x10, __BIT(2)), 341 // DCDC4: 0.5~1.2V, 10mV/step, 1.22~1.54V, 20mV/step, IMAX=3.5A, DVM 342 AXP_CTRL2_RANGE("dcdc4", 343 500, 1540, 70, 10, 1220, 16 , 20, 344 0x16, __BITS(6, 0), 345 0x10, __BIT(3)), 346 // DCDC5: 0.8~1.12V, 10mV/step, 1.14~1.84V, 20mV/step, IMAX=2.5A, DVM 347 AXP_CTRL2_RANGE("dcdc5", 348 800, 1840, 349 32, 10, 350 1140, 35, 20, 351 0x17, __BITS(6, 0), 352 0x10, __BIT(4)), 353 AXP_CTRL("dcdc6", 500, 3400, 100, 354 0x18, __BITS(4, 0), 355 0x10, __BIT(5)), 356 AXP_CTRL("aldo1", 700, 3300, 100, 357 0x19, __BITS(4, 0), 358 0x11, __BIT(0)), 359 AXP_CTRL("aldo2", 700, 3300, 100, 360 0x20, __BITS(4, 0), 361 0x11, __BIT(1)), 362 AXP_CTRL("aldo3", 700, 3300, 100, 363 0x21, __BITS(4, 0), 364 0x11, __BIT(2)), 365 AXP_CTRL("aldo4", 700, 3300, 100, 366 0x22, __BITS(4, 0), 367 0x11, __BIT(3)), 368 AXP_CTRL("aldo5", 700, 3300, 100, 369 0x23, __BITS(4, 0), 370 0x11, __BIT(4)), 371 AXP_CTRL("bldo1", 700, 3300, 100, 372 0x24, __BITS(4, 0), 373 0x11, __BIT(5)), 374 AXP_CTRL("bldo2", 700, 3300, 100, 375 0x25, __BITS(4, 0), 376 0x11, __BIT(6)), 377 AXP_CTRL("bldo3", 700, 3300, 100, 378 0x26, __BITS(4, 0), 379 0x11, __BIT(7)), 380 AXP_CTRL("bldo4", 700, 3300, 100, 381 0x27, __BITS(4, 0), 382 0x12, __BIT(0)), 383 AXP_CTRL("bldo5", 700, 3300, 100, 384 0x28, __BITS(4, 0), 385 0x12, __BIT(1)), 386 AXP_CTRL("cldo1", 700, 3300, 100, 387 0x29, __BITS(4, 0), 388 0x12, __BIT(2)), 389 AXP_CTRL("cldo2", 700, 3300, 100, 390 0x2a, __BITS(4, 0), 391 0x12, __BIT(3)), 392 AXP_CTRL("cldo3", 700, 3300, 100, 393 0x2b, __BITS(4, 0), 394 0x12, __BIT(4)), 395 AXP_CTRL("cldo4", 700, 4200, 100, 396 0x2d, __BITS(5, 0), 397 0x12, __BIT(5)), 398 AXP_CTRL("cpusldo", 700, 1400, 50, 399 0x2e, __BITS(3, 0), 400 0x12, __BIT(6)), 401 }; 402 403 404 struct axppmic_irq { 405 u_int reg; 406 uint8_t mask; 407 }; 408 409 #define AXPPMIC_IRQ(_reg, _mask) \ 410 { .reg = (_reg), .mask = (_mask) } 411 412 struct axppmic_config { 413 const char *name; 414 const char *gpio_compat; 415 u_int gpio_npins; 416 const struct axppmic_ctrl *controls; 417 u_int ncontrols; 418 u_int irq_regs; 419 bool has_battery; 420 bool has_fuel_gauge; 421 bool has_mode_set; 422 struct axppmic_irq poklirq; 423 struct axppmic_irq acinirq; 424 struct axppmic_irq vbusirq; 425 struct axppmic_irq battirq; 426 struct axppmic_irq chargeirq; 427 struct axppmic_irq chargestirq; 428 u_int batsense_step; /* uV */ 429 u_int charge_step; /* uA */ 430 u_int discharge_step; /* uA */ 431 u_int maxcap_step; /* uAh */ 432 u_int coulomb_step; /* uAh */ 433 }; 434 435 enum axppmic_sensor { 436 AXP_SENSOR_ACIN_PRESENT, 437 AXP_SENSOR_VBUS_PRESENT, 438 AXP_SENSOR_BATT_PRESENT, 439 AXP_SENSOR_BATT_CHARGING, 440 AXP_SENSOR_BATT_CHARGE_STATE, 441 AXP_SENSOR_BATT_VOLTAGE, 442 AXP_SENSOR_BATT_CHARGE_CURRENT, 443 AXP_SENSOR_BATT_DISCHARGE_CURRENT, 444 AXP_SENSOR_BATT_CAPACITY_PERCENT, 445 AXP_SENSOR_BATT_MAXIMUM_CAPACITY, 446 AXP_SENSOR_BATT_CURRENT_CAPACITY, 447 AXP_NSENSORS 448 }; 449 450 struct axppmic_softc { 451 device_t sc_dev; 452 i2c_tag_t sc_i2c; 453 i2c_addr_t sc_addr; 454 int sc_phandle; 455 456 void *sc_ih; 457 struct workqueue *sc_wq; 458 459 kmutex_t sc_intr_lock; 460 struct work sc_work; 461 bool sc_work_scheduled; 462 463 const struct axppmic_config *sc_conf; 464 465 struct sysmon_pswitch sc_smpsw; 466 467 struct sysmon_envsys *sc_sme; 468 469 envsys_data_t sc_sensor[AXP_NSENSORS]; 470 471 u_int sc_warn_thres; 472 u_int sc_shut_thres; 473 }; 474 475 struct axppmic_gpio_pin { 476 struct axppmic_softc *pin_sc; 477 u_int pin_nr; 478 int pin_flags; 479 bool pin_actlo; 480 }; 481 482 struct axpreg_softc { 483 device_t sc_dev; 484 i2c_tag_t sc_i2c; 485 i2c_addr_t sc_addr; 486 const struct axppmic_ctrl *sc_ctrl; 487 }; 488 489 struct axpreg_attach_args { 490 const struct axppmic_ctrl *reg_ctrl; 491 int reg_phandle; 492 i2c_tag_t reg_i2c; 493 i2c_addr_t reg_addr; 494 }; 495 496 static const struct axppmic_config axp803_config = { 497 .name = "AXP803", 498 .gpio_compat = "x-powers,axp803-gpio", 499 .gpio_npins = 2, 500 .controls = axp803_ctrls, 501 .ncontrols = __arraycount(axp803_ctrls), 502 .irq_regs = 6, 503 .has_battery = true, 504 .has_fuel_gauge = true, 505 .batsense_step = 1100, 506 .charge_step = 1000, 507 .discharge_step = 1000, 508 .maxcap_step = 1456, 509 .coulomb_step = 1456, 510 .poklirq = AXPPMIC_IRQ(5, __BIT(3)), 511 .acinirq = AXPPMIC_IRQ(1, __BITS(6,5)), 512 .vbusirq = AXPPMIC_IRQ(1, __BITS(3,2)), 513 .battirq = AXPPMIC_IRQ(2, __BITS(7,6)), 514 .chargeirq = AXPPMIC_IRQ(2, __BITS(3,2)), 515 .chargestirq = AXPPMIC_IRQ(4, __BITS(1,0)), 516 }; 517 518 static const struct axppmic_config axp805_config = { 519 .name = "AXP805", 520 .controls = axp805_ctrls, 521 .ncontrols = __arraycount(axp805_ctrls), 522 .irq_regs = 2, 523 .poklirq = AXPPMIC_IRQ(2, __BIT(0)), 524 }; 525 526 static const struct axppmic_config axp806_config = { 527 .name = "AXP806", 528 .controls = axp805_ctrls, 529 .ncontrols = __arraycount(axp805_ctrls), 530 #if notyet 531 .irq_regs = 2, 532 .poklirq = AXPPMIC_IRQ(2, __BIT(0)), 533 #endif 534 .has_mode_set = true, 535 }; 536 537 static const struct axppmic_config axp809_config = { 538 .name = "AXP809", 539 .controls = axp809_ctrls, 540 .ncontrols = __arraycount(axp809_ctrls), 541 }; 542 543 static const struct axppmic_config axp813_config = { 544 .name = "AXP813", 545 .gpio_compat = "x-powers,axp813-gpio", 546 .gpio_npins = 2, 547 .controls = axp813_ctrls, 548 .ncontrols = __arraycount(axp813_ctrls), 549 .irq_regs = 6, 550 .has_battery = true, 551 .has_fuel_gauge = true, 552 .batsense_step = 1100, 553 .charge_step = 1000, 554 .discharge_step = 1000, 555 .maxcap_step = 1456, 556 .coulomb_step = 1456, 557 .poklirq = AXPPMIC_IRQ(5, __BIT(3)), 558 .acinirq = AXPPMIC_IRQ(1, __BITS(6,5)), 559 .vbusirq = AXPPMIC_IRQ(1, __BITS(3,2)), 560 .battirq = AXPPMIC_IRQ(2, __BITS(7,6)), 561 .chargeirq = AXPPMIC_IRQ(2, __BITS(3,2)), 562 .chargestirq = AXPPMIC_IRQ(4, __BITS(1,0)), 563 }; 564 565 static const struct axppmic_config axp15060_config = { 566 .name = "AXP15060", 567 .controls = axp15060_ctrls, 568 .ncontrols = __arraycount(axp15060_ctrls), 569 .irq_regs = 2, 570 .poklirq = AXPPMIC_IRQ(2, __BIT(3)), 571 }; 572 573 static const struct device_compatible_entry compat_data[] = { 574 { .compat = "x-powers,axp803", .data = &axp803_config }, 575 { .compat = "x-powers,axp805", .data = &axp805_config }, 576 { .compat = "x-powers,axp806", .data = &axp806_config }, 577 { .compat = "x-powers,axp809", .data = &axp809_config }, 578 { .compat = "x-powers,axp813", .data = &axp813_config }, 579 { .compat = "x-powers,axp15060", .data = &axp15060_config }, 580 DEVICE_COMPAT_EOL 581 }; 582 583 static int 584 axppmic_read(i2c_tag_t tag, i2c_addr_t addr, uint8_t reg, uint8_t *val, int flags) 585 { 586 return iic_smbus_read_byte(tag, addr, reg, val, flags); 587 } 588 589 static int 590 axppmic_write(i2c_tag_t tag, i2c_addr_t addr, uint8_t reg, uint8_t val, int flags) 591 { 592 return iic_smbus_write_byte(tag, addr, reg, val, flags); 593 } 594 595 static int 596 axppmic_set_voltage(i2c_tag_t tag, i2c_addr_t addr, const struct axppmic_ctrl *c, u_int min, u_int max) 597 { 598 u_int vol, reg_val; 599 int nstep, error; 600 uint8_t val; 601 602 if (!c->c_voltage_mask) 603 return EINVAL; 604 605 if (min < c->c_min || min > c->c_max) 606 return EINVAL; 607 608 reg_val = 0; 609 nstep = 1; 610 vol = c->c_min; 611 612 for (nstep = 0; nstep < c->c_step1cnt && vol < min; nstep++) { 613 ++reg_val; 614 vol += c->c_step1; 615 } 616 617 if (c->c_step2start) 618 vol = c->c_step2start; 619 620 for (nstep = 0; nstep < c->c_step2cnt && vol < min; nstep++) { 621 ++reg_val; 622 vol += c->c_step2; 623 } 624 625 if (vol > max) 626 return EINVAL; 627 628 iic_acquire_bus(tag, 0); 629 if ((error = axppmic_read(tag, addr, c->c_voltage_reg, &val, 0)) == 0) { 630 val &= ~c->c_voltage_mask; 631 val |= __SHIFTIN(reg_val, c->c_voltage_mask); 632 error = axppmic_write(tag, addr, c->c_voltage_reg, val, 0); 633 } 634 iic_release_bus(tag, 0); 635 636 return error; 637 } 638 639 static int 640 axppmic_get_voltage(i2c_tag_t tag, i2c_addr_t addr, const struct axppmic_ctrl *c, u_int *pvol) 641 { 642 int reg_val, error; 643 uint8_t val; 644 645 if (!c->c_voltage_mask) 646 return EINVAL; 647 648 iic_acquire_bus(tag, 0); 649 error = axppmic_read(tag, addr, c->c_voltage_reg, &val, 0); 650 iic_release_bus(tag, 0); 651 if (error) 652 return error; 653 654 reg_val = __SHIFTOUT(val, c->c_voltage_mask); 655 if (reg_val < c->c_step1cnt) { 656 *pvol = c->c_min + reg_val * c->c_step1; 657 } else if (c->c_step2start) { 658 *pvol = c->c_step2start + 659 ((reg_val - c->c_step1cnt) * c->c_step2); 660 } else { 661 *pvol = c->c_min + (c->c_step1cnt * c->c_step1) + 662 ((reg_val - c->c_step1cnt) * c->c_step2); 663 } 664 665 return 0; 666 } 667 668 static void 669 axppmic_power_poweroff(device_t dev) 670 { 671 struct axppmic_softc *sc = device_private(dev); 672 int error; 673 674 delay(1000000); 675 676 error = iic_acquire_bus(sc->sc_i2c, 0); 677 if (error == 0) { 678 error = axppmic_write(sc->sc_i2c, sc->sc_addr, 679 AXP_POWER_DISABLE_REG, AXP_POWER_DISABLE_CTRL, 0); 680 iic_release_bus(sc->sc_i2c, 0); 681 } 682 if (error) { 683 device_printf(dev, "WARNING: unable to power off, error %d\n", 684 error); 685 } 686 } 687 688 static struct fdtbus_power_controller_func axppmic_power_funcs = { 689 .poweroff = axppmic_power_poweroff, 690 }; 691 692 static int 693 axppmic_gpio_ctl(struct axppmic_softc *sc, uint8_t pin, uint8_t func) 694 { 695 uint8_t val; 696 int error; 697 698 KASSERT(pin < sc->sc_conf->gpio_npins); 699 KASSERT((func & ~AXP_GPIO_CTRL_FUNC_MASK) == 0); 700 701 iic_acquire_bus(sc->sc_i2c, 0); 702 error = axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_GPIO_CTRL_REG(pin), 703 &val, 0); 704 if (error == 0) { 705 val &= ~AXP_GPIO_CTRL_FUNC_MASK; 706 val |= func; 707 error = axppmic_write(sc->sc_i2c, sc->sc_addr, 708 AXP_GPIO_CTRL_REG(pin), val, 0); 709 } 710 iic_release_bus(sc->sc_i2c, 0); 711 712 return error; 713 } 714 715 static void * 716 axppmic_gpio_acquire(device_t dev, const void *data, size_t len, int flags) 717 { 718 struct axppmic_softc *sc = device_private(dev); 719 struct axppmic_gpio_pin *gpin; 720 const u_int *gpio = data; 721 int error; 722 723 if (len != 12) { 724 return NULL; 725 } 726 727 const uint8_t pin = be32toh(gpio[1]) & 0xff; 728 const bool actlo = be32toh(gpio[2]) & 1; 729 730 if (pin >= sc->sc_conf->gpio_npins) { 731 return NULL; 732 } 733 734 if ((flags & GPIO_PIN_INPUT) != 0) { 735 error = axppmic_gpio_ctl(sc, pin, AXP_GPIO_CTRL_FUNC_INPUT); 736 if (error != 0) { 737 return NULL; 738 } 739 } 740 741 gpin = kmem_zalloc(sizeof(*gpin), KM_SLEEP); 742 gpin->pin_sc = sc; 743 gpin->pin_nr = pin; 744 gpin->pin_flags = flags; 745 gpin->pin_actlo = actlo; 746 747 return gpin; 748 } 749 750 static void 751 axppmic_gpio_release(device_t dev, void *priv) 752 { 753 struct axppmic_softc *sc = device_private(dev); 754 struct axppmic_gpio_pin *gpin = priv; 755 756 axppmic_gpio_ctl(sc, gpin->pin_nr, AXP_GPIO_CTRL_FUNC_INPUT); 757 758 kmem_free(gpin, sizeof(*gpin)); 759 } 760 761 static int 762 axppmic_gpio_read(device_t dev, void *priv, bool raw) 763 { 764 struct axppmic_softc *sc = device_private(dev); 765 struct axppmic_gpio_pin *gpin = priv; 766 uint8_t data; 767 int error, val; 768 769 KASSERT(sc == gpin->pin_sc); 770 771 const uint8_t data_mask = __BIT(gpin->pin_nr); 772 773 iic_acquire_bus(sc->sc_i2c, 0); 774 error = axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_GPIO_SIGNAL_REG, 775 &data, 0); 776 iic_release_bus(sc->sc_i2c, 0); 777 778 if (error != 0) { 779 device_printf(dev, "WARNING: failed to read pin %d: %d\n", 780 gpin->pin_nr, error); 781 val = 0; 782 } else { 783 val = __SHIFTOUT(data, data_mask); 784 } 785 if (!raw && gpin->pin_actlo) { 786 val = !val; 787 } 788 789 return val; 790 } 791 792 static void 793 axppmic_gpio_write(device_t dev, void *priv, int val, bool raw) 794 { 795 struct axppmic_softc *sc = device_private(dev); 796 struct axppmic_gpio_pin *gpin = priv; 797 int error; 798 799 if (!raw && gpin->pin_actlo) { 800 val = !val; 801 } 802 803 error = axppmic_gpio_ctl(sc, gpin->pin_nr, 804 val == 0 ? AXP_GPIO_CTRL_FUNC_LOW : AXP_GPIO_CTRL_FUNC_HIGH); 805 if (error != 0) { 806 device_printf(dev, "WARNING: failed to write pin %d: %d\n", 807 gpin->pin_nr, error); 808 } 809 } 810 811 static struct fdtbus_gpio_controller_func axppmic_gpio_funcs = { 812 .acquire = axppmic_gpio_acquire, 813 .release = axppmic_gpio_release, 814 .read = axppmic_gpio_read, 815 .write = axppmic_gpio_write, 816 }; 817 818 static void 819 axppmic_task_shut(void *priv) 820 { 821 struct axppmic_softc *sc = priv; 822 823 sysmon_pswitch_event(&sc->sc_smpsw, PSWITCH_EVENT_PRESSED); 824 } 825 826 static void 827 axppmic_sensor_update(struct sysmon_envsys *sme, envsys_data_t *e) 828 { 829 struct axppmic_softc *sc = sme->sme_cookie; 830 const struct axppmic_config *c = sc->sc_conf; 831 uint8_t val, lo, hi; 832 833 e->state = ENVSYS_SINVALID; 834 835 const bool battery_present = 836 sc->sc_sensor[AXP_SENSOR_BATT_PRESENT].state == ENVSYS_SVALID && 837 sc->sc_sensor[AXP_SENSOR_BATT_PRESENT].value_cur == 1; 838 839 switch (e->private) { 840 case AXP_SENSOR_ACIN_PRESENT: 841 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_SOURCE_REG, &val, 0) == 0) { 842 e->state = ENVSYS_SVALID; 843 e->value_cur = !!(val & AXP_POWER_SOURCE_ACIN_PRESENT); 844 } 845 break; 846 case AXP_SENSOR_VBUS_PRESENT: 847 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_SOURCE_REG, &val, 0) == 0) { 848 e->state = ENVSYS_SVALID; 849 e->value_cur = !!(val & AXP_POWER_SOURCE_VBUS_PRESENT); 850 } 851 break; 852 case AXP_SENSOR_BATT_PRESENT: 853 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_MODE_REG, &val, 0) == 0) { 854 if (val & AXP_POWER_MODE_BATT_VALID) { 855 e->state = ENVSYS_SVALID; 856 e->value_cur = !!(val & AXP_POWER_MODE_BATT_PRESENT); 857 } 858 } 859 break; 860 case AXP_SENSOR_BATT_CHARGING: 861 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_MODE_REG, &val, 0) == 0) { 862 e->state = ENVSYS_SVALID; 863 e->value_cur = !!(val & AXP_POWER_MODE_BATT_CHARGING); 864 } 865 break; 866 case AXP_SENSOR_BATT_CHARGE_STATE: 867 if (battery_present && 868 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_CAP_REG, &val, 0) == 0 && 869 (val & AXP_BATT_CAP_VALID) != 0) { 870 const u_int batt_val = __SHIFTOUT(val, AXP_BATT_CAP_PERCENT); 871 if (batt_val <= sc->sc_shut_thres) { 872 e->state = ENVSYS_SCRITICAL; 873 e->value_cur = ENVSYS_BATTERY_CAPACITY_CRITICAL; 874 } else if (batt_val <= sc->sc_warn_thres) { 875 e->state = ENVSYS_SWARNUNDER; 876 e->value_cur = ENVSYS_BATTERY_CAPACITY_WARNING; 877 } else { 878 e->state = ENVSYS_SVALID; 879 e->value_cur = ENVSYS_BATTERY_CAPACITY_NORMAL; 880 } 881 } 882 break; 883 case AXP_SENSOR_BATT_CAPACITY_PERCENT: 884 if (battery_present && 885 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_CAP_REG, &val, 0) == 0 && 886 (val & AXP_BATT_CAP_VALID) != 0) { 887 e->state = ENVSYS_SVALID; 888 e->value_cur = __SHIFTOUT(val, AXP_BATT_CAP_PERCENT); 889 } 890 break; 891 case AXP_SENSOR_BATT_VOLTAGE: 892 if (battery_present && 893 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATSENSE_HI_REG, &hi, 0) == 0 && 894 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATSENSE_LO_REG, &lo, 0) == 0) { 895 e->state = ENVSYS_SVALID; 896 e->value_cur = AXP_ADC_RAW(hi, lo) * c->batsense_step; 897 } 898 break; 899 case AXP_SENSOR_BATT_CHARGE_CURRENT: 900 if (battery_present && 901 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_SOURCE_REG, &val, 0) == 0 && 902 (val & AXP_POWER_SOURCE_CHARGE_DIRECTION) != 0 && 903 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATTCHG_HI_REG, &hi, 0) == 0 && 904 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATTCHG_LO_REG, &lo, 0) == 0) { 905 e->state = ENVSYS_SVALID; 906 e->value_cur = AXP_ADC_RAW(hi, lo) * c->charge_step; 907 } 908 break; 909 case AXP_SENSOR_BATT_DISCHARGE_CURRENT: 910 if (battery_present && 911 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_SOURCE_REG, &val, 0) == 0 && 912 (val & AXP_POWER_SOURCE_CHARGE_DIRECTION) == 0 && 913 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATTDISCHG_HI_REG, &hi, 0) == 0 && 914 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATTDISCHG_LO_REG, &lo, 0) == 0) { 915 e->state = ENVSYS_SVALID; 916 e->value_cur = AXP_ADC_RAW(hi, lo) * c->discharge_step; 917 } 918 break; 919 case AXP_SENSOR_BATT_MAXIMUM_CAPACITY: 920 if (battery_present && 921 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_MAX_CAP_HI_REG, &hi, 0) == 0 && 922 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_MAX_CAP_LO_REG, &lo, 0) == 0) { 923 e->state = (hi & AXP_BATT_MAX_CAP_VALID) ? ENVSYS_SVALID : ENVSYS_SINVALID; 924 e->value_cur = AXP_COULOMB_RAW(hi, lo) * c->maxcap_step; 925 } 926 break; 927 case AXP_SENSOR_BATT_CURRENT_CAPACITY: 928 if (battery_present && 929 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_COULOMB_HI_REG, &hi, 0) == 0 && 930 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_COULOMB_LO_REG, &lo, 0) == 0) { 931 e->state = (hi & AXP_BATT_COULOMB_VALID) ? ENVSYS_SVALID : ENVSYS_SINVALID; 932 e->value_cur = AXP_COULOMB_RAW(hi, lo) * c->coulomb_step; 933 } 934 break; 935 } 936 } 937 938 static void 939 axppmic_sensor_refresh(struct sysmon_envsys *sme, envsys_data_t *e) 940 { 941 struct axppmic_softc *sc = sme->sme_cookie; 942 943 switch (e->private) { 944 case AXP_SENSOR_BATT_CAPACITY_PERCENT: 945 case AXP_SENSOR_BATT_VOLTAGE: 946 case AXP_SENSOR_BATT_CHARGE_CURRENT: 947 case AXP_SENSOR_BATT_DISCHARGE_CURRENT: 948 /* Always update battery capacity and ADCs */ 949 iic_acquire_bus(sc->sc_i2c, 0); 950 axppmic_sensor_update(sme, e); 951 iic_release_bus(sc->sc_i2c, 0); 952 break; 953 default: 954 /* Refresh if the sensor is not in valid state */ 955 if (e->state != ENVSYS_SVALID) { 956 iic_acquire_bus(sc->sc_i2c, 0); 957 axppmic_sensor_update(sme, e); 958 iic_release_bus(sc->sc_i2c, 0); 959 } 960 break; 961 } 962 } 963 964 static int 965 axppmic_intr(void *priv) 966 { 967 struct axppmic_softc * const sc = priv; 968 969 mutex_enter(&sc->sc_intr_lock); 970 971 fdtbus_intr_mask(sc->sc_phandle, sc->sc_ih); 972 973 /* Interrupt is always masked when work is scheduled! */ 974 KASSERT(!sc->sc_work_scheduled); 975 sc->sc_work_scheduled = true; 976 workqueue_enqueue(sc->sc_wq, &sc->sc_work, NULL); 977 978 mutex_exit(&sc->sc_intr_lock); 979 980 return 1; 981 } 982 983 static void 984 axppmic_work(struct work *work, void *arg) 985 { 986 struct axppmic_softc * const sc = 987 container_of(work, struct axppmic_softc, sc_work); 988 const struct axppmic_config * const c = sc->sc_conf; 989 const int flags = 0; 990 uint8_t stat; 991 u_int n; 992 993 KASSERT(sc->sc_work_scheduled); 994 995 iic_acquire_bus(sc->sc_i2c, flags); 996 for (n = 1; n <= c->irq_regs; n++) { 997 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_IRQ_STATUS_REG(n), &stat, flags) == 0) { 998 if (stat != 0) { 999 axppmic_write(sc->sc_i2c, sc->sc_addr, 1000 AXP_IRQ_STATUS_REG(n), stat, flags); 1001 } 1002 1003 if (n == c->poklirq.reg && (stat & c->poklirq.mask) != 0) 1004 sysmon_task_queue_sched(0, axppmic_task_shut, sc); 1005 if (n == c->acinirq.reg && (stat & c->acinirq.mask) != 0) 1006 axppmic_sensor_update(sc->sc_sme, &sc->sc_sensor[AXP_SENSOR_ACIN_PRESENT]); 1007 if (n == c->vbusirq.reg && (stat & c->vbusirq.mask) != 0) 1008 axppmic_sensor_update(sc->sc_sme, &sc->sc_sensor[AXP_SENSOR_VBUS_PRESENT]); 1009 if (n == c->battirq.reg && (stat & c->battirq.mask) != 0) 1010 axppmic_sensor_update(sc->sc_sme, &sc->sc_sensor[AXP_SENSOR_BATT_PRESENT]); 1011 if (n == c->chargeirq.reg && (stat & c->chargeirq.mask) != 0) 1012 axppmic_sensor_update(sc->sc_sme, &sc->sc_sensor[AXP_SENSOR_BATT_CHARGING]); 1013 if (n == c->chargestirq.reg && (stat & c->chargestirq.mask) != 0) 1014 axppmic_sensor_update(sc->sc_sme, &sc->sc_sensor[AXP_SENSOR_BATT_CHARGE_STATE]); 1015 } 1016 } 1017 iic_release_bus(sc->sc_i2c, flags); 1018 1019 mutex_enter(&sc->sc_intr_lock); 1020 sc->sc_work_scheduled = false; 1021 fdtbus_intr_unmask(sc->sc_phandle, sc->sc_ih); 1022 mutex_exit(&sc->sc_intr_lock); 1023 } 1024 1025 static void 1026 axppmic_attach_acadapter(struct axppmic_softc *sc) 1027 { 1028 envsys_data_t *e; 1029 1030 e = &sc->sc_sensor[AXP_SENSOR_ACIN_PRESENT]; 1031 e->private = AXP_SENSOR_ACIN_PRESENT; 1032 e->units = ENVSYS_INDICATOR; 1033 e->state = ENVSYS_SINVALID; 1034 strlcpy(e->desc, "ACIN present", sizeof(e->desc)); 1035 sysmon_envsys_sensor_attach(sc->sc_sme, e); 1036 1037 e = &sc->sc_sensor[AXP_SENSOR_VBUS_PRESENT]; 1038 e->private = AXP_SENSOR_VBUS_PRESENT; 1039 e->units = ENVSYS_INDICATOR; 1040 e->state = ENVSYS_SINVALID; 1041 strlcpy(e->desc, "VBUS present", sizeof(e->desc)); 1042 sysmon_envsys_sensor_attach(sc->sc_sme, e); 1043 } 1044 1045 static void 1046 axppmic_attach_battery(struct axppmic_softc *sc) 1047 { 1048 const struct axppmic_config *c = sc->sc_conf; 1049 envsys_data_t *e; 1050 uint8_t val; 1051 1052 iic_acquire_bus(sc->sc_i2c, 0); 1053 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_CAP_WARN_REG, &val, 0) == 0) { 1054 sc->sc_warn_thres = __SHIFTOUT(val, AXP_BATT_CAP_WARN_LV1) + 5; 1055 sc->sc_shut_thres = __SHIFTOUT(val, AXP_BATT_CAP_WARN_LV2); 1056 } 1057 iic_release_bus(sc->sc_i2c, 0); 1058 1059 e = &sc->sc_sensor[AXP_SENSOR_BATT_PRESENT]; 1060 e->private = AXP_SENSOR_BATT_PRESENT; 1061 e->units = ENVSYS_INDICATOR; 1062 e->state = ENVSYS_SINVALID; 1063 strlcpy(e->desc, "battery present", sizeof(e->desc)); 1064 sysmon_envsys_sensor_attach(sc->sc_sme, e); 1065 1066 e = &sc->sc_sensor[AXP_SENSOR_BATT_CHARGING]; 1067 e->private = AXP_SENSOR_BATT_CHARGING; 1068 e->units = ENVSYS_BATTERY_CHARGE; 1069 e->state = ENVSYS_SINVALID; 1070 strlcpy(e->desc, "charging", sizeof(e->desc)); 1071 sysmon_envsys_sensor_attach(sc->sc_sme, e); 1072 1073 e = &sc->sc_sensor[AXP_SENSOR_BATT_CHARGE_STATE]; 1074 e->private = AXP_SENSOR_BATT_CHARGE_STATE; 1075 e->units = ENVSYS_BATTERY_CAPACITY; 1076 e->flags = ENVSYS_FMONSTCHANGED; 1077 e->state = ENVSYS_SINVALID; 1078 e->value_cur = ENVSYS_BATTERY_CAPACITY_NORMAL; 1079 strlcpy(e->desc, "charge state", sizeof(e->desc)); 1080 sysmon_envsys_sensor_attach(sc->sc_sme, e); 1081 1082 if (c->batsense_step) { 1083 e = &sc->sc_sensor[AXP_SENSOR_BATT_VOLTAGE]; 1084 e->private = AXP_SENSOR_BATT_VOLTAGE; 1085 e->units = ENVSYS_SVOLTS_DC; 1086 e->state = ENVSYS_SINVALID; 1087 strlcpy(e->desc, "battery voltage", sizeof(e->desc)); 1088 sysmon_envsys_sensor_attach(sc->sc_sme, e); 1089 } 1090 1091 if (c->charge_step) { 1092 e = &sc->sc_sensor[AXP_SENSOR_BATT_CHARGE_CURRENT]; 1093 e->private = AXP_SENSOR_BATT_CHARGE_CURRENT; 1094 e->units = ENVSYS_SAMPS; 1095 e->state = ENVSYS_SINVALID; 1096 strlcpy(e->desc, "battery charge current", sizeof(e->desc)); 1097 sysmon_envsys_sensor_attach(sc->sc_sme, e); 1098 } 1099 1100 if (c->discharge_step) { 1101 e = &sc->sc_sensor[AXP_SENSOR_BATT_DISCHARGE_CURRENT]; 1102 e->private = AXP_SENSOR_BATT_DISCHARGE_CURRENT; 1103 e->units = ENVSYS_SAMPS; 1104 e->state = ENVSYS_SINVALID; 1105 strlcpy(e->desc, "battery discharge current", sizeof(e->desc)); 1106 sysmon_envsys_sensor_attach(sc->sc_sme, e); 1107 } 1108 1109 if (c->has_fuel_gauge) { 1110 e = &sc->sc_sensor[AXP_SENSOR_BATT_CAPACITY_PERCENT]; 1111 e->private = AXP_SENSOR_BATT_CAPACITY_PERCENT; 1112 e->units = ENVSYS_INTEGER; 1113 e->state = ENVSYS_SINVALID; 1114 e->flags = ENVSYS_FPERCENT; 1115 strlcpy(e->desc, "battery percent", sizeof(e->desc)); 1116 sysmon_envsys_sensor_attach(sc->sc_sme, e); 1117 } 1118 1119 if (c->maxcap_step) { 1120 e = &sc->sc_sensor[AXP_SENSOR_BATT_MAXIMUM_CAPACITY]; 1121 e->private = AXP_SENSOR_BATT_MAXIMUM_CAPACITY; 1122 e->units = ENVSYS_SAMPHOUR; 1123 e->state = ENVSYS_SINVALID; 1124 strlcpy(e->desc, "battery maximum capacity", sizeof(e->desc)); 1125 sysmon_envsys_sensor_attach(sc->sc_sme, e); 1126 } 1127 1128 if (c->coulomb_step) { 1129 e = &sc->sc_sensor[AXP_SENSOR_BATT_CURRENT_CAPACITY]; 1130 e->private = AXP_SENSOR_BATT_CURRENT_CAPACITY; 1131 e->units = ENVSYS_SAMPHOUR; 1132 e->state = ENVSYS_SINVALID; 1133 strlcpy(e->desc, "battery current capacity", sizeof(e->desc)); 1134 sysmon_envsys_sensor_attach(sc->sc_sme, e); 1135 } 1136 } 1137 1138 static void 1139 axppmic_attach_sensors(struct axppmic_softc *sc) 1140 { 1141 if (sc->sc_conf->has_battery) { 1142 sc->sc_sme = sysmon_envsys_create(); 1143 sc->sc_sme->sme_name = device_xname(sc->sc_dev); 1144 sc->sc_sme->sme_cookie = sc; 1145 sc->sc_sme->sme_refresh = axppmic_sensor_refresh; 1146 sc->sc_sme->sme_class = SME_CLASS_BATTERY; 1147 sc->sc_sme->sme_flags = SME_INIT_REFRESH; 1148 1149 axppmic_attach_acadapter(sc); 1150 axppmic_attach_battery(sc); 1151 1152 sysmon_envsys_register(sc->sc_sme); 1153 } 1154 } 1155 1156 1157 static int 1158 axppmic_match(device_t parent, cfdata_t match, void *aux) 1159 { 1160 struct i2c_attach_args *ia = aux; 1161 int match_result; 1162 1163 if (iic_use_direct_match(ia, match, compat_data, &match_result)) 1164 return match_result; 1165 1166 /* This device is direct-config only. */ 1167 1168 return 0; 1169 } 1170 1171 static void 1172 axppmic_attach(device_t parent, device_t self, void *aux) 1173 { 1174 struct axppmic_softc *sc = device_private(self); 1175 const struct device_compatible_entry *dce = NULL; 1176 const struct axppmic_config *c; 1177 struct axpreg_attach_args aaa; 1178 struct i2c_attach_args *ia = aux; 1179 int phandle, child, i; 1180 uint8_t irq_mask, val; 1181 int error; 1182 1183 dce = iic_compatible_lookup(ia, compat_data); 1184 KASSERT(dce != NULL); 1185 c = dce->data; 1186 1187 sc->sc_dev = self; 1188 sc->sc_i2c = ia->ia_tag; 1189 sc->sc_addr = ia->ia_addr; 1190 sc->sc_phandle = ia->ia_cookie; 1191 sc->sc_conf = c; 1192 1193 aprint_naive("\n"); 1194 aprint_normal(": %s\n", c->name); 1195 1196 if (c->has_mode_set) { 1197 const bool master_mode = 1198 of_hasprop(sc->sc_phandle, "x-powers,self-working-mode") || 1199 of_hasprop(sc->sc_phandle, "x-powers,master-mode"); 1200 1201 iic_acquire_bus(sc->sc_i2c, 0); 1202 axppmic_write(sc->sc_i2c, sc->sc_addr, AXP_ADDR_EXT_REG, 1203 master_mode ? AXP_ADDR_EXT_MASTER : AXP_ADDR_EXT_SLAVE, 0); 1204 iic_release_bus(sc->sc_i2c, 0); 1205 } 1206 1207 iic_acquire_bus(sc->sc_i2c, 0); 1208 error = axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_CHIP_ID_REG, &val, 0); 1209 iic_release_bus(sc->sc_i2c, 0); 1210 if (error != 0) { 1211 aprint_error_dev(self, "couldn't read chipid\n"); 1212 return; 1213 } 1214 aprint_debug_dev(self, "chipid %#x\n", val); 1215 1216 sc->sc_smpsw.smpsw_name = device_xname(self); 1217 sc->sc_smpsw.smpsw_type = PSWITCH_TYPE_POWER; 1218 sysmon_pswitch_register(&sc->sc_smpsw); 1219 1220 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_VM); 1221 1222 if (c->irq_regs > 0) { 1223 char intrstr[128]; 1224 1225 if (!fdtbus_intr_str(sc->sc_phandle, 0, 1226 intrstr, sizeof(intrstr))) { 1227 aprint_error_dev(self, 1228 "WARNING: failed to decode interrupt\n"); 1229 } 1230 1231 sc->sc_ih = fdtbus_intr_establish(sc->sc_phandle, 0, IPL_VM, 1232 FDT_INTR_MPSAFE, 1233 axppmic_intr, sc); 1234 if (sc->sc_ih == NULL) { 1235 aprint_error_dev(self, 1236 "WARNING: couldn't establish interrupt handler\n"); 1237 } 1238 1239 error = workqueue_create(&sc->sc_wq, device_xname(self), 1240 axppmic_work, NULL, 1241 PRI_SOFTSERIAL, IPL_VM, 1242 WQ_MPSAFE); 1243 if (error) { 1244 sc->sc_wq = NULL; 1245 aprint_error_dev(self, 1246 "WARNING: couldn't create work queue: error %d\n", 1247 error); 1248 } 1249 1250 if (sc->sc_ih != NULL && sc->sc_wq != NULL) { 1251 iic_acquire_bus(sc->sc_i2c, 0); 1252 for (i = 1; i <= c->irq_regs; i++) { 1253 irq_mask = 0; 1254 if (i == c->poklirq.reg) 1255 irq_mask |= c->poklirq.mask; 1256 if (i == c->acinirq.reg) 1257 irq_mask |= c->acinirq.mask; 1258 if (i == c->vbusirq.reg) 1259 irq_mask |= c->vbusirq.mask; 1260 if (i == c->battirq.reg) 1261 irq_mask |= c->battirq.mask; 1262 if (i == c->chargeirq.reg) 1263 irq_mask |= c->chargeirq.mask; 1264 if (i == c->chargestirq.reg) 1265 irq_mask |= c->chargestirq.mask; 1266 axppmic_write(sc->sc_i2c, sc->sc_addr, 1267 AXP_IRQ_ENABLE_REG(i), 1268 irq_mask, 0); 1269 } 1270 iic_release_bus(sc->sc_i2c, 0); 1271 } 1272 } 1273 1274 fdtbus_register_power_controller(sc->sc_dev, sc->sc_phandle, 1275 &axppmic_power_funcs); 1276 1277 if (c->gpio_compat != NULL) { 1278 phandle = of_find_bycompat(sc->sc_phandle, c->gpio_compat); 1279 if (phandle > 0) { 1280 fdtbus_register_gpio_controller(self, phandle, 1281 &axppmic_gpio_funcs); 1282 } 1283 } 1284 1285 phandle = of_find_firstchild_byname(sc->sc_phandle, "regulators"); 1286 if (phandle > 0) { 1287 aaa.reg_i2c = sc->sc_i2c; 1288 aaa.reg_addr = sc->sc_addr; 1289 for (i = 0; i < c->ncontrols; i++) { 1290 const struct axppmic_ctrl *ctrl = &c->controls[i]; 1291 child = of_find_firstchild_byname(phandle, ctrl->c_name); 1292 if (child <= 0) 1293 continue; 1294 aaa.reg_ctrl = ctrl; 1295 aaa.reg_phandle = child; 1296 config_found(sc->sc_dev, &aaa, NULL, CFARGS_NONE); 1297 } 1298 } 1299 1300 if (c->has_battery) 1301 axppmic_attach_sensors(sc); 1302 } 1303 1304 static int 1305 axpreg_acquire(device_t dev) 1306 { 1307 return 0; 1308 } 1309 1310 static void 1311 axpreg_release(device_t dev) 1312 { 1313 } 1314 1315 static int 1316 axpreg_enable(device_t dev, bool enable) 1317 { 1318 struct axpreg_softc *sc = device_private(dev); 1319 const struct axppmic_ctrl *c = sc->sc_ctrl; 1320 const int flags = 0; 1321 uint8_t val; 1322 int error; 1323 1324 if (!c->c_enable_mask) 1325 return EINVAL; 1326 1327 iic_acquire_bus(sc->sc_i2c, flags); 1328 if ((error = axppmic_read(sc->sc_i2c, sc->sc_addr, c->c_enable_reg, &val, flags)) == 0) { 1329 val &= ~c->c_enable_mask; 1330 if (enable) 1331 val |= c->c_enable_val; 1332 else 1333 val |= c->c_disable_val; 1334 error = axppmic_write(sc->sc_i2c, sc->sc_addr, c->c_enable_reg, val, flags); 1335 } 1336 iic_release_bus(sc->sc_i2c, flags); 1337 1338 return error; 1339 } 1340 1341 static int 1342 axpreg_set_voltage(device_t dev, u_int min_uvol, u_int max_uvol) 1343 { 1344 struct axpreg_softc *sc = device_private(dev); 1345 const struct axppmic_ctrl *c = sc->sc_ctrl; 1346 1347 return axppmic_set_voltage(sc->sc_i2c, sc->sc_addr, c, 1348 min_uvol / 1000, max_uvol / 1000); 1349 } 1350 1351 static int 1352 axpreg_get_voltage(device_t dev, u_int *puvol) 1353 { 1354 struct axpreg_softc *sc = device_private(dev); 1355 const struct axppmic_ctrl *c = sc->sc_ctrl; 1356 int error; 1357 u_int vol; 1358 1359 error = axppmic_get_voltage(sc->sc_i2c, sc->sc_addr, c, &vol); 1360 if (error) 1361 return error; 1362 1363 *puvol = vol * 1000; 1364 return 0; 1365 } 1366 1367 static struct fdtbus_regulator_controller_func axpreg_funcs = { 1368 .acquire = axpreg_acquire, 1369 .release = axpreg_release, 1370 .enable = axpreg_enable, 1371 .set_voltage = axpreg_set_voltage, 1372 .get_voltage = axpreg_get_voltage, 1373 }; 1374 1375 static int 1376 axpreg_match(device_t parent, cfdata_t match, void *aux) 1377 { 1378 return 1; 1379 } 1380 1381 static void 1382 axpreg_attach(device_t parent, device_t self, void *aux) 1383 { 1384 struct axpreg_softc *sc = device_private(self); 1385 struct axpreg_attach_args *aaa = aux; 1386 const int phandle = aaa->reg_phandle; 1387 const char *name; 1388 u_int uvol, min_uvol, max_uvol; 1389 1390 sc->sc_dev = self; 1391 sc->sc_i2c = aaa->reg_i2c; 1392 sc->sc_addr = aaa->reg_addr; 1393 sc->sc_ctrl = aaa->reg_ctrl; 1394 1395 fdtbus_register_regulator_controller(self, phandle, 1396 &axpreg_funcs); 1397 1398 aprint_naive("\n"); 1399 name = fdtbus_get_string(phandle, "regulator-name"); 1400 if (name) 1401 aprint_normal(": %s\n", name); 1402 else 1403 aprint_normal("\n"); 1404 1405 int error = axpreg_get_voltage(self, &uvol); 1406 if (error) 1407 return; 1408 1409 if (of_getprop_uint32(phandle, "regulator-min-microvolt", &min_uvol) == 0 && 1410 of_getprop_uint32(phandle, "regulator-max-microvolt", &max_uvol) == 0) { 1411 if (uvol < min_uvol || uvol > max_uvol) { 1412 aprint_debug_dev(self, "fix voltage %u uV -> %u/%u uV\n", 1413 uvol, min_uvol, max_uvol); 1414 axpreg_set_voltage(self, min_uvol, max_uvol); 1415 } 1416 } 1417 1418 if (of_hasprop(phandle, "regulator-always-on") || 1419 of_hasprop(phandle, "regulator-boot-on")) { 1420 axpreg_enable(self, true); 1421 } 1422 } 1423 1424 CFATTACH_DECL_NEW(axppmic, sizeof(struct axppmic_softc), 1425 axppmic_match, axppmic_attach, NULL, NULL); 1426 1427 CFATTACH_DECL_NEW(axpreg, sizeof(struct axpreg_softc), 1428 axpreg_match, axpreg_attach, NULL, NULL); 1429
Indexes created Fri Oct 03 02:09:57 GMT 2025