axppmic.c revision 1.42
1 /* $NetBSD: axppmic.c,v 1.42 2025/09/17 13:42:42 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2014-2018 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: axppmic.c,v 1.42 2025/09/17 13:42:42 thorpej Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/device.h> 36 #include <sys/conf.h> 37 #include <sys/bus.h> 38 #include <sys/kmem.h> 39 #include <sys/workqueue.h> 40 41 #include <dev/i2c/i2cvar.h> 42 43 #include <dev/sysmon/sysmonvar.h> 44 #include <dev/sysmon/sysmon_taskq.h> 45 46 #include <dev/fdt/fdtvar.h> 47 48 #define AXP_POWER_SOURCE_REG 0x00 49 #define AXP_POWER_SOURCE_ACIN_PRESENT __BIT(7) 50 #define AXP_POWER_SOURCE_VBUS_PRESENT __BIT(5) 51 #define AXP_POWER_SOURCE_CHARGE_DIRECTION __BIT(2) 52 53 #define AXP_POWER_MODE_REG 0x01 54 #define AXP_POWER_MODE_BATT_VALID __BIT(4) 55 #define AXP_POWER_MODE_BATT_PRESENT __BIT(5) 56 #define AXP_POWER_MODE_BATT_CHARGING __BIT(6) 57 58 #define AXP_CHIP_ID_REG 0x03 59 60 #define AXP_POWER_DISABLE_REG 0x32 61 #define AXP_POWER_DISABLE_CTRL __BIT(7) 62 63 #define AXP_IRQ_ENABLE_REG(n) (0x40 + (n) - 1) 64 #define AXP_IRQ1_ACIN_RAISE __BIT(6) 65 #define AXP_IRQ1_ACIN_LOWER __BIT(5) 66 #define AXP_IRQ1_VBUS_RAISE __BIT(3) 67 #define AXP_IRQ1_VBUS_LOWER __BIT(2) 68 #define AXP_IRQ_STATUS_REG(n) (0x48 + (n) - 1) 69 70 #define AXP_BATSENSE_HI_REG 0x78 71 #define AXP_BATSENSE_LO_REG 0x79 72 73 #define AXP_BATTCHG_HI_REG 0x7a 74 #define AXP_BATTCHG_LO_REG 0x7b 75 76 #define AXP_BATTDISCHG_HI_REG 0x7c 77 #define AXP_BATTDISCHG_LO_REG 0x7d 78 79 #define AXP_ADC_RAW(_hi, _lo) \ 80 (((u_int)(_hi) << 4) | ((_lo) & 0xf)) 81 82 #define AXP_GPIO_CTRL_REG(pin) (0x90 + (pin) * 2) 83 #define AXP_GPIO_CTRL_FUNC_MASK __BITS(2,0) 84 #define AXP_GPIO_CTRL_FUNC_LOW 0 85 #define AXP_GPIO_CTRL_FUNC_HIGH 1 86 #define AXP_GPIO_CTRL_FUNC_INPUT 2 87 #define AXP_GPIO_SIGNAL_REG 0x94 88 89 #define AXP_FUEL_GAUGE_CTRL_REG 0xb8 90 #define AXP_FUEL_GAUGE_CTRL_EN __BIT(7) 91 92 #define AXP_BATT_CAP_REG 0xb9 93 #define AXP_BATT_CAP_VALID __BIT(7) 94 #define AXP_BATT_CAP_PERCENT __BITS(6,0) 95 96 #define AXP_BATT_MAX_CAP_HI_REG 0xe0 97 #define AXP_BATT_MAX_CAP_VALID __BIT(7) 98 #define AXP_BATT_MAX_CAP_LO_REG 0xe1 99 100 #define AXP_BATT_COULOMB_HI_REG 0xe2 101 #define AXP_BATT_COULOMB_VALID __BIT(7) 102 #define AXP_BATT_COULOMB_LO_REG 0xe3 103 104 #define AXP_COULOMB_RAW(_hi, _lo) \ 105 (((u_int)(_hi & ~__BIT(7)) << 8) | (_lo)) 106 107 #define AXP_BATT_CAP_WARN_REG 0xe6 108 #define AXP_BATT_CAP_WARN_LV1 __BITS(7,4) 109 #define AXP_BATT_CAP_WARN_LV2 __BITS(3,0) 110 111 #define AXP_ADDR_EXT_REG 0xff /* AXP806 */ 112 #define AXP_ADDR_EXT_MASTER 0 113 #define AXP_ADDR_EXT_SLAVE __BIT(4) 114 115 struct axppmic_ctrl { 116 device_t c_dev; 117 118 const char * c_name; 119 u_int c_min; 120 u_int c_max; 121 u_int c_step1; 122 u_int c_step1cnt; 123 u_int c_step2; 124 u_int c_step2cnt; 125 u_int c_step2start; 126 127 uint8_t c_enable_reg; 128 uint8_t c_enable_mask; 129 uint8_t c_enable_val; 130 uint8_t c_disable_val; 131 132 uint8_t c_voltage_reg; 133 uint8_t c_voltage_mask; 134 }; 135 136 #define AXP_CTRL(name, min, max, step, ereg, emask, vreg, vmask) \ 137 { .c_name = (name), .c_min = (min), .c_max = (max), \ 138 .c_step1 = (step), .c_step1cnt = (((max) - (min)) / (step)) + 1, \ 139 .c_step2 = 0, .c_step2cnt = 0, \ 140 .c_enable_reg = (ereg), .c_enable_mask = (emask), \ 141 .c_enable_val = (emask), .c_disable_val = 0, \ 142 .c_voltage_reg = (vreg), .c_voltage_mask = (vmask) } 143 144 #define AXP_CTRL2(name, min, max, step1, step1cnt, step2, step2cnt, ereg, emask, vreg, vmask) \ 145 { .c_name = (name), .c_min = (min), .c_max = (max), \ 146 .c_step1 = (step1), .c_step1cnt = (step1cnt), \ 147 .c_step2 = (step2), .c_step2cnt = (step2cnt), \ 148 .c_enable_reg = (ereg), .c_enable_mask = (emask), \ 149 .c_enable_val = (emask), .c_disable_val = 0, \ 150 .c_voltage_reg = (vreg), .c_voltage_mask = (vmask) } 151 152 #define AXP_CTRL2_RANGE(name, min, max, step1, step1cnt, step2start, step2, step2cnt, ereg, emask, vreg, vmask) \ 153 { .c_name = (name), .c_min = (min), .c_max = (max), \ 154 .c_step1 = (step1), .c_step1cnt = (step1cnt), \ 155 .c_step2start = (step2start), \ 156 .c_step2 = (step2), .c_step2cnt = (step2cnt), \ 157 .c_enable_reg = (ereg), .c_enable_mask = (emask), \ 158 .c_enable_val = (emask), .c_disable_val = 0, \ 159 .c_voltage_reg = (vreg), .c_voltage_mask = (vmask) } 160 161 #define AXP_CTRL_IO(name, min, max, step, ereg, emask, eval, dval, vreg, vmask) \ 162 { .c_name = (name), .c_min = (min), .c_max = (max), \ 163 .c_step1 = (step), .c_step1cnt = (((max) - (min)) / (step)) + 1, \ 164 .c_step2 = 0, .c_step2cnt = 0, \ 165 .c_enable_reg = (ereg), .c_enable_mask = (emask), \ 166 .c_enable_val = (eval), .c_disable_val = (dval), \ 167 .c_voltage_reg = (vreg), .c_voltage_mask = (vmask) } 168 169 #define AXP_CTRL_SW(name, ereg, emask) \ 170 { .c_name = (name), \ 171 .c_enable_reg = (ereg), .c_enable_mask = (emask), \ 172 .c_enable_val = (emask), .c_disable_val = 0 } 173 174 static const struct axppmic_ctrl axp803_ctrls[] = { 175 AXP_CTRL("dldo1", 700, 3300, 100, 176 0x12, __BIT(3), 0x15, __BITS(4,0)), 177 AXP_CTRL2("dldo2", 700, 4200, 100, 28, 200, 4, 178 0x12, __BIT(4), 0x16, __BITS(4,0)), 179 AXP_CTRL("dldo3", 700, 3300, 100, 180 0x12, __BIT(5), 0x17, __BITS(4,0)), 181 AXP_CTRL("dldo4", 700, 3300, 100, 182 0x12, __BIT(6), 0x18, __BITS(4,0)), 183 AXP_CTRL("eldo1", 700, 1900, 50, 184 0x12, __BIT(0), 0x19, __BITS(4,0)), 185 AXP_CTRL("eldo2", 700, 1900, 50, 186 0x12, __BIT(1), 0x1a, __BITS(4,0)), 187 AXP_CTRL("eldo3", 700, 1900, 50, 188 0x12, __BIT(2), 0x1b, __BITS(4,0)), 189 AXP_CTRL("fldo1", 700, 1450, 50, 190 0x13, __BIT(2), 0x1c, __BITS(3,0)), 191 AXP_CTRL("fldo2", 700, 1450, 50, 192 0x13, __BIT(3), 0x1d, __BITS(3,0)), 193 AXP_CTRL("dcdc1", 1600, 3400, 100, 194 0x10, __BIT(0), 0x20, __BITS(4,0)), 195 AXP_CTRL2("dcdc2", 500, 1300, 10, 70, 20, 5, 196 0x10, __BIT(1), 0x21, __BITS(6,0)), 197 AXP_CTRL2("dcdc3", 500, 1300, 10, 70, 20, 5, 198 0x10, __BIT(2), 0x22, __BITS(6,0)), 199 AXP_CTRL2("dcdc4", 500, 1300, 10, 70, 20, 5, 200 0x10, __BIT(3), 0x23, __BITS(6,0)), 201 AXP_CTRL2("dcdc5", 800, 1840, 10, 33, 20, 36, 202 0x10, __BIT(4), 0x24, __BITS(6,0)), 203 AXP_CTRL2("dcdc6", 600, 1520, 10, 51, 20, 21, 204 0x10, __BIT(5), 0x25, __BITS(6,0)), 205 AXP_CTRL("aldo1", 700, 3300, 100, 206 0x13, __BIT(5), 0x28, __BITS(4,0)), 207 AXP_CTRL("aldo2", 700, 3300, 100, 208 0x13, __BIT(6), 0x29, __BITS(4,0)), 209 AXP_CTRL("aldo3", 700, 3300, 100, 210 0x13, __BIT(7), 0x2a, __BITS(4,0)), 211 }; 212 213 static const struct axppmic_ctrl axp805_ctrls[] = { 214 AXP_CTRL2("dcdca", 600, 1520, 10, 51, 20, 21, 215 0x10, __BIT(0), 0x12, __BITS(6,0)), 216 AXP_CTRL("dcdcb", 1000, 2550, 50, 217 0x10, __BIT(1), 0x13, __BITS(4,0)), 218 AXP_CTRL2("dcdcc", 600, 1520, 10, 51, 20, 21, 219 0x10, __BIT(2), 0x14, __BITS(6,0)), 220 AXP_CTRL2("dcdcd", 600, 3300, 20, 46, 100, 18, 221 0x10, __BIT(3), 0x15, __BITS(5,0)), 222 AXP_CTRL("dcdce", 1100, 3400, 100, 223 0x10, __BIT(4), 0x16, __BITS(4,0)), 224 AXP_CTRL("aldo1", 700, 3300, 100, 225 0x10, __BIT(5), 0x17, __BITS(4,0)), 226 AXP_CTRL("aldo2", 700, 3400, 100, 227 0x10, __BIT(6), 0x18, __BITS(4,0)), 228 AXP_CTRL("aldo3", 700, 3300, 100, 229 0x10, __BIT(7), 0x19, __BITS(4,0)), 230 AXP_CTRL("bldo1", 700, 1900, 100, 231 0x11, __BIT(0), 0x20, __BITS(3,0)), 232 AXP_CTRL("bldo2", 700, 1900, 100, 233 0x11, __BIT(1), 0x21, __BITS(3,0)), 234 AXP_CTRL("bldo3", 700, 1900, 100, 235 0x11, __BIT(2), 0x22, __BITS(3,0)), 236 AXP_CTRL("bldo4", 700, 1900, 100, 237 0x11, __BIT(3), 0x23, __BITS(3,0)), 238 AXP_CTRL("cldo1", 700, 3300, 100, 239 0x11, __BIT(4), 0x24, __BITS(4,0)), 240 AXP_CTRL2("cldo2", 700, 4200, 100, 28, 200, 4, 241 0x11, __BIT(5), 0x25, __BITS(4,0)), 242 AXP_CTRL("cldo3", 700, 3300, 100, 243 0x11, __BIT(6), 0x26, __BITS(4,0)), 244 }; 245 246 static const struct axppmic_ctrl axp809_ctrls[] = { 247 AXP_CTRL("dc5ldo", 700, 1400, 100, 248 0x10, __BIT(0), 0x1c, __BITS(2,0)), 249 AXP_CTRL("dcdc1", 1600, 3400, 100, 250 0x10, __BIT(1), 0x21, __BITS(4,0)), 251 AXP_CTRL("dcdc2", 600, 1540, 20, 252 0x10, __BIT(2), 0x22, __BITS(5,0)), 253 AXP_CTRL("dcdc3", 600, 1860, 20, 254 0x10, __BIT(3), 0x23, __BITS(5,0)), 255 AXP_CTRL2_RANGE("dcdc4", 600, 2600, 20, 47, 1800, 100, 9, 256 0x10, __BIT(4), 0x24, __BITS(5,0)), 257 AXP_CTRL("dcdc5", 1000, 2550, 50, 258 0x10, __BIT(5), 0x25, __BITS(4,0)), 259 AXP_CTRL("aldo1", 700, 3300, 100, 260 0x10, __BIT(6), 0x28, __BITS(4,0)), 261 AXP_CTRL("aldo2", 700, 3300, 100, 262 0x10, __BIT(7), 0x29, __BITS(4,0)), 263 AXP_CTRL("eldo1", 700, 3300, 100, 264 0x12, __BIT(0), 0x19, __BITS(4,0)), 265 AXP_CTRL("eldo2", 700, 3300, 100, 266 0x12, __BIT(1), 0x1a, __BITS(4,0)), 267 AXP_CTRL("eldo3", 700, 3300, 100, 268 0x12, __BIT(2), 0x1b, __BITS(4,0)), 269 AXP_CTRL2_RANGE("dldo1", 700, 4000, 100, 26, 3400, 200, 4, 270 0x12, __BIT(3), 0x15, __BITS(4,0)), 271 AXP_CTRL("dldo2", 700, 3300, 100, 272 0x12, __BIT(4), 0x16, __BITS(4,0)), 273 AXP_CTRL("aldo3", 700, 3300, 100, 274 0x12, __BIT(5), 0x2a, __BITS(4,0)), 275 AXP_CTRL_SW("sw", 276 0x12, __BIT(6)), 277 /* dc1sw is another switch for dcdc1 */ 278 AXP_CTRL("dc1sw", 1600, 3400, 100, 279 0x12, __BIT(7), 0x21, __BITS(4,0)), 280 AXP_CTRL_IO("ldo_io0", 700, 3300, 100, 281 0x90, __BITS(3,0), 0x3, 0x7, 0x91, __BITS(4,0)), 282 AXP_CTRL_IO("ldo_io1", 700, 3300, 100, 283 0x92, __BITS(3,0), 0x3, 0x7, 0x93, __BITS(4,0)), 284 }; 285 286 static const struct axppmic_ctrl axp813_ctrls[] = { 287 AXP_CTRL("dldo1", 700, 3300, 100, 288 0x12, __BIT(3), 0x15, __BITS(4,0)), 289 AXP_CTRL2("dldo2", 700, 4200, 100, 28, 200, 4, 290 0x12, __BIT(4), 0x16, __BITS(4,0)), 291 AXP_CTRL("dldo3", 700, 3300, 100, 292 0x12, __BIT(5), 0x17, __BITS(4,0)), 293 AXP_CTRL("dldo4", 700, 3300, 100, 294 0x12, __BIT(6), 0x18, __BITS(4,0)), 295 AXP_CTRL("eldo1", 700, 1900, 50, 296 0x12, __BIT(0), 0x19, __BITS(4,0)), 297 AXP_CTRL("eldo2", 700, 1900, 50, 298 0x12, __BIT(1), 0x1a, __BITS(4,0)), 299 AXP_CTRL("eldo3", 700, 1900, 50, 300 0x12, __BIT(2), 0x1b, __BITS(4,0)), 301 AXP_CTRL("fldo1", 700, 1450, 50, 302 0x13, __BIT(2), 0x1c, __BITS(3,0)), 303 AXP_CTRL("fldo2", 700, 1450, 50, 304 0x13, __BIT(3), 0x1d, __BITS(3,0)), 305 AXP_CTRL("dcdc1", 1600, 3400, 100, 306 0x10, __BIT(0), 0x20, __BITS(4,0)), 307 AXP_CTRL2("dcdc2", 500, 1300, 10, 70, 20, 5, 308 0x10, __BIT(1), 0x21, __BITS(6,0)), 309 AXP_CTRL2("dcdc3", 500, 1300, 10, 70, 20, 5, 310 0x10, __BIT(2), 0x22, __BITS(6,0)), 311 AXP_CTRL2("dcdc4", 500, 1300, 10, 70, 20, 5, 312 0x10, __BIT(3), 0x23, __BITS(6,0)), 313 AXP_CTRL2("dcdc5", 800, 1840, 10, 33, 20, 36, 314 0x10, __BIT(4), 0x24, __BITS(6,0)), 315 AXP_CTRL2("dcdc6", 600, 1520, 10, 51, 20, 21, 316 0x10, __BIT(5), 0x25, __BITS(6,0)), 317 AXP_CTRL2("dcdc7", 600, 1520, 10, 51, 20, 21, 318 0x10, __BIT(6), 0x26, __BITS(6,0)), 319 AXP_CTRL("aldo1", 700, 3300, 100, 320 0x13, __BIT(5), 0x28, __BITS(4,0)), 321 AXP_CTRL("aldo2", 700, 3300, 100, 322 0x13, __BIT(6), 0x29, __BITS(4,0)), 323 AXP_CTRL("aldo3", 700, 3300, 100, 324 0x13, __BIT(7), 0x2a, __BITS(4,0)), 325 }; 326 327 static const struct axppmic_ctrl axp15060_ctrls[] = { 328 AXP_CTRL( "dcdc1", 1500, 3400, 100, 329 0x13, __BITS(4, 0), 330 0x10, __BIT(0)), 331 // DCDC2: 0.5~1.2V, 10mV/step, 1.22~1.54V, 20mV/step, IMAX=3.5A, DVM 332 AXP_CTRL2_RANGE("dcdc2", 333 500, 1540, 70, 10, 1220, 16 , 20, 334 0x14, __BITS(6, 0), 335 0x10, __BIT(1)), 336 // DCDC3: 0.5~1.2V, 10mV/step, 1.22~1.54V, 20mV/step, IMAX=3.5A, DVM 337 AXP_CTRL2_RANGE("dcdc3", 338 500, 1540, 70, 10, 1220, 16 , 20, 339 0x15, __BITS(6, 0), 340 0x10, __BIT(2)), 341 // DCDC4: 0.5~1.2V, 10mV/step, 1.22~1.54V, 20mV/step, IMAX=3.5A, DVM 342 AXP_CTRL2_RANGE("dcdc4", 343 500, 1540, 70, 10, 1220, 16 , 20, 344 0x16, __BITS(6, 0), 345 0x10, __BIT(3)), 346 // DCDC5: 0.8~1.12V, 10mV/step, 1.14~1.84V, 20mV/step, IMAX=2.5A, DVM 347 AXP_CTRL2_RANGE("dcdc5", 348 800, 1840, 349 32, 10, 350 1140, 35, 20, 351 0x17, __BITS(6, 0), 352 0x10, __BIT(4)), 353 AXP_CTRL("dcdc6", 500, 3400, 100, 354 0x18, __BITS(4, 0), 355 0x10, __BIT(5)), 356 AXP_CTRL("aldo1", 700, 3300, 100, 357 0x19, __BITS(4, 0), 358 0x11, __BIT(0)), 359 AXP_CTRL("aldo2", 700, 3300, 100, 360 0x20, __BITS(4, 0), 361 0x11, __BIT(1)), 362 AXP_CTRL("aldo3", 700, 3300, 100, 363 0x21, __BITS(4, 0), 364 0x11, __BIT(2)), 365 AXP_CTRL("aldo4", 700, 3300, 100, 366 0x22, __BITS(4, 0), 367 0x11, __BIT(3)), 368 AXP_CTRL("aldo5", 700, 3300, 100, 369 0x23, __BITS(4, 0), 370 0x11, __BIT(4)), 371 AXP_CTRL("bldo1", 700, 3300, 100, 372 0x24, __BITS(4, 0), 373 0x11, __BIT(5)), 374 AXP_CTRL("bldo2", 700, 3300, 100, 375 0x25, __BITS(4, 0), 376 0x11, __BIT(6)), 377 AXP_CTRL("bldo3", 700, 3300, 100, 378 0x26, __BITS(4, 0), 379 0x11, __BIT(7)), 380 AXP_CTRL("bldo4", 700, 3300, 100, 381 0x27, __BITS(4, 0), 382 0x12, __BIT(0)), 383 AXP_CTRL("bldo5", 700, 3300, 100, 384 0x28, __BITS(4, 0), 385 0x12, __BIT(1)), 386 AXP_CTRL("cldo1", 700, 3300, 100, 387 0x29, __BITS(4, 0), 388 0x12, __BIT(2)), 389 AXP_CTRL("cldo2", 700, 3300, 100, 390 0x2a, __BITS(4, 0), 391 0x12, __BIT(3)), 392 AXP_CTRL("cldo3", 700, 3300, 100, 393 0x2b, __BITS(4, 0), 394 0x12, __BIT(4)), 395 AXP_CTRL("cldo4", 700, 4200, 100, 396 0x2d, __BITS(5, 0), 397 0x12, __BIT(5)), 398 AXP_CTRL("cpusldo", 700, 1400, 50, 399 0x2e, __BITS(3, 0), 400 0x12, __BIT(6)), 401 }; 402 403 404 struct axppmic_irq { 405 u_int reg; 406 uint8_t mask; 407 }; 408 409 #define AXPPMIC_IRQ(_reg, _mask) \ 410 { .reg = (_reg), .mask = (_mask) } 411 412 struct axppmic_config { 413 const char *name; 414 const char *gpio_compat; 415 u_int gpio_npins; 416 const struct axppmic_ctrl *controls; 417 u_int ncontrols; 418 u_int irq_regs; 419 bool has_battery; 420 bool has_fuel_gauge; 421 bool has_mode_set; 422 struct axppmic_irq poklirq; 423 struct axppmic_irq acinirq; 424 struct axppmic_irq vbusirq; 425 struct axppmic_irq battirq; 426 struct axppmic_irq chargeirq; 427 struct axppmic_irq chargestirq; 428 u_int batsense_step; /* uV */ 429 u_int charge_step; /* uA */ 430 u_int discharge_step; /* uA */ 431 u_int maxcap_step; /* uAh */ 432 u_int coulomb_step; /* uAh */ 433 }; 434 435 enum axppmic_sensor { 436 AXP_SENSOR_ACIN_PRESENT, 437 AXP_SENSOR_VBUS_PRESENT, 438 AXP_SENSOR_BATT_PRESENT, 439 AXP_SENSOR_BATT_CHARGING, 440 AXP_SENSOR_BATT_CHARGE_STATE, 441 AXP_SENSOR_BATT_VOLTAGE, 442 AXP_SENSOR_BATT_CHARGE_CURRENT, 443 AXP_SENSOR_BATT_DISCHARGE_CURRENT, 444 AXP_SENSOR_BATT_CAPACITY_PERCENT, 445 AXP_SENSOR_BATT_MAXIMUM_CAPACITY, 446 AXP_SENSOR_BATT_CURRENT_CAPACITY, 447 AXP_NSENSORS 448 }; 449 450 struct axppmic_softc { 451 device_t sc_dev; 452 i2c_tag_t sc_i2c; 453 i2c_addr_t sc_addr; 454 int sc_phandle; 455 456 void *sc_ih; 457 struct workqueue *sc_wq; 458 459 kmutex_t sc_intr_lock; 460 struct work sc_work; 461 bool sc_work_scheduled; 462 463 const struct axppmic_config *sc_conf; 464 465 struct sysmon_pswitch sc_smpsw; 466 467 struct sysmon_envsys *sc_sme; 468 469 envsys_data_t sc_sensor[AXP_NSENSORS]; 470 471 u_int sc_warn_thres; 472 u_int sc_shut_thres; 473 }; 474 475 struct axppmic_gpio_pin { 476 struct axppmic_softc *pin_sc; 477 u_int pin_nr; 478 int pin_flags; 479 bool pin_actlo; 480 }; 481 482 struct axpreg_softc { 483 device_t sc_dev; 484 i2c_tag_t sc_i2c; 485 i2c_addr_t sc_addr; 486 const struct axppmic_ctrl *sc_ctrl; 487 }; 488 489 struct axpreg_attach_args { 490 const struct axppmic_ctrl *reg_ctrl; 491 int reg_phandle; 492 i2c_tag_t reg_i2c; 493 i2c_addr_t reg_addr; 494 }; 495 496 static const struct axppmic_config axp803_config = { 497 .name = "AXP803", 498 .gpio_compat = "x-powers,axp803-gpio", 499 .gpio_npins = 2, 500 .controls = axp803_ctrls, 501 .ncontrols = __arraycount(axp803_ctrls), 502 .irq_regs = 6, 503 .has_battery = true, 504 .has_fuel_gauge = true, 505 .batsense_step = 1100, 506 .charge_step = 1000, 507 .discharge_step = 1000, 508 .maxcap_step = 1456, 509 .coulomb_step = 1456, 510 .poklirq = AXPPMIC_IRQ(5, __BIT(3)), 511 .acinirq = AXPPMIC_IRQ(1, __BITS(6,5)), 512 .vbusirq = AXPPMIC_IRQ(1, __BITS(3,2)), 513 .battirq = AXPPMIC_IRQ(2, __BITS(7,6)), 514 .chargeirq = AXPPMIC_IRQ(2, __BITS(3,2)), 515 .chargestirq = AXPPMIC_IRQ(4, __BITS(1,0)), 516 }; 517 518 static const struct axppmic_config axp805_config = { 519 .name = "AXP805", 520 .controls = axp805_ctrls, 521 .ncontrols = __arraycount(axp805_ctrls), 522 .irq_regs = 2, 523 .poklirq = AXPPMIC_IRQ(2, __BIT(0)), 524 }; 525 526 static const struct axppmic_config axp806_config = { 527 .name = "AXP806", 528 .controls = axp805_ctrls, 529 .ncontrols = __arraycount(axp805_ctrls), 530 #if notyet 531 .irq_regs = 2, 532 .poklirq = AXPPMIC_IRQ(2, __BIT(0)), 533 #endif 534 .has_mode_set = true, 535 }; 536 537 static const struct axppmic_config axp809_config = { 538 .name = "AXP809", 539 .controls = axp809_ctrls, 540 .ncontrols = __arraycount(axp809_ctrls), 541 }; 542 543 static const struct axppmic_config axp813_config = { 544 .name = "AXP813", 545 .gpio_compat = "x-powers,axp813-gpio", 546 .gpio_npins = 2, 547 .controls = axp813_ctrls, 548 .ncontrols = __arraycount(axp813_ctrls), 549 .irq_regs = 6, 550 .has_battery = true, 551 .has_fuel_gauge = true, 552 .batsense_step = 1100, 553 .charge_step = 1000, 554 .discharge_step = 1000, 555 .maxcap_step = 1456, 556 .coulomb_step = 1456, 557 .poklirq = AXPPMIC_IRQ(5, __BIT(3)), 558 .acinirq = AXPPMIC_IRQ(1, __BITS(6,5)), 559 .vbusirq = AXPPMIC_IRQ(1, __BITS(3,2)), 560 .battirq = AXPPMIC_IRQ(2, __BITS(7,6)), 561 .chargeirq = AXPPMIC_IRQ(2, __BITS(3,2)), 562 .chargestirq = AXPPMIC_IRQ(4, __BITS(1,0)), 563 }; 564 565 static const struct axppmic_config axp15060_config = { 566 .name = "AXP15060", 567 .controls = axp15060_ctrls, 568 .ncontrols = __arraycount(axp15060_ctrls), 569 }; 570 571 static const struct device_compatible_entry compat_data[] = { 572 { .compat = "x-powers,axp803", .data = &axp803_config }, 573 { .compat = "x-powers,axp805", .data = &axp805_config }, 574 { .compat = "x-powers,axp806", .data = &axp806_config }, 575 { .compat = "x-powers,axp809", .data = &axp809_config }, 576 { .compat = "x-powers,axp813", .data = &axp813_config }, 577 { .compat = "x-powers,axp15060", .data = &axp15060_config }, 578 DEVICE_COMPAT_EOL 579 }; 580 581 static int 582 axppmic_read(i2c_tag_t tag, i2c_addr_t addr, uint8_t reg, uint8_t *val, int flags) 583 { 584 return iic_smbus_read_byte(tag, addr, reg, val, flags); 585 } 586 587 static int 588 axppmic_write(i2c_tag_t tag, i2c_addr_t addr, uint8_t reg, uint8_t val, int flags) 589 { 590 return iic_smbus_write_byte(tag, addr, reg, val, flags); 591 } 592 593 static int 594 axppmic_set_voltage(i2c_tag_t tag, i2c_addr_t addr, const struct axppmic_ctrl *c, u_int min, u_int max) 595 { 596 u_int vol, reg_val; 597 int nstep, error; 598 uint8_t val; 599 600 if (!c->c_voltage_mask) 601 return EINVAL; 602 603 if (min < c->c_min || min > c->c_max) 604 return EINVAL; 605 606 reg_val = 0; 607 nstep = 1; 608 vol = c->c_min; 609 610 for (nstep = 0; nstep < c->c_step1cnt && vol < min; nstep++) { 611 ++reg_val; 612 vol += c->c_step1; 613 } 614 615 if (c->c_step2start) 616 vol = c->c_step2start; 617 618 for (nstep = 0; nstep < c->c_step2cnt && vol < min; nstep++) { 619 ++reg_val; 620 vol += c->c_step2; 621 } 622 623 if (vol > max) 624 return EINVAL; 625 626 iic_acquire_bus(tag, 0); 627 if ((error = axppmic_read(tag, addr, c->c_voltage_reg, &val, 0)) == 0) { 628 val &= ~c->c_voltage_mask; 629 val |= __SHIFTIN(reg_val, c->c_voltage_mask); 630 error = axppmic_write(tag, addr, c->c_voltage_reg, val, 0); 631 } 632 iic_release_bus(tag, 0); 633 634 return error; 635 } 636 637 static int 638 axppmic_get_voltage(i2c_tag_t tag, i2c_addr_t addr, const struct axppmic_ctrl *c, u_int *pvol) 639 { 640 int reg_val, error; 641 uint8_t val; 642 643 if (!c->c_voltage_mask) 644 return EINVAL; 645 646 iic_acquire_bus(tag, 0); 647 error = axppmic_read(tag, addr, c->c_voltage_reg, &val, 0); 648 iic_release_bus(tag, 0); 649 if (error) 650 return error; 651 652 reg_val = __SHIFTOUT(val, c->c_voltage_mask); 653 if (reg_val < c->c_step1cnt) { 654 *pvol = c->c_min + reg_val * c->c_step1; 655 } else if (c->c_step2start) { 656 *pvol = c->c_step2start + 657 ((reg_val - c->c_step1cnt) * c->c_step2); 658 } else { 659 *pvol = c->c_min + (c->c_step1cnt * c->c_step1) + 660 ((reg_val - c->c_step1cnt) * c->c_step2); 661 } 662 663 return 0; 664 } 665 666 static void 667 axppmic_power_poweroff(device_t dev) 668 { 669 struct axppmic_softc *sc = device_private(dev); 670 int error; 671 672 delay(1000000); 673 674 error = iic_acquire_bus(sc->sc_i2c, 0); 675 if (error == 0) { 676 error = axppmic_write(sc->sc_i2c, sc->sc_addr, 677 AXP_POWER_DISABLE_REG, AXP_POWER_DISABLE_CTRL, 0); 678 iic_release_bus(sc->sc_i2c, 0); 679 } 680 if (error) { 681 device_printf(dev, "WARNING: unable to power off, error %d\n", 682 error); 683 } 684 } 685 686 static struct fdtbus_power_controller_func axppmic_power_funcs = { 687 .poweroff = axppmic_power_poweroff, 688 }; 689 690 static int 691 axppmic_gpio_ctl(struct axppmic_softc *sc, uint8_t pin, uint8_t func) 692 { 693 uint8_t val; 694 int error; 695 696 KASSERT(pin < sc->sc_conf->gpio_npins); 697 KASSERT((func & ~AXP_GPIO_CTRL_FUNC_MASK) == 0); 698 699 iic_acquire_bus(sc->sc_i2c, 0); 700 error = axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_GPIO_CTRL_REG(pin), 701 &val, 0); 702 if (error == 0) { 703 val &= ~AXP_GPIO_CTRL_FUNC_MASK; 704 val |= func; 705 error = axppmic_write(sc->sc_i2c, sc->sc_addr, 706 AXP_GPIO_CTRL_REG(pin), val, 0); 707 } 708 iic_release_bus(sc->sc_i2c, 0); 709 710 return error; 711 } 712 713 static void * 714 axppmic_gpio_acquire(device_t dev, const void *data, size_t len, int flags) 715 { 716 struct axppmic_softc *sc = device_private(dev); 717 struct axppmic_gpio_pin *gpin; 718 const u_int *gpio = data; 719 int error; 720 721 if (len != 12) { 722 return NULL; 723 } 724 725 const uint8_t pin = be32toh(gpio[1]) & 0xff; 726 const bool actlo = be32toh(gpio[2]) & 1; 727 728 if (pin >= sc->sc_conf->gpio_npins) { 729 return NULL; 730 } 731 732 if ((flags & GPIO_PIN_INPUT) != 0) { 733 error = axppmic_gpio_ctl(sc, pin, AXP_GPIO_CTRL_FUNC_INPUT); 734 if (error != 0) { 735 return NULL; 736 } 737 } 738 739 gpin = kmem_zalloc(sizeof(*gpin), KM_SLEEP); 740 gpin->pin_sc = sc; 741 gpin->pin_nr = pin; 742 gpin->pin_flags = flags; 743 gpin->pin_actlo = actlo; 744 745 return gpin; 746 } 747 748 static void 749 axppmic_gpio_release(device_t dev, void *priv) 750 { 751 struct axppmic_softc *sc = device_private(dev); 752 struct axppmic_gpio_pin *gpin = priv; 753 754 axppmic_gpio_ctl(sc, gpin->pin_nr, AXP_GPIO_CTRL_FUNC_INPUT); 755 756 kmem_free(gpin, sizeof(*gpin)); 757 } 758 759 static int 760 axppmic_gpio_read(device_t dev, void *priv, bool raw) 761 { 762 struct axppmic_softc *sc = device_private(dev); 763 struct axppmic_gpio_pin *gpin = priv; 764 uint8_t data; 765 int error, val; 766 767 KASSERT(sc == gpin->pin_sc); 768 769 const uint8_t data_mask = __BIT(gpin->pin_nr); 770 771 iic_acquire_bus(sc->sc_i2c, 0); 772 error = axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_GPIO_SIGNAL_REG, 773 &data, 0); 774 iic_release_bus(sc->sc_i2c, 0); 775 776 if (error != 0) { 777 device_printf(dev, "WARNING: failed to read pin %d: %d\n", 778 gpin->pin_nr, error); 779 val = 0; 780 } else { 781 val = __SHIFTOUT(data, data_mask); 782 } 783 if (!raw && gpin->pin_actlo) { 784 val = !val; 785 } 786 787 return val; 788 } 789 790 static void 791 axppmic_gpio_write(device_t dev, void *priv, int val, bool raw) 792 { 793 struct axppmic_softc *sc = device_private(dev); 794 struct axppmic_gpio_pin *gpin = priv; 795 int error; 796 797 if (!raw && gpin->pin_actlo) { 798 val = !val; 799 } 800 801 error = axppmic_gpio_ctl(sc, gpin->pin_nr, 802 val == 0 ? AXP_GPIO_CTRL_FUNC_LOW : AXP_GPIO_CTRL_FUNC_HIGH); 803 if (error != 0) { 804 device_printf(dev, "WARNING: failed to write pin %d: %d\n", 805 gpin->pin_nr, error); 806 } 807 } 808 809 static struct fdtbus_gpio_controller_func axppmic_gpio_funcs = { 810 .acquire = axppmic_gpio_acquire, 811 .release = axppmic_gpio_release, 812 .read = axppmic_gpio_read, 813 .write = axppmic_gpio_write, 814 }; 815 816 static void 817 axppmic_task_shut(void *priv) 818 { 819 struct axppmic_softc *sc = priv; 820 821 sysmon_pswitch_event(&sc->sc_smpsw, PSWITCH_EVENT_PRESSED); 822 } 823 824 static void 825 axppmic_sensor_update(struct sysmon_envsys *sme, envsys_data_t *e) 826 { 827 struct axppmic_softc *sc = sme->sme_cookie; 828 const struct axppmic_config *c = sc->sc_conf; 829 uint8_t val, lo, hi; 830 831 e->state = ENVSYS_SINVALID; 832 833 const bool battery_present = 834 sc->sc_sensor[AXP_SENSOR_BATT_PRESENT].state == ENVSYS_SVALID && 835 sc->sc_sensor[AXP_SENSOR_BATT_PRESENT].value_cur == 1; 836 837 switch (e->private) { 838 case AXP_SENSOR_ACIN_PRESENT: 839 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_SOURCE_REG, &val, 0) == 0) { 840 e->state = ENVSYS_SVALID; 841 e->value_cur = !!(val & AXP_POWER_SOURCE_ACIN_PRESENT); 842 } 843 break; 844 case AXP_SENSOR_VBUS_PRESENT: 845 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_SOURCE_REG, &val, 0) == 0) { 846 e->state = ENVSYS_SVALID; 847 e->value_cur = !!(val & AXP_POWER_SOURCE_VBUS_PRESENT); 848 } 849 break; 850 case AXP_SENSOR_BATT_PRESENT: 851 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_MODE_REG, &val, 0) == 0) { 852 if (val & AXP_POWER_MODE_BATT_VALID) { 853 e->state = ENVSYS_SVALID; 854 e->value_cur = !!(val & AXP_POWER_MODE_BATT_PRESENT); 855 } 856 } 857 break; 858 case AXP_SENSOR_BATT_CHARGING: 859 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_MODE_REG, &val, 0) == 0) { 860 e->state = ENVSYS_SVALID; 861 e->value_cur = !!(val & AXP_POWER_MODE_BATT_CHARGING); 862 } 863 break; 864 case AXP_SENSOR_BATT_CHARGE_STATE: 865 if (battery_present && 866 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_CAP_REG, &val, 0) == 0 && 867 (val & AXP_BATT_CAP_VALID) != 0) { 868 const u_int batt_val = __SHIFTOUT(val, AXP_BATT_CAP_PERCENT); 869 if (batt_val <= sc->sc_shut_thres) { 870 e->state = ENVSYS_SCRITICAL; 871 e->value_cur = ENVSYS_BATTERY_CAPACITY_CRITICAL; 872 } else if (batt_val <= sc->sc_warn_thres) { 873 e->state = ENVSYS_SWARNUNDER; 874 e->value_cur = ENVSYS_BATTERY_CAPACITY_WARNING; 875 } else { 876 e->state = ENVSYS_SVALID; 877 e->value_cur = ENVSYS_BATTERY_CAPACITY_NORMAL; 878 } 879 } 880 break; 881 case AXP_SENSOR_BATT_CAPACITY_PERCENT: 882 if (battery_present && 883 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_CAP_REG, &val, 0) == 0 && 884 (val & AXP_BATT_CAP_VALID) != 0) { 885 e->state = ENVSYS_SVALID; 886 e->value_cur = __SHIFTOUT(val, AXP_BATT_CAP_PERCENT); 887 } 888 break; 889 case AXP_SENSOR_BATT_VOLTAGE: 890 if (battery_present && 891 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATSENSE_HI_REG, &hi, 0) == 0 && 892 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATSENSE_LO_REG, &lo, 0) == 0) { 893 e->state = ENVSYS_SVALID; 894 e->value_cur = AXP_ADC_RAW(hi, lo) * c->batsense_step; 895 } 896 break; 897 case AXP_SENSOR_BATT_CHARGE_CURRENT: 898 if (battery_present && 899 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_SOURCE_REG, &val, 0) == 0 && 900 (val & AXP_POWER_SOURCE_CHARGE_DIRECTION) != 0 && 901 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATTCHG_HI_REG, &hi, 0) == 0 && 902 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATTCHG_LO_REG, &lo, 0) == 0) { 903 e->state = ENVSYS_SVALID; 904 e->value_cur = AXP_ADC_RAW(hi, lo) * c->charge_step; 905 } 906 break; 907 case AXP_SENSOR_BATT_DISCHARGE_CURRENT: 908 if (battery_present && 909 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_SOURCE_REG, &val, 0) == 0 && 910 (val & AXP_POWER_SOURCE_CHARGE_DIRECTION) == 0 && 911 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATTDISCHG_HI_REG, &hi, 0) == 0 && 912 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATTDISCHG_LO_REG, &lo, 0) == 0) { 913 e->state = ENVSYS_SVALID; 914 e->value_cur = AXP_ADC_RAW(hi, lo) * c->discharge_step; 915 } 916 break; 917 case AXP_SENSOR_BATT_MAXIMUM_CAPACITY: 918 if (battery_present && 919 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_MAX_CAP_HI_REG, &hi, 0) == 0 && 920 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_MAX_CAP_LO_REG, &lo, 0) == 0) { 921 e->state = (hi & AXP_BATT_MAX_CAP_VALID) ? ENVSYS_SVALID : ENVSYS_SINVALID; 922 e->value_cur = AXP_COULOMB_RAW(hi, lo) * c->maxcap_step; 923 } 924 break; 925 case AXP_SENSOR_BATT_CURRENT_CAPACITY: 926 if (battery_present && 927 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_COULOMB_HI_REG, &hi, 0) == 0 && 928 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_COULOMB_LO_REG, &lo, 0) == 0) { 929 e->state = (hi & AXP_BATT_COULOMB_VALID) ? ENVSYS_SVALID : ENVSYS_SINVALID; 930 e->value_cur = AXP_COULOMB_RAW(hi, lo) * c->coulomb_step; 931 } 932 break; 933 } 934 } 935 936 static void 937 axppmic_sensor_refresh(struct sysmon_envsys *sme, envsys_data_t *e) 938 { 939 struct axppmic_softc *sc = sme->sme_cookie; 940 941 switch (e->private) { 942 case AXP_SENSOR_BATT_CAPACITY_PERCENT: 943 case AXP_SENSOR_BATT_VOLTAGE: 944 case AXP_SENSOR_BATT_CHARGE_CURRENT: 945 case AXP_SENSOR_BATT_DISCHARGE_CURRENT: 946 /* Always update battery capacity and ADCs */ 947 iic_acquire_bus(sc->sc_i2c, 0); 948 axppmic_sensor_update(sme, e); 949 iic_release_bus(sc->sc_i2c, 0); 950 break; 951 default: 952 /* Refresh if the sensor is not in valid state */ 953 if (e->state != ENVSYS_SVALID) { 954 iic_acquire_bus(sc->sc_i2c, 0); 955 axppmic_sensor_update(sme, e); 956 iic_release_bus(sc->sc_i2c, 0); 957 } 958 break; 959 } 960 } 961 962 static int 963 axppmic_intr(void *priv) 964 { 965 struct axppmic_softc * const sc = priv; 966 967 mutex_enter(&sc->sc_intr_lock); 968 969 fdtbus_intr_mask(sc->sc_phandle, sc->sc_ih); 970 971 /* Interrupt is always masked when work is scheduled! */ 972 KASSERT(!sc->sc_work_scheduled); 973 sc->sc_work_scheduled = true; 974 workqueue_enqueue(sc->sc_wq, &sc->sc_work, NULL); 975 976 mutex_exit(&sc->sc_intr_lock); 977 978 return 1; 979 } 980 981 static void 982 axppmic_work(struct work *work, void *arg) 983 { 984 struct axppmic_softc * const sc = 985 container_of(work, struct axppmic_softc, sc_work); 986 const struct axppmic_config * const c = sc->sc_conf; 987 const int flags = 0; 988 uint8_t stat; 989 u_int n; 990 991 KASSERT(sc->sc_work_scheduled); 992 993 iic_acquire_bus(sc->sc_i2c, flags); 994 for (n = 1; n <= c->irq_regs; n++) { 995 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_IRQ_STATUS_REG(n), &stat, flags) == 0) { 996 if (stat != 0) { 997 axppmic_write(sc->sc_i2c, sc->sc_addr, 998 AXP_IRQ_STATUS_REG(n), stat, flags); 999 } 1000 1001 if (n == c->poklirq.reg && (stat & c->poklirq.mask) != 0) 1002 sysmon_task_queue_sched(0, axppmic_task_shut, sc); 1003 if (n == c->acinirq.reg && (stat & c->acinirq.mask) != 0) 1004 axppmic_sensor_update(sc->sc_sme, &sc->sc_sensor[AXP_SENSOR_ACIN_PRESENT]); 1005 if (n == c->vbusirq.reg && (stat & c->vbusirq.mask) != 0) 1006 axppmic_sensor_update(sc->sc_sme, &sc->sc_sensor[AXP_SENSOR_VBUS_PRESENT]); 1007 if (n == c->battirq.reg && (stat & c->battirq.mask) != 0) 1008 axppmic_sensor_update(sc->sc_sme, &sc->sc_sensor[AXP_SENSOR_BATT_PRESENT]); 1009 if (n == c->chargeirq.reg && (stat & c->chargeirq.mask) != 0) 1010 axppmic_sensor_update(sc->sc_sme, &sc->sc_sensor[AXP_SENSOR_BATT_CHARGING]); 1011 if (n == c->chargestirq.reg && (stat & c->chargestirq.mask) != 0) 1012 axppmic_sensor_update(sc->sc_sme, &sc->sc_sensor[AXP_SENSOR_BATT_CHARGE_STATE]); 1013 } 1014 } 1015 iic_release_bus(sc->sc_i2c, flags); 1016 1017 mutex_enter(&sc->sc_intr_lock); 1018 sc->sc_work_scheduled = false; 1019 fdtbus_intr_unmask(sc->sc_phandle, sc->sc_ih); 1020 mutex_exit(&sc->sc_intr_lock); 1021 } 1022 1023 static void 1024 axppmic_attach_acadapter(struct axppmic_softc *sc) 1025 { 1026 envsys_data_t *e; 1027 1028 e = &sc->sc_sensor[AXP_SENSOR_ACIN_PRESENT]; 1029 e->private = AXP_SENSOR_ACIN_PRESENT; 1030 e->units = ENVSYS_INDICATOR; 1031 e->state = ENVSYS_SINVALID; 1032 strlcpy(e->desc, "ACIN present", sizeof(e->desc)); 1033 sysmon_envsys_sensor_attach(sc->sc_sme, e); 1034 1035 e = &sc->sc_sensor[AXP_SENSOR_VBUS_PRESENT]; 1036 e->private = AXP_SENSOR_VBUS_PRESENT; 1037 e->units = ENVSYS_INDICATOR; 1038 e->state = ENVSYS_SINVALID; 1039 strlcpy(e->desc, "VBUS present", sizeof(e->desc)); 1040 sysmon_envsys_sensor_attach(sc->sc_sme, e); 1041 } 1042 1043 static void 1044 axppmic_attach_battery(struct axppmic_softc *sc) 1045 { 1046 const struct axppmic_config *c = sc->sc_conf; 1047 envsys_data_t *e; 1048 uint8_t val; 1049 1050 iic_acquire_bus(sc->sc_i2c, 0); 1051 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_CAP_WARN_REG, &val, 0) == 0) { 1052 sc->sc_warn_thres = __SHIFTOUT(val, AXP_BATT_CAP_WARN_LV1) + 5; 1053 sc->sc_shut_thres = __SHIFTOUT(val, AXP_BATT_CAP_WARN_LV2); 1054 } 1055 iic_release_bus(sc->sc_i2c, 0); 1056 1057 e = &sc->sc_sensor[AXP_SENSOR_BATT_PRESENT]; 1058 e->private = AXP_SENSOR_BATT_PRESENT; 1059 e->units = ENVSYS_INDICATOR; 1060 e->state = ENVSYS_SINVALID; 1061 strlcpy(e->desc, "battery present", sizeof(e->desc)); 1062 sysmon_envsys_sensor_attach(sc->sc_sme, e); 1063 1064 e = &sc->sc_sensor[AXP_SENSOR_BATT_CHARGING]; 1065 e->private = AXP_SENSOR_BATT_CHARGING; 1066 e->units = ENVSYS_BATTERY_CHARGE; 1067 e->state = ENVSYS_SINVALID; 1068 strlcpy(e->desc, "charging", sizeof(e->desc)); 1069 sysmon_envsys_sensor_attach(sc->sc_sme, e); 1070 1071 e = &sc->sc_sensor[AXP_SENSOR_BATT_CHARGE_STATE]; 1072 e->private = AXP_SENSOR_BATT_CHARGE_STATE; 1073 e->units = ENVSYS_BATTERY_CAPACITY; 1074 e->flags = ENVSYS_FMONSTCHANGED; 1075 e->state = ENVSYS_SINVALID; 1076 e->value_cur = ENVSYS_BATTERY_CAPACITY_NORMAL; 1077 strlcpy(e->desc, "charge state", sizeof(e->desc)); 1078 sysmon_envsys_sensor_attach(sc->sc_sme, e); 1079 1080 if (c->batsense_step) { 1081 e = &sc->sc_sensor[AXP_SENSOR_BATT_VOLTAGE]; 1082 e->private = AXP_SENSOR_BATT_VOLTAGE; 1083 e->units = ENVSYS_SVOLTS_DC; 1084 e->state = ENVSYS_SINVALID; 1085 strlcpy(e->desc, "battery voltage", sizeof(e->desc)); 1086 sysmon_envsys_sensor_attach(sc->sc_sme, e); 1087 } 1088 1089 if (c->charge_step) { 1090 e = &sc->sc_sensor[AXP_SENSOR_BATT_CHARGE_CURRENT]; 1091 e->private = AXP_SENSOR_BATT_CHARGE_CURRENT; 1092 e->units = ENVSYS_SAMPS; 1093 e->state = ENVSYS_SINVALID; 1094 strlcpy(e->desc, "battery charge current", sizeof(e->desc)); 1095 sysmon_envsys_sensor_attach(sc->sc_sme, e); 1096 } 1097 1098 if (c->discharge_step) { 1099 e = &sc->sc_sensor[AXP_SENSOR_BATT_DISCHARGE_CURRENT]; 1100 e->private = AXP_SENSOR_BATT_DISCHARGE_CURRENT; 1101 e->units = ENVSYS_SAMPS; 1102 e->state = ENVSYS_SINVALID; 1103 strlcpy(e->desc, "battery discharge current", sizeof(e->desc)); 1104 sysmon_envsys_sensor_attach(sc->sc_sme, e); 1105 } 1106 1107 if (c->has_fuel_gauge) { 1108 e = &sc->sc_sensor[AXP_SENSOR_BATT_CAPACITY_PERCENT]; 1109 e->private = AXP_SENSOR_BATT_CAPACITY_PERCENT; 1110 e->units = ENVSYS_INTEGER; 1111 e->state = ENVSYS_SINVALID; 1112 e->flags = ENVSYS_FPERCENT; 1113 strlcpy(e->desc, "battery percent", sizeof(e->desc)); 1114 sysmon_envsys_sensor_attach(sc->sc_sme, e); 1115 } 1116 1117 if (c->maxcap_step) { 1118 e = &sc->sc_sensor[AXP_SENSOR_BATT_MAXIMUM_CAPACITY]; 1119 e->private = AXP_SENSOR_BATT_MAXIMUM_CAPACITY; 1120 e->units = ENVSYS_SAMPHOUR; 1121 e->state = ENVSYS_SINVALID; 1122 strlcpy(e->desc, "battery maximum capacity", sizeof(e->desc)); 1123 sysmon_envsys_sensor_attach(sc->sc_sme, e); 1124 } 1125 1126 if (c->coulomb_step) { 1127 e = &sc->sc_sensor[AXP_SENSOR_BATT_CURRENT_CAPACITY]; 1128 e->private = AXP_SENSOR_BATT_CURRENT_CAPACITY; 1129 e->units = ENVSYS_SAMPHOUR; 1130 e->state = ENVSYS_SINVALID; 1131 strlcpy(e->desc, "battery current capacity", sizeof(e->desc)); 1132 sysmon_envsys_sensor_attach(sc->sc_sme, e); 1133 } 1134 } 1135 1136 static void 1137 axppmic_attach_sensors(struct axppmic_softc *sc) 1138 { 1139 if (sc->sc_conf->has_battery) { 1140 sc->sc_sme = sysmon_envsys_create(); 1141 sc->sc_sme->sme_name = device_xname(sc->sc_dev); 1142 sc->sc_sme->sme_cookie = sc; 1143 sc->sc_sme->sme_refresh = axppmic_sensor_refresh; 1144 sc->sc_sme->sme_class = SME_CLASS_BATTERY; 1145 sc->sc_sme->sme_flags = SME_INIT_REFRESH; 1146 1147 axppmic_attach_acadapter(sc); 1148 axppmic_attach_battery(sc); 1149 1150 sysmon_envsys_register(sc->sc_sme); 1151 } 1152 } 1153 1154 1155 static int 1156 axppmic_match(device_t parent, cfdata_t match, void *aux) 1157 { 1158 struct i2c_attach_args *ia = aux; 1159 int match_result; 1160 1161 if (iic_use_direct_match(ia, match, compat_data, &match_result)) 1162 return match_result; 1163 1164 /* This device is direct-config only. */ 1165 1166 return 0; 1167 } 1168 1169 static void 1170 axppmic_attach(device_t parent, device_t self, void *aux) 1171 { 1172 struct axppmic_softc *sc = device_private(self); 1173 const struct device_compatible_entry *dce = NULL; 1174 const struct axppmic_config *c; 1175 struct axpreg_attach_args aaa; 1176 struct i2c_attach_args *ia = aux; 1177 int phandle, child, i; 1178 uint8_t irq_mask, val; 1179 int error; 1180 1181 dce = iic_compatible_lookup(ia, compat_data); 1182 KASSERT(dce != NULL); 1183 c = dce->data; 1184 1185 sc->sc_dev = self; 1186 sc->sc_i2c = ia->ia_tag; 1187 sc->sc_addr = ia->ia_addr; 1188 sc->sc_phandle = devhandle_to_of(device_handle(self)); 1189 sc->sc_conf = c; 1190 1191 aprint_naive("\n"); 1192 aprint_normal(": %s\n", c->name); 1193 1194 if (c->has_mode_set) { 1195 const bool master_mode = 1196 of_hasprop(sc->sc_phandle, "x-powers,self-working-mode") || 1197 of_hasprop(sc->sc_phandle, "x-powers,master-mode"); 1198 1199 iic_acquire_bus(sc->sc_i2c, 0); 1200 axppmic_write(sc->sc_i2c, sc->sc_addr, AXP_ADDR_EXT_REG, 1201 master_mode ? AXP_ADDR_EXT_MASTER : AXP_ADDR_EXT_SLAVE, 0); 1202 iic_release_bus(sc->sc_i2c, 0); 1203 } 1204 1205 iic_acquire_bus(sc->sc_i2c, 0); 1206 error = axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_CHIP_ID_REG, &val, 0); 1207 iic_release_bus(sc->sc_i2c, 0); 1208 if (error != 0) { 1209 aprint_error_dev(self, "couldn't read chipid\n"); 1210 return; 1211 } 1212 aprint_debug_dev(self, "chipid %#x\n", val); 1213 1214 sc->sc_smpsw.smpsw_name = device_xname(self); 1215 sc->sc_smpsw.smpsw_type = PSWITCH_TYPE_POWER; 1216 sysmon_pswitch_register(&sc->sc_smpsw); 1217 1218 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_VM); 1219 1220 if (c->irq_regs > 0) { 1221 char intrstr[128]; 1222 1223 if (!fdtbus_intr_str(sc->sc_phandle, 0, 1224 intrstr, sizeof(intrstr))) { 1225 aprint_error_dev(self, 1226 "WARNING: failed to decode interrupt\n"); 1227 } 1228 1229 sc->sc_ih = fdtbus_intr_establish(sc->sc_phandle, 0, IPL_VM, 1230 FDT_INTR_MPSAFE, 1231 axppmic_intr, sc); 1232 if (sc->sc_ih == NULL) { 1233 aprint_error_dev(self, 1234 "WARNING: couldn't establish interrupt handler\n"); 1235 } 1236 1237 error = workqueue_create(&sc->sc_wq, device_xname(self), 1238 axppmic_work, NULL, 1239 PRI_SOFTSERIAL, IPL_VM, 1240 WQ_MPSAFE); 1241 if (error) { 1242 sc->sc_wq = NULL; 1243 aprint_error_dev(self, 1244 "WARNING: couldn't create work queue: error %d\n", 1245 error); 1246 } 1247 1248 if (sc->sc_ih != NULL && sc->sc_wq != NULL) { 1249 iic_acquire_bus(sc->sc_i2c, 0); 1250 for (i = 1; i <= c->irq_regs; i++) { 1251 irq_mask = 0; 1252 if (i == c->poklirq.reg) 1253 irq_mask |= c->poklirq.mask; 1254 if (i == c->acinirq.reg) 1255 irq_mask |= c->acinirq.mask; 1256 if (i == c->vbusirq.reg) 1257 irq_mask |= c->vbusirq.mask; 1258 if (i == c->battirq.reg) 1259 irq_mask |= c->battirq.mask; 1260 if (i == c->chargeirq.reg) 1261 irq_mask |= c->chargeirq.mask; 1262 if (i == c->chargestirq.reg) 1263 irq_mask |= c->chargestirq.mask; 1264 axppmic_write(sc->sc_i2c, sc->sc_addr, 1265 AXP_IRQ_ENABLE_REG(i), 1266 irq_mask, 0); 1267 } 1268 iic_release_bus(sc->sc_i2c, 0); 1269 } 1270 } 1271 1272 fdtbus_register_power_controller(sc->sc_dev, sc->sc_phandle, 1273 &axppmic_power_funcs); 1274 1275 if (c->gpio_compat != NULL) { 1276 phandle = of_find_bycompat(sc->sc_phandle, c->gpio_compat); 1277 if (phandle > 0) { 1278 fdtbus_register_gpio_controller(self, phandle, 1279 &axppmic_gpio_funcs); 1280 } 1281 } 1282 1283 phandle = of_find_firstchild_byname(sc->sc_phandle, "regulators"); 1284 if (phandle > 0) { 1285 aaa.reg_i2c = sc->sc_i2c; 1286 aaa.reg_addr = sc->sc_addr; 1287 for (i = 0; i < c->ncontrols; i++) { 1288 const struct axppmic_ctrl *ctrl = &c->controls[i]; 1289 child = of_find_firstchild_byname(phandle, ctrl->c_name); 1290 if (child <= 0) 1291 continue; 1292 aaa.reg_ctrl = ctrl; 1293 aaa.reg_phandle = child; 1294 config_found(sc->sc_dev, &aaa, NULL, CFARGS_NONE); 1295 } 1296 } 1297 1298 if (c->has_battery) 1299 axppmic_attach_sensors(sc); 1300 } 1301 1302 static int 1303 axpreg_acquire(device_t dev) 1304 { 1305 return 0; 1306 } 1307 1308 static void 1309 axpreg_release(device_t dev) 1310 { 1311 } 1312 1313 static int 1314 axpreg_enable(device_t dev, bool enable) 1315 { 1316 struct axpreg_softc *sc = device_private(dev); 1317 const struct axppmic_ctrl *c = sc->sc_ctrl; 1318 const int flags = 0; 1319 uint8_t val; 1320 int error; 1321 1322 if (!c->c_enable_mask) 1323 return EINVAL; 1324 1325 iic_acquire_bus(sc->sc_i2c, flags); 1326 if ((error = axppmic_read(sc->sc_i2c, sc->sc_addr, c->c_enable_reg, &val, flags)) == 0) { 1327 val &= ~c->c_enable_mask; 1328 if (enable) 1329 val |= c->c_enable_val; 1330 else 1331 val |= c->c_disable_val; 1332 error = axppmic_write(sc->sc_i2c, sc->sc_addr, c->c_enable_reg, val, flags); 1333 } 1334 iic_release_bus(sc->sc_i2c, flags); 1335 1336 return error; 1337 } 1338 1339 static int 1340 axpreg_set_voltage(device_t dev, u_int min_uvol, u_int max_uvol) 1341 { 1342 struct axpreg_softc *sc = device_private(dev); 1343 const struct axppmic_ctrl *c = sc->sc_ctrl; 1344 1345 return axppmic_set_voltage(sc->sc_i2c, sc->sc_addr, c, 1346 min_uvol / 1000, max_uvol / 1000); 1347 } 1348 1349 static int 1350 axpreg_get_voltage(device_t dev, u_int *puvol) 1351 { 1352 struct axpreg_softc *sc = device_private(dev); 1353 const struct axppmic_ctrl *c = sc->sc_ctrl; 1354 int error; 1355 u_int vol; 1356 1357 error = axppmic_get_voltage(sc->sc_i2c, sc->sc_addr, c, &vol); 1358 if (error) 1359 return error; 1360 1361 *puvol = vol * 1000; 1362 return 0; 1363 } 1364 1365 static struct fdtbus_regulator_controller_func axpreg_funcs = { 1366 .acquire = axpreg_acquire, 1367 .release = axpreg_release, 1368 .enable = axpreg_enable, 1369 .set_voltage = axpreg_set_voltage, 1370 .get_voltage = axpreg_get_voltage, 1371 }; 1372 1373 static int 1374 axpreg_match(device_t parent, cfdata_t match, void *aux) 1375 { 1376 return 1; 1377 } 1378 1379 static void 1380 axpreg_attach(device_t parent, device_t self, void *aux) 1381 { 1382 struct axpreg_softc *sc = device_private(self); 1383 struct axpreg_attach_args *aaa = aux; 1384 const int phandle = aaa->reg_phandle; 1385 const char *name; 1386 u_int uvol, min_uvol, max_uvol; 1387 1388 sc->sc_dev = self; 1389 sc->sc_i2c = aaa->reg_i2c; 1390 sc->sc_addr = aaa->reg_addr; 1391 sc->sc_ctrl = aaa->reg_ctrl; 1392 1393 fdtbus_register_regulator_controller(self, phandle, 1394 &axpreg_funcs); 1395 1396 aprint_naive("\n"); 1397 name = fdtbus_get_string(phandle, "regulator-name"); 1398 if (name) 1399 aprint_normal(": %s\n", name); 1400 else 1401 aprint_normal("\n"); 1402 1403 int error = axpreg_get_voltage(self, &uvol); 1404 if (error) 1405 return; 1406 1407 if (of_getprop_uint32(phandle, "regulator-min-microvolt", &min_uvol) == 0 && 1408 of_getprop_uint32(phandle, "regulator-max-microvolt", &max_uvol) == 0) { 1409 if (uvol < min_uvol || uvol > max_uvol) { 1410 aprint_debug_dev(self, "fix voltage %u uV -> %u/%u uV\n", 1411 uvol, min_uvol, max_uvol); 1412 axpreg_set_voltage(self, min_uvol, max_uvol); 1413 } 1414 } 1415 1416 if (of_hasprop(phandle, "regulator-always-on") || 1417 of_hasprop(phandle, "regulator-boot-on")) { 1418 axpreg_enable(self, true); 1419 } 1420 } 1421 1422 CFATTACH_DECL_NEW(axppmic, sizeof(struct axppmic_softc), 1423 axppmic_match, axppmic_attach, NULL, NULL); 1424 1425 CFATTACH_DECL_NEW(axpreg, sizeof(struct axpreg_softc), 1426 axpreg_match, axpreg_attach, NULL, NULL); 1427
Indexes created Fri Oct 03 02:09:57 GMT 2025