axppmic.c revision 1.9
1 /* $NetBSD: axppmic.c,v 1.9 2018/05/13 22:58:58 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2014-2018 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: axppmic.c,v 1.9 2018/05/13 22:58:58 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/device.h> 36 #include <sys/conf.h> 37 #include <sys/bus.h> 38 #include <sys/kmem.h> 39 40 #include <dev/i2c/i2cvar.h> 41 42 #include <dev/sysmon/sysmonvar.h> 43 #include <dev/sysmon/sysmon_taskq.h> 44 45 #include <dev/fdt/fdtvar.h> 46 47 #define AXP_POWER_SOURCE_REG 0x00 48 #define AXP_POWER_SOURCE_ACIN_PRESENT __BIT(7) 49 #define AXP_POWER_SOURCE_VBUS_PRESENT __BIT(5) 50 51 #define AXP_POWER_MODE_REG 0x01 52 #define AXP_POWER_MODE_BATT_VALID __BIT(4) 53 #define AXP_POWER_MODE_BATT_PRESENT __BIT(5) 54 #define AXP_POWER_MODE_BATT_CHARGING __BIT(6) 55 56 #define AXP_POWER_DISABLE_REG 0x32 57 #define AXP_POWER_DISABLE_CTRL __BIT(7) 58 59 #define AXP_IRQ_ENABLE_REG(n) (0x40 + (n) - 1) 60 #define AXP_IRQ1_ACIN_RAISE __BIT(6) 61 #define AXP_IRQ1_ACIN_LOWER __BIT(5) 62 #define AXP_IRQ1_VBUS_RAISE __BIT(3) 63 #define AXP_IRQ1_VBUS_LOWER __BIT(2) 64 #define AXP_IRQ_STATUS_REG(n) (0x48 + (n) - 1) 65 66 #define AXP_FUEL_GAUGE_CTRL_REG 0xb8 67 #define AXP_FUEL_GAUGE_CTRL_EN __BIT(7) 68 #define AXP_BATT_CAP_REG 0xb9 69 #define AXP_BATT_CAP_VALID __BIT(7) 70 #define AXP_BATT_CAP_PERCENT __BITS(6,0) 71 72 #define AXP_BATT_CAP_WARN_REG 0xe6 73 #define AXP_BATT_CAP_WARN_LV1 __BITS(7,4) 74 #define AXP_BATT_CAP_WARN_LV2 __BITS(3,0) 75 76 struct axppmic_ctrl { 77 device_t c_dev; 78 79 const char * c_name; 80 u_int c_min; 81 u_int c_max; 82 u_int c_step1; 83 u_int c_step1cnt; 84 u_int c_step2; 85 u_int c_step2cnt; 86 87 uint8_t c_enable_reg; 88 uint8_t c_enable_mask; 89 90 uint8_t c_voltage_reg; 91 uint8_t c_voltage_mask; 92 }; 93 94 #define AXP_CTRL(name, min, max, step, ereg, emask, vreg, vmask) \ 95 { .c_name = (name), .c_min = (min), .c_max = (max), \ 96 .c_step1 = (step), .c_step1cnt = (((max) - (min)) / (step)) + 1, \ 97 .c_step2 = 0, .c_step2cnt = 0, \ 98 .c_enable_reg = (ereg), .c_enable_mask = (emask), \ 99 .c_voltage_reg = (vreg), .c_voltage_mask = (vmask) } 100 101 #define AXP_CTRL2(name, min, max, step1, step1cnt, step2, step2cnt, ereg, emask, vreg, vmask) \ 102 { .c_name = (name), .c_min = (min), .c_max = (max), \ 103 .c_step1 = (step1), .c_step1cnt = (step1cnt), \ 104 .c_step2 = (step2), .c_step2cnt = (step2cnt), \ 105 .c_enable_reg = (ereg), .c_enable_mask = (emask), \ 106 .c_voltage_reg = (vreg), .c_voltage_mask = (vmask) } 107 108 static const struct axppmic_ctrl axp803_ctrls[] = { 109 AXP_CTRL("dldo1", 700, 3300, 100, 110 0x12, __BIT(3), 0x15, __BITS(4,0)), 111 AXP_CTRL2("dldo2", 700, 4200, 100, 28, 200, 4, 112 0x12, __BIT(4), 0x16, __BITS(4,0)), 113 AXP_CTRL("dldo3", 700, 3300, 100, 114 0x12, __BIT(5), 0x17, __BITS(4,0)), 115 AXP_CTRL("dldo4", 700, 3300, 100, 116 0x12, __BIT(6), 0x18, __BITS(4,0)), 117 AXP_CTRL("eldo1", 700, 1900, 50, 118 0x12, __BIT(0), 0x19, __BITS(4,0)), 119 AXP_CTRL("eldo2", 700, 1900, 50, 120 0x12, __BIT(1), 0x1a, __BITS(4,0)), 121 AXP_CTRL("eldo3", 700, 1900, 50, 122 0x12, __BIT(2), 0x1b, __BITS(4,0)), 123 AXP_CTRL("fldo1", 700, 1450, 50, 124 0x13, __BIT(2), 0x1c, __BITS(3,0)), 125 AXP_CTRL("fldo2", 700, 1450, 50, 126 0x13, __BIT(3), 0x1d, __BITS(3,0)), 127 AXP_CTRL("dcdc1", 1600, 3400, 100, 128 0x10, __BIT(0), 0x20, __BITS(4,0)), 129 AXP_CTRL2("dcdc2", 500, 1300, 10, 70, 20, 5, 130 0x10, __BIT(1), 0x21, __BITS(6,0)), 131 AXP_CTRL2("dcdc3", 500, 1300, 10, 70, 20, 5, 132 0x10, __BIT(2), 0x22, __BITS(6,0)), 133 AXP_CTRL2("dcdc4", 500, 1300, 10, 70, 20, 5, 134 0x10, __BIT(3), 0x23, __BITS(6,0)), 135 AXP_CTRL2("dcdc5", 800, 1840, 10, 33, 20, 36, 136 0x10, __BIT(4), 0x24, __BITS(6,0)), 137 AXP_CTRL2("dcdc6", 600, 1520, 10, 51, 20, 21, 138 0x10, __BIT(5), 0x25, __BITS(6,0)), 139 AXP_CTRL("aldo1", 700, 3300, 100, 140 0x13, __BIT(5), 0x28, __BITS(4,0)), 141 AXP_CTRL("aldo2", 700, 3300, 100, 142 0x13, __BIT(6), 0x29, __BITS(4,0)), 143 AXP_CTRL("aldo3", 700, 3300, 100, 144 0x13, __BIT(7), 0x2a, __BITS(4,0)), 145 }; 146 147 static const struct axppmic_ctrl axp805_ctrls[] = { 148 AXP_CTRL2("dcdca", 600, 1520, 10, 51, 20, 21, 149 0x10, __BIT(0), 0x12, __BITS(6,0)), 150 AXP_CTRL("dcdcb", 1000, 2550, 50, 151 0x10, __BIT(1), 0x13, __BITS(4,0)), 152 AXP_CTRL2("dcdcc", 600, 1520, 10, 51, 20, 21, 153 0x10, __BIT(2), 0x14, __BITS(6,0)), 154 AXP_CTRL2("dcdcd", 600, 3300, 20, 46, 100, 18, 155 0x10, __BIT(3), 0x15, __BITS(5,0)), 156 AXP_CTRL("dcdce", 1100, 3400, 100, 157 0x10, __BIT(4), 0x16, __BITS(4,0)), 158 AXP_CTRL("aldo1", 700, 3300, 100, 159 0x10, __BIT(5), 0x17, __BITS(4,0)), 160 AXP_CTRL("aldo2", 700, 3400, 100, 161 0x10, __BIT(6), 0x18, __BITS(4,0)), 162 AXP_CTRL("aldo3", 700, 3300, 100, 163 0x10, __BIT(7), 0x19, __BITS(4,0)), 164 AXP_CTRL("bldo1", 700, 1900, 100, 165 0x11, __BIT(0), 0x20, __BITS(3,0)), 166 AXP_CTRL("bldo2", 700, 1900, 100, 167 0x11, __BIT(1), 0x21, __BITS(3,0)), 168 AXP_CTRL("bldo3", 700, 1900, 100, 169 0x11, __BIT(2), 0x22, __BITS(3,0)), 170 AXP_CTRL("bldo4", 700, 1900, 100, 171 0x11, __BIT(3), 0x23, __BITS(3,0)), 172 AXP_CTRL("cldo1", 700, 3300, 100, 173 0x11, __BIT(4), 0x24, __BITS(4,0)), 174 AXP_CTRL2("cldo2", 700, 4200, 100, 28, 200, 4, 175 0x11, __BIT(5), 0x25, __BITS(4,0)), 176 AXP_CTRL("cldo3", 700, 3300, 100, 177 0x11, __BIT(6), 0x26, __BITS(4,0)), 178 }; 179 180 struct axppmic_irq { 181 u_int reg; 182 uint8_t mask; 183 }; 184 185 #define AXPPMIC_IRQ(_reg, _mask) \ 186 { .reg = (_reg), .mask = (_mask) } 187 188 struct axppmic_config { 189 const char *name; 190 const struct axppmic_ctrl *controls; 191 u_int ncontrols; 192 u_int irq_regs; 193 bool has_battery; 194 bool has_fuel_gauge; 195 struct axppmic_irq poklirq; 196 struct axppmic_irq acinirq; 197 struct axppmic_irq vbusirq; 198 struct axppmic_irq battirq; 199 struct axppmic_irq chargeirq; 200 struct axppmic_irq chargestirq; 201 }; 202 203 enum axppmic_sensor { 204 AXP_SENSOR_ACIN_PRESENT, 205 AXP_SENSOR_VBUS_PRESENT, 206 AXP_SENSOR_BATT_PRESENT, 207 AXP_SENSOR_BATT_CHARGING, 208 AXP_SENSOR_BATT_CHARGE_STATE, 209 AXP_SENSOR_BATT_CAPACITY, 210 AXP_NSENSORS 211 }; 212 213 struct axppmic_softc { 214 device_t sc_dev; 215 i2c_tag_t sc_i2c; 216 i2c_addr_t sc_addr; 217 int sc_phandle; 218 219 const struct axppmic_config *sc_conf; 220 221 struct sysmon_pswitch sc_smpsw; 222 223 struct sysmon_envsys *sc_sme; 224 225 envsys_data_t sc_sensor[AXP_NSENSORS]; 226 227 u_int sc_warn_thres; 228 u_int sc_shut_thres; 229 }; 230 231 struct axpreg_softc { 232 device_t sc_dev; 233 i2c_tag_t sc_i2c; 234 i2c_addr_t sc_addr; 235 const struct axppmic_ctrl *sc_ctrl; 236 }; 237 238 struct axpreg_attach_args { 239 const struct axppmic_ctrl *reg_ctrl; 240 int reg_phandle; 241 i2c_tag_t reg_i2c; 242 i2c_addr_t reg_addr; 243 }; 244 245 static const struct axppmic_config axp803_config = { 246 .name = "AXP803", 247 .controls = axp803_ctrls, 248 .ncontrols = __arraycount(axp803_ctrls), 249 .irq_regs = 6, 250 .has_battery = true, 251 .has_fuel_gauge = true, 252 .poklirq = AXPPMIC_IRQ(5, __BIT(3)), 253 .acinirq = AXPPMIC_IRQ(1, __BITS(6,5)), 254 .vbusirq = AXPPMIC_IRQ(1, __BITS(3,2)), 255 .battirq = AXPPMIC_IRQ(2, __BITS(7,6)), 256 .chargeirq = AXPPMIC_IRQ(2, __BITS(3,2)), 257 .chargestirq = AXPPMIC_IRQ(4, __BITS(1,0)), 258 }; 259 260 static const struct axppmic_config axp805_config = { 261 .name = "AXP805/806", 262 .controls = axp805_ctrls, 263 .ncontrols = __arraycount(axp805_ctrls), 264 .irq_regs = 2, 265 .poklirq = AXPPMIC_IRQ(2, __BIT(0)), 266 }; 267 268 static const struct of_compat_data compat_data[] = { 269 { "x-powers,axp803", (uintptr_t)&axp803_config }, 270 { "x-powers,axp805", (uintptr_t)&axp805_config }, 271 { "x-powers,axp806", (uintptr_t)&axp805_config }, 272 { NULL } 273 }; 274 275 static int 276 axppmic_read(i2c_tag_t tag, i2c_addr_t addr, uint8_t reg, uint8_t *val, int flags) 277 { 278 return iic_smbus_read_byte(tag, addr, reg, val, flags); 279 } 280 281 static int 282 axppmic_write(i2c_tag_t tag, i2c_addr_t addr, uint8_t reg, uint8_t val, int flags) 283 { 284 return iic_smbus_write_byte(tag, addr, reg, val, flags); 285 } 286 287 static int 288 axppmic_set_voltage(i2c_tag_t tag, i2c_addr_t addr, const struct axppmic_ctrl *c, u_int min, u_int max) 289 { 290 const int flags = (cold ? I2C_F_POLL : 0); 291 u_int vol, reg_val; 292 int nstep, error; 293 uint8_t val; 294 295 if (!c->c_voltage_mask) 296 return EINVAL; 297 298 if (min < c->c_min || min > c->c_max) 299 return EINVAL; 300 301 reg_val = 0; 302 nstep = 1; 303 vol = c->c_min; 304 305 for (nstep = 0; nstep < c->c_step1cnt && vol < min; nstep++) { 306 ++reg_val; 307 vol += c->c_step1; 308 } 309 for (nstep = 0; nstep < c->c_step2cnt && vol < min; nstep++) { 310 ++reg_val; 311 vol += c->c_step2; 312 } 313 314 if (vol > max) 315 return EINVAL; 316 317 iic_acquire_bus(tag, flags); 318 if ((error = axppmic_read(tag, addr, c->c_voltage_reg, &val, flags)) == 0) { 319 val &= ~c->c_voltage_mask; 320 val |= __SHIFTIN(reg_val, c->c_voltage_mask); 321 error = axppmic_write(tag, addr, c->c_voltage_reg, val, flags); 322 } 323 iic_release_bus(tag, flags); 324 325 return error; 326 } 327 328 static int 329 axppmic_get_voltage(i2c_tag_t tag, i2c_addr_t addr, const struct axppmic_ctrl *c, u_int *pvol) 330 { 331 const int flags = (cold ? I2C_F_POLL : 0); 332 int reg_val, error; 333 uint8_t val; 334 335 if (!c->c_voltage_mask) 336 return EINVAL; 337 338 iic_acquire_bus(tag, flags); 339 error = axppmic_read(tag, addr, c->c_voltage_reg, &val, flags); 340 iic_release_bus(tag, flags); 341 if (error) 342 return error; 343 344 reg_val = __SHIFTOUT(val, c->c_voltage_mask); 345 if (reg_val < c->c_step1cnt) { 346 *pvol = c->c_min + reg_val * c->c_step1; 347 } else { 348 *pvol = c->c_min + (c->c_step1cnt * c->c_step1) + 349 ((reg_val - c->c_step1cnt) * c->c_step2); 350 } 351 352 return 0; 353 } 354 355 static void 356 axppmic_power_poweroff(device_t dev) 357 { 358 struct axppmic_softc *sc = device_private(dev); 359 360 delay(1000000); 361 362 iic_acquire_bus(sc->sc_i2c, I2C_F_POLL); 363 axppmic_write(sc->sc_i2c, sc->sc_addr, AXP_POWER_DISABLE_REG, AXP_POWER_DISABLE_CTRL, I2C_F_POLL); 364 iic_release_bus(sc->sc_i2c, I2C_F_POLL); 365 } 366 367 static struct fdtbus_power_controller_func axppmic_power_funcs = { 368 .poweroff = axppmic_power_poweroff, 369 }; 370 371 static void 372 axppmic_task_shut(void *priv) 373 { 374 struct axppmic_softc *sc = priv; 375 376 sysmon_pswitch_event(&sc->sc_smpsw, PSWITCH_EVENT_PRESSED); 377 } 378 379 static void 380 axppmic_sensor_update(struct sysmon_envsys *sme, envsys_data_t *e) 381 { 382 struct axppmic_softc *sc = sme->sme_cookie; 383 const int flags = I2C_F_POLL; 384 uint8_t val; 385 386 e->state = ENVSYS_SINVALID; 387 388 switch (e->private) { 389 case AXP_SENSOR_ACIN_PRESENT: 390 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_SOURCE_REG, &val, flags) == 0) { 391 e->state = ENVSYS_SVALID; 392 e->value_cur = !!(val & AXP_POWER_SOURCE_ACIN_PRESENT); 393 } 394 break; 395 case AXP_SENSOR_VBUS_PRESENT: 396 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_SOURCE_REG, &val, flags) == 0) { 397 e->state = ENVSYS_SVALID; 398 e->value_cur = !!(val & AXP_POWER_SOURCE_VBUS_PRESENT); 399 } 400 break; 401 case AXP_SENSOR_BATT_PRESENT: 402 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_MODE_REG, &val, flags) == 0) { 403 if (val & AXP_POWER_MODE_BATT_VALID) { 404 e->state = ENVSYS_SVALID; 405 e->value_cur = !!(val & AXP_POWER_MODE_BATT_PRESENT); 406 } 407 } 408 break; 409 case AXP_SENSOR_BATT_CHARGING: 410 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_MODE_REG, &val, flags) == 0) { 411 e->state = ENVSYS_SVALID; 412 e->value_cur = !!(val & AXP_POWER_MODE_BATT_CHARGING); 413 } 414 break; 415 case AXP_SENSOR_BATT_CHARGE_STATE: 416 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_MODE_REG, &val, flags) == 0 && 417 (val & AXP_POWER_MODE_BATT_VALID) != 0 && 418 (val & AXP_POWER_MODE_BATT_PRESENT) != 0 && 419 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_CAP_REG, &val, flags) == 0 && 420 (val & AXP_BATT_CAP_VALID) != 0) { 421 const u_int batt_val = __SHIFTOUT(val, AXP_BATT_CAP_PERCENT); 422 if (batt_val <= sc->sc_shut_thres) { 423 e->state = ENVSYS_SCRITICAL; 424 e->value_cur = ENVSYS_BATTERY_CAPACITY_CRITICAL; 425 } else if (batt_val <= sc->sc_warn_thres) { 426 e->state = ENVSYS_SWARNUNDER; 427 e->value_cur = ENVSYS_BATTERY_CAPACITY_WARNING; 428 } else { 429 e->state = ENVSYS_SVALID; 430 e->value_cur = ENVSYS_BATTERY_CAPACITY_NORMAL; 431 } 432 } 433 break; 434 case AXP_SENSOR_BATT_CAPACITY: 435 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_MODE_REG, &val, flags) == 0 && 436 (val & AXP_POWER_MODE_BATT_VALID) != 0 && 437 (val & AXP_POWER_MODE_BATT_PRESENT) != 0 && 438 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_CAP_REG, &val, flags) == 0 && 439 (val & AXP_BATT_CAP_VALID) != 0) { 440 e->state = ENVSYS_SVALID; 441 e->value_cur = __SHIFTOUT(val, AXP_BATT_CAP_PERCENT); 442 } 443 break; 444 } 445 } 446 447 static void 448 axppmic_sensor_refresh(struct sysmon_envsys *sme, envsys_data_t *e) 449 { 450 struct axppmic_softc *sc = sme->sme_cookie; 451 const int flags = I2C_F_POLL; 452 453 switch (e->private) { 454 case AXP_SENSOR_BATT_CAPACITY: 455 /* Always update battery capacity (fuel gauge) */ 456 iic_acquire_bus(sc->sc_i2c, flags); 457 axppmic_sensor_update(sme, e); 458 iic_release_bus(sc->sc_i2c, flags); 459 break; 460 default: 461 /* Refresh if the sensor is not in valid state */ 462 if (e->state != ENVSYS_SVALID) { 463 iic_acquire_bus(sc->sc_i2c, flags); 464 axppmic_sensor_update(sme, e); 465 iic_release_bus(sc->sc_i2c, flags); 466 } 467 break; 468 } 469 } 470 471 static int 472 axppmic_intr(void *priv) 473 { 474 struct axppmic_softc *sc = priv; 475 const struct axppmic_config *c = sc->sc_conf; 476 const int flags = I2C_F_POLL; 477 uint8_t stat; 478 u_int n; 479 480 iic_acquire_bus(sc->sc_i2c, flags); 481 for (n = 1; n <= c->irq_regs; n++) { 482 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_IRQ_STATUS_REG(n), &stat, flags) == 0) { 483 if (n == c->poklirq.reg && (stat & c->poklirq.mask) != 0) 484 sysmon_task_queue_sched(0, axppmic_task_shut, sc); 485 if (n == c->acinirq.reg && (stat & c->acinirq.mask) != 0) 486 axppmic_sensor_update(sc->sc_sme, &sc->sc_sensor[AXP_SENSOR_ACIN_PRESENT]); 487 if (n == c->vbusirq.reg && (stat & c->vbusirq.mask) != 0) 488 axppmic_sensor_update(sc->sc_sme, &sc->sc_sensor[AXP_SENSOR_VBUS_PRESENT]); 489 if (n == c->battirq.reg && (stat & c->battirq.mask) != 0) 490 axppmic_sensor_update(sc->sc_sme, &sc->sc_sensor[AXP_SENSOR_BATT_PRESENT]); 491 if (n == c->chargeirq.reg && (stat & c->chargeirq.mask) != 0) 492 axppmic_sensor_update(sc->sc_sme, &sc->sc_sensor[AXP_SENSOR_BATT_CHARGING]); 493 if (n == c->chargestirq.reg && (stat & c->chargestirq.mask) != 0) 494 axppmic_sensor_update(sc->sc_sme, &sc->sc_sensor[AXP_SENSOR_BATT_CHARGE_STATE]); 495 496 if (stat != 0) 497 axppmic_write(sc->sc_i2c, sc->sc_addr, 498 AXP_IRQ_STATUS_REG(n), stat, flags); 499 } 500 } 501 iic_release_bus(sc->sc_i2c, flags); 502 503 return 1; 504 } 505 506 static void 507 axppmic_attach_acadapter(struct axppmic_softc *sc) 508 { 509 envsys_data_t *e; 510 511 e = &sc->sc_sensor[AXP_SENSOR_ACIN_PRESENT]; 512 e->private = AXP_SENSOR_ACIN_PRESENT; 513 e->units = ENVSYS_INDICATOR; 514 e->state = ENVSYS_SINVALID; 515 strlcpy(e->desc, "ACIN present", sizeof(e->desc)); 516 sysmon_envsys_sensor_attach(sc->sc_sme, e); 517 518 e = &sc->sc_sensor[AXP_SENSOR_VBUS_PRESENT]; 519 e->private = AXP_SENSOR_VBUS_PRESENT; 520 e->units = ENVSYS_INDICATOR; 521 e->state = ENVSYS_SINVALID; 522 strlcpy(e->desc, "VBUS present", sizeof(e->desc)); 523 sysmon_envsys_sensor_attach(sc->sc_sme, e); 524 } 525 526 static void 527 axppmic_attach_battery(struct axppmic_softc *sc) 528 { 529 envsys_data_t *e; 530 uint8_t val; 531 532 iic_acquire_bus(sc->sc_i2c, I2C_F_POLL); 533 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_CAP_WARN_REG, &val, I2C_F_POLL) == 0) { 534 sc->sc_warn_thres = __SHIFTOUT(val, AXP_BATT_CAP_WARN_LV1) + 5; 535 sc->sc_shut_thres = __SHIFTOUT(val, AXP_BATT_CAP_WARN_LV2); 536 } 537 iic_release_bus(sc->sc_i2c, I2C_F_POLL); 538 539 e = &sc->sc_sensor[AXP_SENSOR_BATT_PRESENT]; 540 e->private = AXP_SENSOR_BATT_PRESENT; 541 e->units = ENVSYS_INDICATOR; 542 e->state = ENVSYS_SINVALID; 543 strlcpy(e->desc, "battery present", sizeof(e->desc)); 544 sysmon_envsys_sensor_attach(sc->sc_sme, e); 545 546 e = &sc->sc_sensor[AXP_SENSOR_BATT_CHARGING]; 547 e->private = AXP_SENSOR_BATT_CHARGING; 548 e->units = ENVSYS_BATTERY_CHARGE; 549 e->state = ENVSYS_SINVALID; 550 strlcpy(e->desc, "charging", sizeof(e->desc)); 551 sysmon_envsys_sensor_attach(sc->sc_sme, e); 552 553 e = &sc->sc_sensor[AXP_SENSOR_BATT_CHARGE_STATE]; 554 e->private = AXP_SENSOR_BATT_CHARGE_STATE; 555 e->units = ENVSYS_BATTERY_CAPACITY; 556 e->flags = ENVSYS_FMONSTCHANGED; 557 e->state = ENVSYS_SINVALID; 558 e->value_cur = ENVSYS_BATTERY_CAPACITY_NORMAL; 559 strlcpy(e->desc, "charge state", sizeof(e->desc)); 560 sysmon_envsys_sensor_attach(sc->sc_sme, e); 561 562 if (sc->sc_conf->has_fuel_gauge) { 563 e = &sc->sc_sensor[AXP_SENSOR_BATT_CAPACITY]; 564 e->private = AXP_SENSOR_BATT_CAPACITY; 565 e->units = ENVSYS_INTEGER; 566 e->state = ENVSYS_SINVALID; 567 e->flags = ENVSYS_FPERCENT; 568 strlcpy(e->desc, "battery percent", sizeof(e->desc)); 569 sysmon_envsys_sensor_attach(sc->sc_sme, e); 570 } 571 } 572 573 static void 574 axppmic_attach_sensors(struct axppmic_softc *sc) 575 { 576 if (sc->sc_conf->has_battery) { 577 sc->sc_sme = sysmon_envsys_create(); 578 sc->sc_sme->sme_name = device_xname(sc->sc_dev); 579 sc->sc_sme->sme_cookie = sc; 580 sc->sc_sme->sme_refresh = axppmic_sensor_refresh; 581 sc->sc_sme->sme_class = SME_CLASS_BATTERY; 582 sc->sc_sme->sme_flags = SME_INIT_REFRESH; 583 584 axppmic_attach_acadapter(sc); 585 axppmic_attach_battery(sc); 586 587 sysmon_envsys_register(sc->sc_sme); 588 } 589 } 590 591 592 static int 593 axppmic_match(device_t parent, cfdata_t match, void *aux) 594 { 595 struct i2c_attach_args *ia = aux; 596 597 if (ia->ia_name != NULL) { 598 if (ia->ia_cookie) 599 return of_match_compat_data(ia->ia_cookie, compat_data); 600 else 601 return 0; 602 } 603 604 return 1; 605 } 606 607 static void 608 axppmic_attach(device_t parent, device_t self, void *aux) 609 { 610 struct axppmic_softc *sc = device_private(self); 611 const struct axppmic_config *c; 612 struct axpreg_attach_args aaa; 613 struct i2c_attach_args *ia = aux; 614 int phandle, child, i; 615 uint32_t irq_mask; 616 void *ih; 617 618 c = (void *)of_search_compatible(ia->ia_cookie, compat_data)->data; 619 620 sc->sc_dev = self; 621 sc->sc_i2c = ia->ia_tag; 622 sc->sc_addr = ia->ia_addr; 623 sc->sc_phandle = ia->ia_cookie; 624 sc->sc_conf = c; 625 626 aprint_naive("\n"); 627 aprint_normal(": %s\n", c->name); 628 629 sc->sc_smpsw.smpsw_name = device_xname(self); 630 sc->sc_smpsw.smpsw_type = PSWITCH_TYPE_POWER; 631 sysmon_pswitch_register(&sc->sc_smpsw); 632 633 iic_acquire_bus(sc->sc_i2c, I2C_F_POLL); 634 for (i = 1; i <= c->irq_regs; i++) { 635 irq_mask = 0; 636 if (i == c->poklirq.reg) 637 irq_mask |= c->poklirq.mask; 638 if (i == c->acinirq.reg) 639 irq_mask |= c->acinirq.mask; 640 if (i == c->vbusirq.reg) 641 irq_mask |= c->vbusirq.mask; 642 if (i == c->battirq.reg) 643 irq_mask |= c->battirq.mask; 644 if (i == c->chargeirq.reg) 645 irq_mask |= c->chargeirq.mask; 646 if (i == c->chargestirq.reg) 647 irq_mask |= c->chargestirq.mask; 648 axppmic_write(sc->sc_i2c, sc->sc_addr, AXP_IRQ_ENABLE_REG(i), irq_mask, I2C_F_POLL); 649 } 650 iic_release_bus(sc->sc_i2c, I2C_F_POLL); 651 652 ih = fdtbus_intr_establish(sc->sc_phandle, 0, IPL_VM, FDT_INTR_MPSAFE, 653 axppmic_intr, sc); 654 if (ih == NULL) { 655 aprint_error_dev(self, "WARNING: couldn't establish interrupt handler\n"); 656 } 657 658 fdtbus_register_power_controller(sc->sc_dev, sc->sc_phandle, 659 &axppmic_power_funcs); 660 661 phandle = of_find_firstchild_byname(sc->sc_phandle, "regulators"); 662 if (phandle > 0) { 663 aaa.reg_i2c = sc->sc_i2c; 664 aaa.reg_addr = sc->sc_addr; 665 for (i = 0; i < c->ncontrols; i++) { 666 const struct axppmic_ctrl *ctrl = &c->controls[i]; 667 child = of_find_firstchild_byname(phandle, ctrl->c_name); 668 if (child <= 0) 669 continue; 670 aaa.reg_ctrl = ctrl; 671 aaa.reg_phandle = child; 672 config_found(sc->sc_dev, &aaa, NULL); 673 } 674 } 675 676 if (c->has_battery) 677 axppmic_attach_sensors(sc); 678 } 679 680 static int 681 axpreg_acquire(device_t dev) 682 { 683 return 0; 684 } 685 686 static void 687 axpreg_release(device_t dev) 688 { 689 } 690 691 static int 692 axpreg_enable(device_t dev, bool enable) 693 { 694 struct axpreg_softc *sc = device_private(dev); 695 const struct axppmic_ctrl *c = sc->sc_ctrl; 696 const int flags = (cold ? I2C_F_POLL : 0); 697 uint8_t val; 698 int error; 699 700 if (!c->c_enable_mask) 701 return EINVAL; 702 703 iic_acquire_bus(sc->sc_i2c, flags); 704 if ((error = axppmic_read(sc->sc_i2c, sc->sc_addr, c->c_enable_reg, &val, flags)) == 0) { 705 if (enable) 706 val |= c->c_enable_mask; 707 else 708 val &= ~c->c_enable_mask; 709 error = axppmic_write(sc->sc_i2c, sc->sc_addr, c->c_enable_reg, val, flags); 710 } 711 iic_release_bus(sc->sc_i2c, flags); 712 713 return error; 714 } 715 716 static int 717 axpreg_set_voltage(device_t dev, u_int min_uvol, u_int max_uvol) 718 { 719 struct axpreg_softc *sc = device_private(dev); 720 const struct axppmic_ctrl *c = sc->sc_ctrl; 721 722 return axppmic_set_voltage(sc->sc_i2c, sc->sc_addr, c, 723 min_uvol / 1000, max_uvol / 1000); 724 } 725 726 static int 727 axpreg_get_voltage(device_t dev, u_int *puvol) 728 { 729 struct axpreg_softc *sc = device_private(dev); 730 const struct axppmic_ctrl *c = sc->sc_ctrl; 731 int error; 732 u_int vol; 733 734 error = axppmic_get_voltage(sc->sc_i2c, sc->sc_addr, c, &vol); 735 if (error) 736 return error; 737 738 *puvol = vol * 1000; 739 return 0; 740 } 741 742 static struct fdtbus_regulator_controller_func axpreg_funcs = { 743 .acquire = axpreg_acquire, 744 .release = axpreg_release, 745 .enable = axpreg_enable, 746 .set_voltage = axpreg_set_voltage, 747 .get_voltage = axpreg_get_voltage, 748 }; 749 750 static int 751 axpreg_match(device_t parent, cfdata_t match, void *aux) 752 { 753 return 1; 754 } 755 756 static void 757 axpreg_attach(device_t parent, device_t self, void *aux) 758 { 759 struct axpreg_softc *sc = device_private(self); 760 struct axpreg_attach_args *aaa = aux; 761 const int phandle = aaa->reg_phandle; 762 const char *name; 763 764 sc->sc_dev = self; 765 sc->sc_i2c = aaa->reg_i2c; 766 sc->sc_addr = aaa->reg_addr; 767 sc->sc_ctrl = aaa->reg_ctrl; 768 769 fdtbus_register_regulator_controller(self, phandle, 770 &axpreg_funcs); 771 772 aprint_naive("\n"); 773 name = fdtbus_get_string(phandle, "regulator-name"); 774 if (name) 775 aprint_normal(": %s\n", name); 776 else 777 aprint_normal("\n"); 778 } 779 780 CFATTACH_DECL_NEW(axppmic, sizeof(struct axppmic_softc), 781 axppmic_match, axppmic_attach, NULL, NULL); 782 783 CFATTACH_DECL_NEW(axpreg, sizeof(struct axpreg_softc), 784 axpreg_match, axpreg_attach, NULL, NULL); 785
Indexes created Fri Oct 03 02:09:57 GMT 2025