axppmic.c revision 1.9.2.3 1 /* $NetBSD: axppmic.c,v 1.9.2.3 2018/06/25 07:25:50 pgoyette Exp $ */
2
3 /*-
4 * Copyright (c) 2014-2018 Jared McNeill <jmcneill (at) invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: axppmic.c,v 1.9.2.3 2018/06/25 07:25:50 pgoyette Exp $");
31
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
35 #include <sys/device.h>
36 #include <sys/conf.h>
37 #include <sys/bus.h>
38 #include <sys/kmem.h>
39
40 #include <dev/i2c/i2cvar.h>
41
42 #include <dev/sysmon/sysmonvar.h>
43 #include <dev/sysmon/sysmon_taskq.h>
44
45 #include <dev/fdt/fdtvar.h>
46
47 #define AXP_POWER_SOURCE_REG 0x00
48 #define AXP_POWER_SOURCE_ACIN_PRESENT __BIT(7)
49 #define AXP_POWER_SOURCE_VBUS_PRESENT __BIT(5)
50 #define AXP_POWER_SOURCE_CHARGE_DIRECTION __BIT(2)
51
52 #define AXP_POWER_MODE_REG 0x01
53 #define AXP_POWER_MODE_BATT_VALID __BIT(4)
54 #define AXP_POWER_MODE_BATT_PRESENT __BIT(5)
55 #define AXP_POWER_MODE_BATT_CHARGING __BIT(6)
56
57 #define AXP_POWER_DISABLE_REG 0x32
58 #define AXP_POWER_DISABLE_CTRL __BIT(7)
59
60 #define AXP_IRQ_ENABLE_REG(n) (0x40 + (n) - 1)
61 #define AXP_IRQ1_ACIN_RAISE __BIT(6)
62 #define AXP_IRQ1_ACIN_LOWER __BIT(5)
63 #define AXP_IRQ1_VBUS_RAISE __BIT(3)
64 #define AXP_IRQ1_VBUS_LOWER __BIT(2)
65 #define AXP_IRQ_STATUS_REG(n) (0x48 + (n) - 1)
66
67 #define AXP_BATSENSE_HI_REG 0x78
68 #define AXP_BATSENSE_LO_REG 0x79
69
70 #define AXP_BATTCHG_HI_REG 0x7a
71 #define AXP_BATTCHG_LO_REG 0x7b
72
73 #define AXP_BATTDISCHG_HI_REG 0x7c
74 #define AXP_BATTDISCHG_LO_REG 0x7d
75
76 #define AXP_ADC_RAW(_hi, _lo) \
77 (((u_int)(_hi) << 4) | ((lo) & 0xf))
78
79 #define AXP_FUEL_GAUGE_CTRL_REG 0xb8
80 #define AXP_FUEL_GAUGE_CTRL_EN __BIT(7)
81
82 #define AXP_BATT_CAP_REG 0xb9
83 #define AXP_BATT_CAP_VALID __BIT(7)
84 #define AXP_BATT_CAP_PERCENT __BITS(6,0)
85
86 #define AXP_BATT_CAP_WARN_REG 0xe6
87 #define AXP_BATT_CAP_WARN_LV1 __BITS(7,4)
88 #define AXP_BATT_CAP_WARN_LV2 __BITS(3,0)
89
90 struct axppmic_ctrl {
91 device_t c_dev;
92
93 const char * c_name;
94 u_int c_min;
95 u_int c_max;
96 u_int c_step1;
97 u_int c_step1cnt;
98 u_int c_step2;
99 u_int c_step2cnt;
100
101 uint8_t c_enable_reg;
102 uint8_t c_enable_mask;
103
104 uint8_t c_voltage_reg;
105 uint8_t c_voltage_mask;
106 };
107
108 #define AXP_CTRL(name, min, max, step, ereg, emask, vreg, vmask) \
109 { .c_name = (name), .c_min = (min), .c_max = (max), \
110 .c_step1 = (step), .c_step1cnt = (((max) - (min)) / (step)) + 1, \
111 .c_step2 = 0, .c_step2cnt = 0, \
112 .c_enable_reg = (ereg), .c_enable_mask = (emask), \
113 .c_voltage_reg = (vreg), .c_voltage_mask = (vmask) }
114
115 #define AXP_CTRL2(name, min, max, step1, step1cnt, step2, step2cnt, ereg, emask, vreg, vmask) \
116 { .c_name = (name), .c_min = (min), .c_max = (max), \
117 .c_step1 = (step1), .c_step1cnt = (step1cnt), \
118 .c_step2 = (step2), .c_step2cnt = (step2cnt), \
119 .c_enable_reg = (ereg), .c_enable_mask = (emask), \
120 .c_voltage_reg = (vreg), .c_voltage_mask = (vmask) }
121
122 static const struct axppmic_ctrl axp803_ctrls[] = {
123 AXP_CTRL("dldo1", 700, 3300, 100,
124 0x12, __BIT(3), 0x15, __BITS(4,0)),
125 AXP_CTRL2("dldo2", 700, 4200, 100, 28, 200, 4,
126 0x12, __BIT(4), 0x16, __BITS(4,0)),
127 AXP_CTRL("dldo3", 700, 3300, 100,
128 0x12, __BIT(5), 0x17, __BITS(4,0)),
129 AXP_CTRL("dldo4", 700, 3300, 100,
130 0x12, __BIT(6), 0x18, __BITS(4,0)),
131 AXP_CTRL("eldo1", 700, 1900, 50,
132 0x12, __BIT(0), 0x19, __BITS(4,0)),
133 AXP_CTRL("eldo2", 700, 1900, 50,
134 0x12, __BIT(1), 0x1a, __BITS(4,0)),
135 AXP_CTRL("eldo3", 700, 1900, 50,
136 0x12, __BIT(2), 0x1b, __BITS(4,0)),
137 AXP_CTRL("fldo1", 700, 1450, 50,
138 0x13, __BIT(2), 0x1c, __BITS(3,0)),
139 AXP_CTRL("fldo2", 700, 1450, 50,
140 0x13, __BIT(3), 0x1d, __BITS(3,0)),
141 AXP_CTRL("dcdc1", 1600, 3400, 100,
142 0x10, __BIT(0), 0x20, __BITS(4,0)),
143 AXP_CTRL2("dcdc2", 500, 1300, 10, 70, 20, 5,
144 0x10, __BIT(1), 0x21, __BITS(6,0)),
145 AXP_CTRL2("dcdc3", 500, 1300, 10, 70, 20, 5,
146 0x10, __BIT(2), 0x22, __BITS(6,0)),
147 AXP_CTRL2("dcdc4", 500, 1300, 10, 70, 20, 5,
148 0x10, __BIT(3), 0x23, __BITS(6,0)),
149 AXP_CTRL2("dcdc5", 800, 1840, 10, 33, 20, 36,
150 0x10, __BIT(4), 0x24, __BITS(6,0)),
151 AXP_CTRL2("dcdc6", 600, 1520, 10, 51, 20, 21,
152 0x10, __BIT(5), 0x25, __BITS(6,0)),
153 AXP_CTRL("aldo1", 700, 3300, 100,
154 0x13, __BIT(5), 0x28, __BITS(4,0)),
155 AXP_CTRL("aldo2", 700, 3300, 100,
156 0x13, __BIT(6), 0x29, __BITS(4,0)),
157 AXP_CTRL("aldo3", 700, 3300, 100,
158 0x13, __BIT(7), 0x2a, __BITS(4,0)),
159 };
160
161 static const struct axppmic_ctrl axp805_ctrls[] = {
162 AXP_CTRL2("dcdca", 600, 1520, 10, 51, 20, 21,
163 0x10, __BIT(0), 0x12, __BITS(6,0)),
164 AXP_CTRL("dcdcb", 1000, 2550, 50,
165 0x10, __BIT(1), 0x13, __BITS(4,0)),
166 AXP_CTRL2("dcdcc", 600, 1520, 10, 51, 20, 21,
167 0x10, __BIT(2), 0x14, __BITS(6,0)),
168 AXP_CTRL2("dcdcd", 600, 3300, 20, 46, 100, 18,
169 0x10, __BIT(3), 0x15, __BITS(5,0)),
170 AXP_CTRL("dcdce", 1100, 3400, 100,
171 0x10, __BIT(4), 0x16, __BITS(4,0)),
172 AXP_CTRL("aldo1", 700, 3300, 100,
173 0x10, __BIT(5), 0x17, __BITS(4,0)),
174 AXP_CTRL("aldo2", 700, 3400, 100,
175 0x10, __BIT(6), 0x18, __BITS(4,0)),
176 AXP_CTRL("aldo3", 700, 3300, 100,
177 0x10, __BIT(7), 0x19, __BITS(4,0)),
178 AXP_CTRL("bldo1", 700, 1900, 100,
179 0x11, __BIT(0), 0x20, __BITS(3,0)),
180 AXP_CTRL("bldo2", 700, 1900, 100,
181 0x11, __BIT(1), 0x21, __BITS(3,0)),
182 AXP_CTRL("bldo3", 700, 1900, 100,
183 0x11, __BIT(2), 0x22, __BITS(3,0)),
184 AXP_CTRL("bldo4", 700, 1900, 100,
185 0x11, __BIT(3), 0x23, __BITS(3,0)),
186 AXP_CTRL("cldo1", 700, 3300, 100,
187 0x11, __BIT(4), 0x24, __BITS(4,0)),
188 AXP_CTRL2("cldo2", 700, 4200, 100, 28, 200, 4,
189 0x11, __BIT(5), 0x25, __BITS(4,0)),
190 AXP_CTRL("cldo3", 700, 3300, 100,
191 0x11, __BIT(6), 0x26, __BITS(4,0)),
192 };
193
194 struct axppmic_irq {
195 u_int reg;
196 uint8_t mask;
197 };
198
199 #define AXPPMIC_IRQ(_reg, _mask) \
200 { .reg = (_reg), .mask = (_mask) }
201
202 struct axppmic_config {
203 const char *name;
204 const struct axppmic_ctrl *controls;
205 u_int ncontrols;
206 u_int irq_regs;
207 bool has_battery;
208 bool has_fuel_gauge;
209 struct axppmic_irq poklirq;
210 struct axppmic_irq acinirq;
211 struct axppmic_irq vbusirq;
212 struct axppmic_irq battirq;
213 struct axppmic_irq chargeirq;
214 struct axppmic_irq chargestirq;
215 u_int batsense_step; /* uV */
216 u_int charge_step; /* uA */
217 u_int discharge_step; /* uA */
218 u_int maxcap_step; /* uAh */
219 u_int coulomb_step; /* uAh */
220 };
221
222 enum axppmic_sensor {
223 AXP_SENSOR_ACIN_PRESENT,
224 AXP_SENSOR_VBUS_PRESENT,
225 AXP_SENSOR_BATT_PRESENT,
226 AXP_SENSOR_BATT_CHARGING,
227 AXP_SENSOR_BATT_CHARGE_STATE,
228 AXP_SENSOR_BATT_VOLTAGE,
229 AXP_SENSOR_BATT_CHARGE_CURRENT,
230 AXP_SENSOR_BATT_DISCHARGE_CURRENT,
231 AXP_SENSOR_BATT_CAPACITY_PERCENT,
232 AXP_NSENSORS
233 };
234
235 struct axppmic_softc {
236 device_t sc_dev;
237 i2c_tag_t sc_i2c;
238 i2c_addr_t sc_addr;
239 int sc_phandle;
240
241 const struct axppmic_config *sc_conf;
242
243 struct sysmon_pswitch sc_smpsw;
244
245 struct sysmon_envsys *sc_sme;
246
247 envsys_data_t sc_sensor[AXP_NSENSORS];
248
249 u_int sc_warn_thres;
250 u_int sc_shut_thres;
251 };
252
253 struct axpreg_softc {
254 device_t sc_dev;
255 i2c_tag_t sc_i2c;
256 i2c_addr_t sc_addr;
257 const struct axppmic_ctrl *sc_ctrl;
258 };
259
260 struct axpreg_attach_args {
261 const struct axppmic_ctrl *reg_ctrl;
262 int reg_phandle;
263 i2c_tag_t reg_i2c;
264 i2c_addr_t reg_addr;
265 };
266
267 static const char *axp803_compatstrings[] = { "x-powers,axp803", NULL };
268 static const struct axppmic_config axp803_config = {
269 .name = "AXP803",
270 .controls = axp803_ctrls,
271 .ncontrols = __arraycount(axp803_ctrls),
272 .irq_regs = 6,
273 .has_battery = true,
274 .has_fuel_gauge = true,
275 .batsense_step = 1100,
276 .charge_step = 1000,
277 .discharge_step = 1000,
278 .poklirq = AXPPMIC_IRQ(5, __BIT(3)),
279 .acinirq = AXPPMIC_IRQ(1, __BITS(6,5)),
280 .vbusirq = AXPPMIC_IRQ(1, __BITS(3,2)),
281 .battirq = AXPPMIC_IRQ(2, __BITS(7,6)),
282 .chargeirq = AXPPMIC_IRQ(2, __BITS(3,2)),
283 .chargestirq = AXPPMIC_IRQ(4, __BITS(1,0)),
284 };
285
286 static const char *axp805_compatstrings[] = { "x-powers,axp805",
287 "x-powers,axp806", NULL };
288 static const struct axppmic_config axp805_config = {
289 .name = "AXP805/806",
290 .controls = axp805_ctrls,
291 .ncontrols = __arraycount(axp805_ctrls),
292 .irq_regs = 2,
293 .poklirq = AXPPMIC_IRQ(2, __BIT(0)),
294 };
295
296 static const struct device_compatible_entry axppmic_compat_data[] = {
297 DEVICE_COMPAT_ENTRY_WITH_DATA(axp803_compatstrings, &axp803_config),
298 DEVICE_COMPAT_ENTRY_WITH_DATA(axp805_compatstrings, &axp805_config),
299 DEVICE_COMPAT_TERMINATOR
300 };
301
302 static int
303 axppmic_read(i2c_tag_t tag, i2c_addr_t addr, uint8_t reg, uint8_t *val, int flags)
304 {
305 return iic_smbus_read_byte(tag, addr, reg, val, flags);
306 }
307
308 static int
309 axppmic_write(i2c_tag_t tag, i2c_addr_t addr, uint8_t reg, uint8_t val, int flags)
310 {
311 return iic_smbus_write_byte(tag, addr, reg, val, flags);
312 }
313
314 static int
315 axppmic_set_voltage(i2c_tag_t tag, i2c_addr_t addr, const struct axppmic_ctrl *c, u_int min, u_int max)
316 {
317 const int flags = (cold ? I2C_F_POLL : 0);
318 u_int vol, reg_val;
319 int nstep, error;
320 uint8_t val;
321
322 if (!c->c_voltage_mask)
323 return EINVAL;
324
325 if (min < c->c_min || min > c->c_max)
326 return EINVAL;
327
328 reg_val = 0;
329 nstep = 1;
330 vol = c->c_min;
331
332 for (nstep = 0; nstep < c->c_step1cnt && vol < min; nstep++) {
333 ++reg_val;
334 vol += c->c_step1;
335 }
336 for (nstep = 0; nstep < c->c_step2cnt && vol < min; nstep++) {
337 ++reg_val;
338 vol += c->c_step2;
339 }
340
341 if (vol > max)
342 return EINVAL;
343
344 iic_acquire_bus(tag, flags);
345 if ((error = axppmic_read(tag, addr, c->c_voltage_reg, &val, flags)) == 0) {
346 val &= ~c->c_voltage_mask;
347 val |= __SHIFTIN(reg_val, c->c_voltage_mask);
348 error = axppmic_write(tag, addr, c->c_voltage_reg, val, flags);
349 }
350 iic_release_bus(tag, flags);
351
352 return error;
353 }
354
355 static int
356 axppmic_get_voltage(i2c_tag_t tag, i2c_addr_t addr, const struct axppmic_ctrl *c, u_int *pvol)
357 {
358 const int flags = (cold ? I2C_F_POLL : 0);
359 int reg_val, error;
360 uint8_t val;
361
362 if (!c->c_voltage_mask)
363 return EINVAL;
364
365 iic_acquire_bus(tag, flags);
366 error = axppmic_read(tag, addr, c->c_voltage_reg, &val, flags);
367 iic_release_bus(tag, flags);
368 if (error)
369 return error;
370
371 reg_val = __SHIFTOUT(val, c->c_voltage_mask);
372 if (reg_val < c->c_step1cnt) {
373 *pvol = c->c_min + reg_val * c->c_step1;
374 } else {
375 *pvol = c->c_min + (c->c_step1cnt * c->c_step1) +
376 ((reg_val - c->c_step1cnt) * c->c_step2);
377 }
378
379 return 0;
380 }
381
382 static void
383 axppmic_power_poweroff(device_t dev)
384 {
385 struct axppmic_softc *sc = device_private(dev);
386
387 delay(1000000);
388
389 iic_acquire_bus(sc->sc_i2c, I2C_F_POLL);
390 axppmic_write(sc->sc_i2c, sc->sc_addr, AXP_POWER_DISABLE_REG, AXP_POWER_DISABLE_CTRL, I2C_F_POLL);
391 iic_release_bus(sc->sc_i2c, I2C_F_POLL);
392 }
393
394 static struct fdtbus_power_controller_func axppmic_power_funcs = {
395 .poweroff = axppmic_power_poweroff,
396 };
397
398 static void
399 axppmic_task_shut(void *priv)
400 {
401 struct axppmic_softc *sc = priv;
402
403 sysmon_pswitch_event(&sc->sc_smpsw, PSWITCH_EVENT_PRESSED);
404 }
405
406 static void
407 axppmic_sensor_update(struct sysmon_envsys *sme, envsys_data_t *e)
408 {
409 struct axppmic_softc *sc = sme->sme_cookie;
410 const struct axppmic_config *c = sc->sc_conf;
411 const int flags = I2C_F_POLL;
412 uint8_t val, lo, hi;
413
414 e->state = ENVSYS_SINVALID;
415
416 const bool battery_present =
417 sc->sc_sensor[AXP_SENSOR_BATT_PRESENT].state == ENVSYS_SVALID &&
418 sc->sc_sensor[AXP_SENSOR_BATT_PRESENT].value_cur == 1;
419
420 switch (e->private) {
421 case AXP_SENSOR_ACIN_PRESENT:
422 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_SOURCE_REG, &val, flags) == 0) {
423 e->state = ENVSYS_SVALID;
424 e->value_cur = !!(val & AXP_POWER_SOURCE_ACIN_PRESENT);
425 }
426 break;
427 case AXP_SENSOR_VBUS_PRESENT:
428 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_SOURCE_REG, &val, flags) == 0) {
429 e->state = ENVSYS_SVALID;
430 e->value_cur = !!(val & AXP_POWER_SOURCE_VBUS_PRESENT);
431 }
432 break;
433 case AXP_SENSOR_BATT_PRESENT:
434 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_MODE_REG, &val, flags) == 0) {
435 if (val & AXP_POWER_MODE_BATT_VALID) {
436 e->state = ENVSYS_SVALID;
437 e->value_cur = !!(val & AXP_POWER_MODE_BATT_PRESENT);
438 }
439 }
440 break;
441 case AXP_SENSOR_BATT_CHARGING:
442 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_MODE_REG, &val, flags) == 0) {
443 e->state = ENVSYS_SVALID;
444 e->value_cur = !!(val & AXP_POWER_MODE_BATT_CHARGING);
445 }
446 break;
447 case AXP_SENSOR_BATT_CHARGE_STATE:
448 if (battery_present &&
449 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_CAP_REG, &val, flags) == 0 &&
450 (val & AXP_BATT_CAP_VALID) != 0) {
451 const u_int batt_val = __SHIFTOUT(val, AXP_BATT_CAP_PERCENT);
452 if (batt_val <= sc->sc_shut_thres) {
453 e->state = ENVSYS_SCRITICAL;
454 e->value_cur = ENVSYS_BATTERY_CAPACITY_CRITICAL;
455 } else if (batt_val <= sc->sc_warn_thres) {
456 e->state = ENVSYS_SWARNUNDER;
457 e->value_cur = ENVSYS_BATTERY_CAPACITY_WARNING;
458 } else {
459 e->state = ENVSYS_SVALID;
460 e->value_cur = ENVSYS_BATTERY_CAPACITY_NORMAL;
461 }
462 }
463 break;
464 case AXP_SENSOR_BATT_CAPACITY_PERCENT:
465 if (battery_present &&
466 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_CAP_REG, &val, flags) == 0 &&
467 (val & AXP_BATT_CAP_VALID) != 0) {
468 e->state = ENVSYS_SVALID;
469 e->value_cur = __SHIFTOUT(val, AXP_BATT_CAP_PERCENT);
470 }
471 break;
472 case AXP_SENSOR_BATT_VOLTAGE:
473 if (battery_present &&
474 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATSENSE_HI_REG, &hi, flags) == 0 &&
475 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATSENSE_LO_REG, &lo, flags) == 0) {
476 e->state = ENVSYS_SVALID;
477 e->value_cur = AXP_ADC_RAW(hi, lo) * c->batsense_step;
478 }
479 break;
480 case AXP_SENSOR_BATT_CHARGE_CURRENT:
481 if (battery_present &&
482 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_SOURCE_REG, &val, flags) == 0 &&
483 (val & AXP_POWER_SOURCE_CHARGE_DIRECTION) != 0 &&
484 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATTCHG_HI_REG, &hi, flags) == 0 &&
485 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATTCHG_LO_REG, &lo, flags) == 0) {
486 e->state = ENVSYS_SVALID;
487 e->value_cur = AXP_ADC_RAW(hi, lo) * c->charge_step;
488 }
489 break;
490 case AXP_SENSOR_BATT_DISCHARGE_CURRENT:
491 if (battery_present &&
492 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_SOURCE_REG, &val, flags) == 0 &&
493 (val & AXP_POWER_SOURCE_CHARGE_DIRECTION) == 0 &&
494 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATTDISCHG_HI_REG, &hi, flags) == 0 &&
495 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATTDISCHG_LO_REG, &lo, flags) == 0) {
496 e->state = ENVSYS_SVALID;
497 e->value_cur = AXP_ADC_RAW(hi, lo) * c->discharge_step;
498 }
499 break;
500 }
501 }
502
503 static void
504 axppmic_sensor_refresh(struct sysmon_envsys *sme, envsys_data_t *e)
505 {
506 struct axppmic_softc *sc = sme->sme_cookie;
507 const int flags = I2C_F_POLL;
508
509 switch (e->private) {
510 case AXP_SENSOR_BATT_CAPACITY_PERCENT:
511 case AXP_SENSOR_BATT_VOLTAGE:
512 case AXP_SENSOR_BATT_CHARGE_CURRENT:
513 case AXP_SENSOR_BATT_DISCHARGE_CURRENT:
514 /* Always update battery capacity and ADCs */
515 iic_acquire_bus(sc->sc_i2c, flags);
516 axppmic_sensor_update(sme, e);
517 iic_release_bus(sc->sc_i2c, flags);
518 break;
519 default:
520 /* Refresh if the sensor is not in valid state */
521 if (e->state != ENVSYS_SVALID) {
522 iic_acquire_bus(sc->sc_i2c, flags);
523 axppmic_sensor_update(sme, e);
524 iic_release_bus(sc->sc_i2c, flags);
525 }
526 break;
527 }
528 }
529
530 static int
531 axppmic_intr(void *priv)
532 {
533 struct axppmic_softc *sc = priv;
534 const struct axppmic_config *c = sc->sc_conf;
535 const int flags = I2C_F_POLL;
536 uint8_t stat;
537 u_int n;
538
539 iic_acquire_bus(sc->sc_i2c, flags);
540 for (n = 1; n <= c->irq_regs; n++) {
541 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_IRQ_STATUS_REG(n), &stat, flags) == 0) {
542 if (n == c->poklirq.reg && (stat & c->poklirq.mask) != 0)
543 sysmon_task_queue_sched(0, axppmic_task_shut, sc);
544 if (n == c->acinirq.reg && (stat & c->acinirq.mask) != 0)
545 axppmic_sensor_update(sc->sc_sme, &sc->sc_sensor[AXP_SENSOR_ACIN_PRESENT]);
546 if (n == c->vbusirq.reg && (stat & c->vbusirq.mask) != 0)
547 axppmic_sensor_update(sc->sc_sme, &sc->sc_sensor[AXP_SENSOR_VBUS_PRESENT]);
548 if (n == c->battirq.reg && (stat & c->battirq.mask) != 0)
549 axppmic_sensor_update(sc->sc_sme, &sc->sc_sensor[AXP_SENSOR_BATT_PRESENT]);
550 if (n == c->chargeirq.reg && (stat & c->chargeirq.mask) != 0)
551 axppmic_sensor_update(sc->sc_sme, &sc->sc_sensor[AXP_SENSOR_BATT_CHARGING]);
552 if (n == c->chargestirq.reg && (stat & c->chargestirq.mask) != 0)
553 axppmic_sensor_update(sc->sc_sme, &sc->sc_sensor[AXP_SENSOR_BATT_CHARGE_STATE]);
554
555 if (stat != 0)
556 axppmic_write(sc->sc_i2c, sc->sc_addr,
557 AXP_IRQ_STATUS_REG(n), stat, flags);
558 }
559 }
560 iic_release_bus(sc->sc_i2c, flags);
561
562 return 1;
563 }
564
565 static void
566 axppmic_attach_acadapter(struct axppmic_softc *sc)
567 {
568 envsys_data_t *e;
569
570 e = &sc->sc_sensor[AXP_SENSOR_ACIN_PRESENT];
571 e->private = AXP_SENSOR_ACIN_PRESENT;
572 e->units = ENVSYS_INDICATOR;
573 e->state = ENVSYS_SINVALID;
574 strlcpy(e->desc, "ACIN present", sizeof(e->desc));
575 sysmon_envsys_sensor_attach(sc->sc_sme, e);
576
577 e = &sc->sc_sensor[AXP_SENSOR_VBUS_PRESENT];
578 e->private = AXP_SENSOR_VBUS_PRESENT;
579 e->units = ENVSYS_INDICATOR;
580 e->state = ENVSYS_SINVALID;
581 strlcpy(e->desc, "VBUS present", sizeof(e->desc));
582 sysmon_envsys_sensor_attach(sc->sc_sme, e);
583 }
584
585 static void
586 axppmic_attach_battery(struct axppmic_softc *sc)
587 {
588 const struct axppmic_config *c = sc->sc_conf;
589 envsys_data_t *e;
590 uint8_t val;
591
592 iic_acquire_bus(sc->sc_i2c, I2C_F_POLL);
593 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_CAP_WARN_REG, &val, I2C_F_POLL) == 0) {
594 sc->sc_warn_thres = __SHIFTOUT(val, AXP_BATT_CAP_WARN_LV1) + 5;
595 sc->sc_shut_thres = __SHIFTOUT(val, AXP_BATT_CAP_WARN_LV2);
596 }
597 iic_release_bus(sc->sc_i2c, I2C_F_POLL);
598
599 e = &sc->sc_sensor[AXP_SENSOR_BATT_PRESENT];
600 e->private = AXP_SENSOR_BATT_PRESENT;
601 e->units = ENVSYS_INDICATOR;
602 e->state = ENVSYS_SINVALID;
603 strlcpy(e->desc, "battery present", sizeof(e->desc));
604 sysmon_envsys_sensor_attach(sc->sc_sme, e);
605
606 e = &sc->sc_sensor[AXP_SENSOR_BATT_CHARGING];
607 e->private = AXP_SENSOR_BATT_CHARGING;
608 e->units = ENVSYS_BATTERY_CHARGE;
609 e->state = ENVSYS_SINVALID;
610 strlcpy(e->desc, "charging", sizeof(e->desc));
611 sysmon_envsys_sensor_attach(sc->sc_sme, e);
612
613 e = &sc->sc_sensor[AXP_SENSOR_BATT_CHARGE_STATE];
614 e->private = AXP_SENSOR_BATT_CHARGE_STATE;
615 e->units = ENVSYS_BATTERY_CAPACITY;
616 e->flags = ENVSYS_FMONSTCHANGED;
617 e->state = ENVSYS_SINVALID;
618 e->value_cur = ENVSYS_BATTERY_CAPACITY_NORMAL;
619 strlcpy(e->desc, "charge state", sizeof(e->desc));
620 sysmon_envsys_sensor_attach(sc->sc_sme, e);
621
622 if (c->batsense_step) {
623 e = &sc->sc_sensor[AXP_SENSOR_BATT_VOLTAGE];
624 e->private = AXP_SENSOR_BATT_VOLTAGE;
625 e->units = ENVSYS_SVOLTS_DC;
626 e->state = ENVSYS_SINVALID;
627 strlcpy(e->desc, "battery voltage", sizeof(e->desc));
628 sysmon_envsys_sensor_attach(sc->sc_sme, e);
629 }
630
631 if (c->charge_step) {
632 e = &sc->sc_sensor[AXP_SENSOR_BATT_CHARGE_CURRENT];
633 e->private = AXP_SENSOR_BATT_CHARGE_CURRENT;
634 e->units = ENVSYS_SAMPS;
635 e->state = ENVSYS_SINVALID;
636 strlcpy(e->desc, "battery charge current", sizeof(e->desc));
637 sysmon_envsys_sensor_attach(sc->sc_sme, e);
638 }
639
640 if (c->discharge_step) {
641 e = &sc->sc_sensor[AXP_SENSOR_BATT_DISCHARGE_CURRENT];
642 e->private = AXP_SENSOR_BATT_DISCHARGE_CURRENT;
643 e->units = ENVSYS_SAMPS;
644 e->state = ENVSYS_SINVALID;
645 strlcpy(e->desc, "battery discharge current", sizeof(e->desc));
646 sysmon_envsys_sensor_attach(sc->sc_sme, e);
647 }
648
649 if (c->has_fuel_gauge) {
650 e = &sc->sc_sensor[AXP_SENSOR_BATT_CAPACITY_PERCENT];
651 e->private = AXP_SENSOR_BATT_CAPACITY_PERCENT;
652 e->units = ENVSYS_INTEGER;
653 e->state = ENVSYS_SINVALID;
654 e->flags = ENVSYS_FPERCENT;
655 strlcpy(e->desc, "battery percent", sizeof(e->desc));
656 sysmon_envsys_sensor_attach(sc->sc_sme, e);
657 }
658 }
659
660 static void
661 axppmic_attach_sensors(struct axppmic_softc *sc)
662 {
663 if (sc->sc_conf->has_battery) {
664 sc->sc_sme = sysmon_envsys_create();
665 sc->sc_sme->sme_name = device_xname(sc->sc_dev);
666 sc->sc_sme->sme_cookie = sc;
667 sc->sc_sme->sme_refresh = axppmic_sensor_refresh;
668 sc->sc_sme->sme_class = SME_CLASS_BATTERY;
669 sc->sc_sme->sme_flags = SME_INIT_REFRESH;
670
671 axppmic_attach_acadapter(sc);
672 axppmic_attach_battery(sc);
673
674 sysmon_envsys_register(sc->sc_sme);
675 }
676 }
677
678
679 static int
680 axppmic_match(device_t parent, cfdata_t match, void *aux)
681 {
682 struct i2c_attach_args *ia = aux;
683 int match_result;
684
685 if (iic_use_direct_match(ia, match, axppmic_compat_data, &match_result))
686 return match_result;
687
688 /* This device is direct-config only. */
689
690 return 0;
691 }
692
693 static void
694 axppmic_attach(device_t parent, device_t self, void *aux)
695 {
696 struct axppmic_softc *sc = device_private(self);
697 const struct device_compatible_entry *dce;
698 const struct axppmic_config *c;
699 struct axpreg_attach_args aaa;
700 struct i2c_attach_args *ia = aux;
701 int phandle, child, i;
702 uint32_t irq_mask;
703 void *ih;
704
705 dce = iic_compatible_match(ia, axppmic_compat_data, NULL);
706 KASSERT(dce != NULL);
707 c = DEVICE_COMPAT_ENTRY_GET_PTR(dce);
708
709 sc->sc_dev = self;
710 sc->sc_i2c = ia->ia_tag;
711 sc->sc_addr = ia->ia_addr;
712 sc->sc_phandle = ia->ia_cookie;
713 sc->sc_conf = c;
714
715 aprint_naive("\n");
716 aprint_normal(": %s\n", c->name);
717
718 sc->sc_smpsw.smpsw_name = device_xname(self);
719 sc->sc_smpsw.smpsw_type = PSWITCH_TYPE_POWER;
720 sysmon_pswitch_register(&sc->sc_smpsw);
721
722 iic_acquire_bus(sc->sc_i2c, I2C_F_POLL);
723 for (i = 1; i <= c->irq_regs; i++) {
724 irq_mask = 0;
725 if (i == c->poklirq.reg)
726 irq_mask |= c->poklirq.mask;
727 if (i == c->acinirq.reg)
728 irq_mask |= c->acinirq.mask;
729 if (i == c->vbusirq.reg)
730 irq_mask |= c->vbusirq.mask;
731 if (i == c->battirq.reg)
732 irq_mask |= c->battirq.mask;
733 if (i == c->chargeirq.reg)
734 irq_mask |= c->chargeirq.mask;
735 if (i == c->chargestirq.reg)
736 irq_mask |= c->chargestirq.mask;
737 axppmic_write(sc->sc_i2c, sc->sc_addr, AXP_IRQ_ENABLE_REG(i), irq_mask, I2C_F_POLL);
738 }
739 iic_release_bus(sc->sc_i2c, I2C_F_POLL);
740
741 ih = fdtbus_intr_establish(sc->sc_phandle, 0, IPL_VM, FDT_INTR_MPSAFE,
742 axppmic_intr, sc);
743 if (ih == NULL) {
744 aprint_error_dev(self, "WARNING: couldn't establish interrupt handler\n");
745 }
746
747 fdtbus_register_power_controller(sc->sc_dev, sc->sc_phandle,
748 &axppmic_power_funcs);
749
750 phandle = of_find_firstchild_byname(sc->sc_phandle, "regulators");
751 if (phandle > 0) {
752 aaa.reg_i2c = sc->sc_i2c;
753 aaa.reg_addr = sc->sc_addr;
754 for (i = 0; i < c->ncontrols; i++) {
755 const struct axppmic_ctrl *ctrl = &c->controls[i];
756 child = of_find_firstchild_byname(phandle, ctrl->c_name);
757 if (child <= 0)
758 continue;
759 aaa.reg_ctrl = ctrl;
760 aaa.reg_phandle = child;
761 config_found(sc->sc_dev, &aaa, NULL);
762 }
763 }
764
765 if (c->has_battery)
766 axppmic_attach_sensors(sc);
767 }
768
769 static int
770 axpreg_acquire(device_t dev)
771 {
772 return 0;
773 }
774
775 static void
776 axpreg_release(device_t dev)
777 {
778 }
779
780 static int
781 axpreg_enable(device_t dev, bool enable)
782 {
783 struct axpreg_softc *sc = device_private(dev);
784 const struct axppmic_ctrl *c = sc->sc_ctrl;
785 const int flags = (cold ? I2C_F_POLL : 0);
786 uint8_t val;
787 int error;
788
789 if (!c->c_enable_mask)
790 return EINVAL;
791
792 iic_acquire_bus(sc->sc_i2c, flags);
793 if ((error = axppmic_read(sc->sc_i2c, sc->sc_addr, c->c_enable_reg, &val, flags)) == 0) {
794 if (enable)
795 val |= c->c_enable_mask;
796 else
797 val &= ~c->c_enable_mask;
798 error = axppmic_write(sc->sc_i2c, sc->sc_addr, c->c_enable_reg, val, flags);
799 }
800 iic_release_bus(sc->sc_i2c, flags);
801
802 return error;
803 }
804
805 static int
806 axpreg_set_voltage(device_t dev, u_int min_uvol, u_int max_uvol)
807 {
808 struct axpreg_softc *sc = device_private(dev);
809 const struct axppmic_ctrl *c = sc->sc_ctrl;
810
811 return axppmic_set_voltage(sc->sc_i2c, sc->sc_addr, c,
812 min_uvol / 1000, max_uvol / 1000);
813 }
814
815 static int
816 axpreg_get_voltage(device_t dev, u_int *puvol)
817 {
818 struct axpreg_softc *sc = device_private(dev);
819 const struct axppmic_ctrl *c = sc->sc_ctrl;
820 int error;
821 u_int vol;
822
823 error = axppmic_get_voltage(sc->sc_i2c, sc->sc_addr, c, &vol);
824 if (error)
825 return error;
826
827 *puvol = vol * 1000;
828 return 0;
829 }
830
831 static struct fdtbus_regulator_controller_func axpreg_funcs = {
832 .acquire = axpreg_acquire,
833 .release = axpreg_release,
834 .enable = axpreg_enable,
835 .set_voltage = axpreg_set_voltage,
836 .get_voltage = axpreg_get_voltage,
837 };
838
839 static int
840 axpreg_match(device_t parent, cfdata_t match, void *aux)
841 {
842 return 1;
843 }
844
845 static void
846 axpreg_attach(device_t parent, device_t self, void *aux)
847 {
848 struct axpreg_softc *sc = device_private(self);
849 struct axpreg_attach_args *aaa = aux;
850 const int phandle = aaa->reg_phandle;
851 const char *name;
852
853 sc->sc_dev = self;
854 sc->sc_i2c = aaa->reg_i2c;
855 sc->sc_addr = aaa->reg_addr;
856 sc->sc_ctrl = aaa->reg_ctrl;
857
858 fdtbus_register_regulator_controller(self, phandle,
859 &axpreg_funcs);
860
861 aprint_naive("\n");
862 name = fdtbus_get_string(phandle, "regulator-name");
863 if (name)
864 aprint_normal(": %s\n", name);
865 else
866 aprint_normal("\n");
867 }
868
869 CFATTACH_DECL_NEW(axppmic, sizeof(struct axppmic_softc),
870 axppmic_match, axppmic_attach, NULL, NULL);
871
872 CFATTACH_DECL_NEW(axpreg, sizeof(struct axpreg_softc),
873 axpreg_match, axpreg_attach, NULL, NULL);
874