axppmic.c revision 1.9.2.6
1 /* $NetBSD: axppmic.c,v 1.9.2.6 2019/01/18 08:50:26 pgoyette Exp $ */ 2 3 /*- 4 * Copyright (c) 2014-2018 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: axppmic.c,v 1.9.2.6 2019/01/18 08:50:26 pgoyette Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/device.h> 36 #include <sys/conf.h> 37 #include <sys/bus.h> 38 #include <sys/kmem.h> 39 40 #include <dev/i2c/i2cvar.h> 41 42 #include <dev/sysmon/sysmonvar.h> 43 #include <dev/sysmon/sysmon_taskq.h> 44 45 #include <dev/fdt/fdtvar.h> 46 47 #define AXP_POWER_SOURCE_REG 0x00 48 #define AXP_POWER_SOURCE_ACIN_PRESENT __BIT(7) 49 #define AXP_POWER_SOURCE_VBUS_PRESENT __BIT(5) 50 #define AXP_POWER_SOURCE_CHARGE_DIRECTION __BIT(2) 51 52 #define AXP_POWER_MODE_REG 0x01 53 #define AXP_POWER_MODE_BATT_VALID __BIT(4) 54 #define AXP_POWER_MODE_BATT_PRESENT __BIT(5) 55 #define AXP_POWER_MODE_BATT_CHARGING __BIT(6) 56 57 #define AXP_POWER_DISABLE_REG 0x32 58 #define AXP_POWER_DISABLE_CTRL __BIT(7) 59 60 #define AXP_IRQ_ENABLE_REG(n) (0x40 + (n) - 1) 61 #define AXP_IRQ1_ACIN_RAISE __BIT(6) 62 #define AXP_IRQ1_ACIN_LOWER __BIT(5) 63 #define AXP_IRQ1_VBUS_RAISE __BIT(3) 64 #define AXP_IRQ1_VBUS_LOWER __BIT(2) 65 #define AXP_IRQ_STATUS_REG(n) (0x48 + (n) - 1) 66 67 #define AXP_BATSENSE_HI_REG 0x78 68 #define AXP_BATSENSE_LO_REG 0x79 69 70 #define AXP_BATTCHG_HI_REG 0x7a 71 #define AXP_BATTCHG_LO_REG 0x7b 72 73 #define AXP_BATTDISCHG_HI_REG 0x7c 74 #define AXP_BATTDISCHG_LO_REG 0x7d 75 76 #define AXP_ADC_RAW(_hi, _lo) \ 77 (((u_int)(_hi) << 4) | ((_lo) & 0xf)) 78 79 #define AXP_FUEL_GAUGE_CTRL_REG 0xb8 80 #define AXP_FUEL_GAUGE_CTRL_EN __BIT(7) 81 82 #define AXP_BATT_CAP_REG 0xb9 83 #define AXP_BATT_CAP_VALID __BIT(7) 84 #define AXP_BATT_CAP_PERCENT __BITS(6,0) 85 86 #define AXP_BATT_MAX_CAP_HI_REG 0xe0 87 #define AXP_BATT_MAX_CAP_VALID __BIT(7) 88 #define AXP_BATT_MAX_CAP_LO_REG 0xe1 89 90 #define AXP_BATT_COULOMB_HI_REG 0xe2 91 #define AXP_BATT_COULOMB_VALID __BIT(7) 92 #define AXP_BATT_COULOMB_LO_REG 0xe3 93 94 #define AXP_COULOMB_RAW(_hi, _lo) \ 95 (((u_int)(_hi & ~__BIT(7)) << 8) | (_lo)) 96 97 #define AXP_BATT_CAP_WARN_REG 0xe6 98 #define AXP_BATT_CAP_WARN_LV1 __BITS(7,4) 99 #define AXP_BATT_CAP_WARN_LV2 __BITS(3,0) 100 101 struct axppmic_ctrl { 102 device_t c_dev; 103 104 const char * c_name; 105 u_int c_min; 106 u_int c_max; 107 u_int c_step1; 108 u_int c_step1cnt; 109 u_int c_step2; 110 u_int c_step2cnt; 111 112 uint8_t c_enable_reg; 113 uint8_t c_enable_mask; 114 115 uint8_t c_voltage_reg; 116 uint8_t c_voltage_mask; 117 }; 118 119 #define AXP_CTRL(name, min, max, step, ereg, emask, vreg, vmask) \ 120 { .c_name = (name), .c_min = (min), .c_max = (max), \ 121 .c_step1 = (step), .c_step1cnt = (((max) - (min)) / (step)) + 1, \ 122 .c_step2 = 0, .c_step2cnt = 0, \ 123 .c_enable_reg = (ereg), .c_enable_mask = (emask), \ 124 .c_voltage_reg = (vreg), .c_voltage_mask = (vmask) } 125 126 #define AXP_CTRL2(name, min, max, step1, step1cnt, step2, step2cnt, ereg, emask, vreg, vmask) \ 127 { .c_name = (name), .c_min = (min), .c_max = (max), \ 128 .c_step1 = (step1), .c_step1cnt = (step1cnt), \ 129 .c_step2 = (step2), .c_step2cnt = (step2cnt), \ 130 .c_enable_reg = (ereg), .c_enable_mask = (emask), \ 131 .c_voltage_reg = (vreg), .c_voltage_mask = (vmask) } 132 133 static const struct axppmic_ctrl axp803_ctrls[] = { 134 AXP_CTRL("dldo1", 700, 3300, 100, 135 0x12, __BIT(3), 0x15, __BITS(4,0)), 136 AXP_CTRL2("dldo2", 700, 4200, 100, 28, 200, 4, 137 0x12, __BIT(4), 0x16, __BITS(4,0)), 138 AXP_CTRL("dldo3", 700, 3300, 100, 139 0x12, __BIT(5), 0x17, __BITS(4,0)), 140 AXP_CTRL("dldo4", 700, 3300, 100, 141 0x12, __BIT(6), 0x18, __BITS(4,0)), 142 AXP_CTRL("eldo1", 700, 1900, 50, 143 0x12, __BIT(0), 0x19, __BITS(4,0)), 144 AXP_CTRL("eldo2", 700, 1900, 50, 145 0x12, __BIT(1), 0x1a, __BITS(4,0)), 146 AXP_CTRL("eldo3", 700, 1900, 50, 147 0x12, __BIT(2), 0x1b, __BITS(4,0)), 148 AXP_CTRL("fldo1", 700, 1450, 50, 149 0x13, __BIT(2), 0x1c, __BITS(3,0)), 150 AXP_CTRL("fldo2", 700, 1450, 50, 151 0x13, __BIT(3), 0x1d, __BITS(3,0)), 152 AXP_CTRL("dcdc1", 1600, 3400, 100, 153 0x10, __BIT(0), 0x20, __BITS(4,0)), 154 AXP_CTRL2("dcdc2", 500, 1300, 10, 70, 20, 5, 155 0x10, __BIT(1), 0x21, __BITS(6,0)), 156 AXP_CTRL2("dcdc3", 500, 1300, 10, 70, 20, 5, 157 0x10, __BIT(2), 0x22, __BITS(6,0)), 158 AXP_CTRL2("dcdc4", 500, 1300, 10, 70, 20, 5, 159 0x10, __BIT(3), 0x23, __BITS(6,0)), 160 AXP_CTRL2("dcdc5", 800, 1840, 10, 33, 20, 36, 161 0x10, __BIT(4), 0x24, __BITS(6,0)), 162 AXP_CTRL2("dcdc6", 600, 1520, 10, 51, 20, 21, 163 0x10, __BIT(5), 0x25, __BITS(6,0)), 164 AXP_CTRL("aldo1", 700, 3300, 100, 165 0x13, __BIT(5), 0x28, __BITS(4,0)), 166 AXP_CTRL("aldo2", 700, 3300, 100, 167 0x13, __BIT(6), 0x29, __BITS(4,0)), 168 AXP_CTRL("aldo3", 700, 3300, 100, 169 0x13, __BIT(7), 0x2a, __BITS(4,0)), 170 }; 171 172 static const struct axppmic_ctrl axp805_ctrls[] = { 173 AXP_CTRL2("dcdca", 600, 1520, 10, 51, 20, 21, 174 0x10, __BIT(0), 0x12, __BITS(6,0)), 175 AXP_CTRL("dcdcb", 1000, 2550, 50, 176 0x10, __BIT(1), 0x13, __BITS(4,0)), 177 AXP_CTRL2("dcdcc", 600, 1520, 10, 51, 20, 21, 178 0x10, __BIT(2), 0x14, __BITS(6,0)), 179 AXP_CTRL2("dcdcd", 600, 3300, 20, 46, 100, 18, 180 0x10, __BIT(3), 0x15, __BITS(5,0)), 181 AXP_CTRL("dcdce", 1100, 3400, 100, 182 0x10, __BIT(4), 0x16, __BITS(4,0)), 183 AXP_CTRL("aldo1", 700, 3300, 100, 184 0x10, __BIT(5), 0x17, __BITS(4,0)), 185 AXP_CTRL("aldo2", 700, 3400, 100, 186 0x10, __BIT(6), 0x18, __BITS(4,0)), 187 AXP_CTRL("aldo3", 700, 3300, 100, 188 0x10, __BIT(7), 0x19, __BITS(4,0)), 189 AXP_CTRL("bldo1", 700, 1900, 100, 190 0x11, __BIT(0), 0x20, __BITS(3,0)), 191 AXP_CTRL("bldo2", 700, 1900, 100, 192 0x11, __BIT(1), 0x21, __BITS(3,0)), 193 AXP_CTRL("bldo3", 700, 1900, 100, 194 0x11, __BIT(2), 0x22, __BITS(3,0)), 195 AXP_CTRL("bldo4", 700, 1900, 100, 196 0x11, __BIT(3), 0x23, __BITS(3,0)), 197 AXP_CTRL("cldo1", 700, 3300, 100, 198 0x11, __BIT(4), 0x24, __BITS(4,0)), 199 AXP_CTRL2("cldo2", 700, 4200, 100, 28, 200, 4, 200 0x11, __BIT(5), 0x25, __BITS(4,0)), 201 AXP_CTRL("cldo3", 700, 3300, 100, 202 0x11, __BIT(6), 0x26, __BITS(4,0)), 203 }; 204 205 static const struct axppmic_ctrl axp813_ctrls[] = { 206 AXP_CTRL("dldo1", 700, 3300, 100, 207 0x12, __BIT(3), 0x15, __BITS(4,0)), 208 AXP_CTRL2("dldo2", 700, 4200, 100, 28, 200, 4, 209 0x12, __BIT(4), 0x16, __BITS(4,0)), 210 AXP_CTRL("dldo3", 700, 3300, 100, 211 0x12, __BIT(5), 0x17, __BITS(4,0)), 212 AXP_CTRL("dldo4", 700, 3300, 100, 213 0x12, __BIT(6), 0x18, __BITS(4,0)), 214 AXP_CTRL("eldo1", 700, 1900, 50, 215 0x12, __BIT(0), 0x19, __BITS(4,0)), 216 AXP_CTRL("eldo2", 700, 1900, 50, 217 0x12, __BIT(1), 0x1a, __BITS(4,0)), 218 AXP_CTRL("eldo3", 700, 1900, 50, 219 0x12, __BIT(2), 0x1b, __BITS(4,0)), 220 AXP_CTRL("fldo1", 700, 1450, 50, 221 0x13, __BIT(2), 0x1c, __BITS(3,0)), 222 AXP_CTRL("fldo2", 700, 1450, 50, 223 0x13, __BIT(3), 0x1d, __BITS(3,0)), 224 AXP_CTRL("dcdc1", 1600, 3400, 100, 225 0x10, __BIT(0), 0x20, __BITS(4,0)), 226 AXP_CTRL2("dcdc2", 500, 1300, 10, 70, 20, 5, 227 0x10, __BIT(1), 0x21, __BITS(6,0)), 228 AXP_CTRL2("dcdc3", 500, 1300, 10, 70, 20, 5, 229 0x10, __BIT(2), 0x22, __BITS(6,0)), 230 AXP_CTRL2("dcdc4", 500, 1300, 10, 70, 20, 5, 231 0x10, __BIT(3), 0x23, __BITS(6,0)), 232 AXP_CTRL2("dcdc5", 800, 1840, 10, 33, 20, 36, 233 0x10, __BIT(4), 0x24, __BITS(6,0)), 234 AXP_CTRL2("dcdc6", 600, 1520, 10, 51, 20, 21, 235 0x10, __BIT(5), 0x25, __BITS(6,0)), 236 AXP_CTRL2("dcdc7", 600, 1520, 10, 51, 20, 21, 237 0x10, __BIT(6), 0x26, __BITS(6,0)), 238 AXP_CTRL("aldo1", 700, 3300, 100, 239 0x13, __BIT(5), 0x28, __BITS(4,0)), 240 AXP_CTRL("aldo2", 700, 3300, 100, 241 0x13, __BIT(6), 0x29, __BITS(4,0)), 242 AXP_CTRL("aldo3", 700, 3300, 100, 243 0x13, __BIT(7), 0x2a, __BITS(4,0)), 244 }; 245 246 struct axppmic_irq { 247 u_int reg; 248 uint8_t mask; 249 }; 250 251 #define AXPPMIC_IRQ(_reg, _mask) \ 252 { .reg = (_reg), .mask = (_mask) } 253 254 struct axppmic_config { 255 const char *name; 256 const struct axppmic_ctrl *controls; 257 u_int ncontrols; 258 u_int irq_regs; 259 bool has_battery; 260 bool has_fuel_gauge; 261 struct axppmic_irq poklirq; 262 struct axppmic_irq acinirq; 263 struct axppmic_irq vbusirq; 264 struct axppmic_irq battirq; 265 struct axppmic_irq chargeirq; 266 struct axppmic_irq chargestirq; 267 u_int batsense_step; /* uV */ 268 u_int charge_step; /* uA */ 269 u_int discharge_step; /* uA */ 270 u_int maxcap_step; /* uAh */ 271 u_int coulomb_step; /* uAh */ 272 }; 273 274 enum axppmic_sensor { 275 AXP_SENSOR_ACIN_PRESENT, 276 AXP_SENSOR_VBUS_PRESENT, 277 AXP_SENSOR_BATT_PRESENT, 278 AXP_SENSOR_BATT_CHARGING, 279 AXP_SENSOR_BATT_CHARGE_STATE, 280 AXP_SENSOR_BATT_VOLTAGE, 281 AXP_SENSOR_BATT_CHARGE_CURRENT, 282 AXP_SENSOR_BATT_DISCHARGE_CURRENT, 283 AXP_SENSOR_BATT_CAPACITY_PERCENT, 284 AXP_SENSOR_BATT_MAXIMUM_CAPACITY, 285 AXP_SENSOR_BATT_CURRENT_CAPACITY, 286 AXP_NSENSORS 287 }; 288 289 struct axppmic_softc { 290 device_t sc_dev; 291 i2c_tag_t sc_i2c; 292 i2c_addr_t sc_addr; 293 int sc_phandle; 294 295 const struct axppmic_config *sc_conf; 296 297 struct sysmon_pswitch sc_smpsw; 298 299 struct sysmon_envsys *sc_sme; 300 301 envsys_data_t sc_sensor[AXP_NSENSORS]; 302 303 u_int sc_warn_thres; 304 u_int sc_shut_thres; 305 }; 306 307 struct axpreg_softc { 308 device_t sc_dev; 309 i2c_tag_t sc_i2c; 310 i2c_addr_t sc_addr; 311 const struct axppmic_ctrl *sc_ctrl; 312 }; 313 314 struct axpreg_attach_args { 315 const struct axppmic_ctrl *reg_ctrl; 316 int reg_phandle; 317 i2c_tag_t reg_i2c; 318 i2c_addr_t reg_addr; 319 }; 320 321 static const struct axppmic_config axp803_config = { 322 .name = "AXP803", 323 .controls = axp803_ctrls, 324 .ncontrols = __arraycount(axp803_ctrls), 325 .irq_regs = 6, 326 .has_battery = true, 327 .has_fuel_gauge = true, 328 .batsense_step = 1100, 329 .charge_step = 1000, 330 .discharge_step = 1000, 331 .maxcap_step = 1456, 332 .coulomb_step = 1456, 333 .poklirq = AXPPMIC_IRQ(5, __BIT(3)), 334 .acinirq = AXPPMIC_IRQ(1, __BITS(6,5)), 335 .vbusirq = AXPPMIC_IRQ(1, __BITS(3,2)), 336 .battirq = AXPPMIC_IRQ(2, __BITS(7,6)), 337 .chargeirq = AXPPMIC_IRQ(2, __BITS(3,2)), 338 .chargestirq = AXPPMIC_IRQ(4, __BITS(1,0)), 339 }; 340 341 static const struct axppmic_config axp805_config = { 342 .name = "AXP805/806", 343 .controls = axp805_ctrls, 344 .ncontrols = __arraycount(axp805_ctrls), 345 .irq_regs = 2, 346 .poklirq = AXPPMIC_IRQ(2, __BIT(0)), 347 }; 348 349 static const struct axppmic_config axp813_config = { 350 .name = "AXP813", 351 .controls = axp813_ctrls, 352 .ncontrols = __arraycount(axp813_ctrls), 353 .irq_regs = 6, 354 .has_battery = true, 355 .has_fuel_gauge = true, 356 .batsense_step = 1100, 357 .charge_step = 1000, 358 .discharge_step = 1000, 359 .maxcap_step = 1456, 360 .coulomb_step = 1456, 361 .poklirq = AXPPMIC_IRQ(5, __BIT(3)), 362 .acinirq = AXPPMIC_IRQ(1, __BITS(6,5)), 363 .vbusirq = AXPPMIC_IRQ(1, __BITS(3,2)), 364 .battirq = AXPPMIC_IRQ(2, __BITS(7,6)), 365 .chargeirq = AXPPMIC_IRQ(2, __BITS(3,2)), 366 .chargestirq = AXPPMIC_IRQ(4, __BITS(1,0)), 367 }; 368 369 static const struct device_compatible_entry compat_data[] = { 370 { "x-powers,axp803", (uintptr_t)&axp803_config }, 371 { "x-powers,axp805", (uintptr_t)&axp805_config }, 372 { "x-powers,axp806", (uintptr_t)&axp805_config }, 373 { "x-powers,axp813", (uintptr_t)&axp813_config }, 374 { NULL, 0 } 375 }; 376 377 static int 378 axppmic_read(i2c_tag_t tag, i2c_addr_t addr, uint8_t reg, uint8_t *val, int flags) 379 { 380 return iic_smbus_read_byte(tag, addr, reg, val, flags); 381 } 382 383 static int 384 axppmic_write(i2c_tag_t tag, i2c_addr_t addr, uint8_t reg, uint8_t val, int flags) 385 { 386 return iic_smbus_write_byte(tag, addr, reg, val, flags); 387 } 388 389 static int 390 axppmic_set_voltage(i2c_tag_t tag, i2c_addr_t addr, const struct axppmic_ctrl *c, u_int min, u_int max) 391 { 392 const int flags = (cold ? I2C_F_POLL : 0); 393 u_int vol, reg_val; 394 int nstep, error; 395 uint8_t val; 396 397 if (!c->c_voltage_mask) 398 return EINVAL; 399 400 if (min < c->c_min || min > c->c_max) 401 return EINVAL; 402 403 reg_val = 0; 404 nstep = 1; 405 vol = c->c_min; 406 407 for (nstep = 0; nstep < c->c_step1cnt && vol < min; nstep++) { 408 ++reg_val; 409 vol += c->c_step1; 410 } 411 for (nstep = 0; nstep < c->c_step2cnt && vol < min; nstep++) { 412 ++reg_val; 413 vol += c->c_step2; 414 } 415 416 if (vol > max) 417 return EINVAL; 418 419 iic_acquire_bus(tag, flags); 420 if ((error = axppmic_read(tag, addr, c->c_voltage_reg, &val, flags)) == 0) { 421 val &= ~c->c_voltage_mask; 422 val |= __SHIFTIN(reg_val, c->c_voltage_mask); 423 error = axppmic_write(tag, addr, c->c_voltage_reg, val, flags); 424 } 425 iic_release_bus(tag, flags); 426 427 return error; 428 } 429 430 static int 431 axppmic_get_voltage(i2c_tag_t tag, i2c_addr_t addr, const struct axppmic_ctrl *c, u_int *pvol) 432 { 433 const int flags = (cold ? I2C_F_POLL : 0); 434 int reg_val, error; 435 uint8_t val; 436 437 if (!c->c_voltage_mask) 438 return EINVAL; 439 440 iic_acquire_bus(tag, flags); 441 error = axppmic_read(tag, addr, c->c_voltage_reg, &val, flags); 442 iic_release_bus(tag, flags); 443 if (error) 444 return error; 445 446 reg_val = __SHIFTOUT(val, c->c_voltage_mask); 447 if (reg_val < c->c_step1cnt) { 448 *pvol = c->c_min + reg_val * c->c_step1; 449 } else { 450 *pvol = c->c_min + (c->c_step1cnt * c->c_step1) + 451 ((reg_val - c->c_step1cnt) * c->c_step2); 452 } 453 454 return 0; 455 } 456 457 static void 458 axppmic_power_poweroff(device_t dev) 459 { 460 struct axppmic_softc *sc = device_private(dev); 461 462 delay(1000000); 463 464 iic_acquire_bus(sc->sc_i2c, I2C_F_POLL); 465 axppmic_write(sc->sc_i2c, sc->sc_addr, AXP_POWER_DISABLE_REG, AXP_POWER_DISABLE_CTRL, I2C_F_POLL); 466 iic_release_bus(sc->sc_i2c, I2C_F_POLL); 467 } 468 469 static struct fdtbus_power_controller_func axppmic_power_funcs = { 470 .poweroff = axppmic_power_poweroff, 471 }; 472 473 static void 474 axppmic_task_shut(void *priv) 475 { 476 struct axppmic_softc *sc = priv; 477 478 sysmon_pswitch_event(&sc->sc_smpsw, PSWITCH_EVENT_PRESSED); 479 } 480 481 static void 482 axppmic_sensor_update(struct sysmon_envsys *sme, envsys_data_t *e) 483 { 484 struct axppmic_softc *sc = sme->sme_cookie; 485 const struct axppmic_config *c = sc->sc_conf; 486 const int flags = I2C_F_POLL; 487 uint8_t val, lo, hi; 488 489 e->state = ENVSYS_SINVALID; 490 491 const bool battery_present = 492 sc->sc_sensor[AXP_SENSOR_BATT_PRESENT].state == ENVSYS_SVALID && 493 sc->sc_sensor[AXP_SENSOR_BATT_PRESENT].value_cur == 1; 494 495 switch (e->private) { 496 case AXP_SENSOR_ACIN_PRESENT: 497 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_SOURCE_REG, &val, flags) == 0) { 498 e->state = ENVSYS_SVALID; 499 e->value_cur = !!(val & AXP_POWER_SOURCE_ACIN_PRESENT); 500 } 501 break; 502 case AXP_SENSOR_VBUS_PRESENT: 503 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_SOURCE_REG, &val, flags) == 0) { 504 e->state = ENVSYS_SVALID; 505 e->value_cur = !!(val & AXP_POWER_SOURCE_VBUS_PRESENT); 506 } 507 break; 508 case AXP_SENSOR_BATT_PRESENT: 509 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_MODE_REG, &val, flags) == 0) { 510 if (val & AXP_POWER_MODE_BATT_VALID) { 511 e->state = ENVSYS_SVALID; 512 e->value_cur = !!(val & AXP_POWER_MODE_BATT_PRESENT); 513 } 514 } 515 break; 516 case AXP_SENSOR_BATT_CHARGING: 517 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_MODE_REG, &val, flags) == 0) { 518 e->state = ENVSYS_SVALID; 519 e->value_cur = !!(val & AXP_POWER_MODE_BATT_CHARGING); 520 } 521 break; 522 case AXP_SENSOR_BATT_CHARGE_STATE: 523 if (battery_present && 524 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_CAP_REG, &val, flags) == 0 && 525 (val & AXP_BATT_CAP_VALID) != 0) { 526 const u_int batt_val = __SHIFTOUT(val, AXP_BATT_CAP_PERCENT); 527 if (batt_val <= sc->sc_shut_thres) { 528 e->state = ENVSYS_SCRITICAL; 529 e->value_cur = ENVSYS_BATTERY_CAPACITY_CRITICAL; 530 } else if (batt_val <= sc->sc_warn_thres) { 531 e->state = ENVSYS_SWARNUNDER; 532 e->value_cur = ENVSYS_BATTERY_CAPACITY_WARNING; 533 } else { 534 e->state = ENVSYS_SVALID; 535 e->value_cur = ENVSYS_BATTERY_CAPACITY_NORMAL; 536 } 537 } 538 break; 539 case AXP_SENSOR_BATT_CAPACITY_PERCENT: 540 if (battery_present && 541 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_CAP_REG, &val, flags) == 0 && 542 (val & AXP_BATT_CAP_VALID) != 0) { 543 e->state = ENVSYS_SVALID; 544 e->value_cur = __SHIFTOUT(val, AXP_BATT_CAP_PERCENT); 545 } 546 break; 547 case AXP_SENSOR_BATT_VOLTAGE: 548 if (battery_present && 549 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATSENSE_HI_REG, &hi, flags) == 0 && 550 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATSENSE_LO_REG, &lo, flags) == 0) { 551 e->state = ENVSYS_SVALID; 552 e->value_cur = AXP_ADC_RAW(hi, lo) * c->batsense_step; 553 } 554 break; 555 case AXP_SENSOR_BATT_CHARGE_CURRENT: 556 if (battery_present && 557 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_SOURCE_REG, &val, flags) == 0 && 558 (val & AXP_POWER_SOURCE_CHARGE_DIRECTION) != 0 && 559 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATTCHG_HI_REG, &hi, flags) == 0 && 560 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATTCHG_LO_REG, &lo, flags) == 0) { 561 e->state = ENVSYS_SVALID; 562 e->value_cur = AXP_ADC_RAW(hi, lo) * c->charge_step; 563 } 564 break; 565 case AXP_SENSOR_BATT_DISCHARGE_CURRENT: 566 if (battery_present && 567 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_POWER_SOURCE_REG, &val, flags) == 0 && 568 (val & AXP_POWER_SOURCE_CHARGE_DIRECTION) == 0 && 569 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATTDISCHG_HI_REG, &hi, flags) == 0 && 570 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATTDISCHG_LO_REG, &lo, flags) == 0) { 571 e->state = ENVSYS_SVALID; 572 e->value_cur = AXP_ADC_RAW(hi, lo) * c->discharge_step; 573 } 574 break; 575 case AXP_SENSOR_BATT_MAXIMUM_CAPACITY: 576 if (battery_present && 577 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_MAX_CAP_HI_REG, &hi, flags) == 0 && 578 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_MAX_CAP_LO_REG, &lo, flags) == 0) { 579 e->state = (hi & AXP_BATT_MAX_CAP_VALID) ? ENVSYS_SVALID : ENVSYS_SINVALID; 580 e->value_cur = AXP_COULOMB_RAW(hi, lo) * c->maxcap_step; 581 } 582 break; 583 case AXP_SENSOR_BATT_CURRENT_CAPACITY: 584 if (battery_present && 585 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_COULOMB_HI_REG, &hi, flags) == 0 && 586 axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_COULOMB_LO_REG, &lo, flags) == 0) { 587 e->state = (hi & AXP_BATT_COULOMB_VALID) ? ENVSYS_SVALID : ENVSYS_SINVALID; 588 e->value_cur = AXP_COULOMB_RAW(hi, lo) * c->coulomb_step; 589 } 590 break; 591 } 592 } 593 594 static void 595 axppmic_sensor_refresh(struct sysmon_envsys *sme, envsys_data_t *e) 596 { 597 struct axppmic_softc *sc = sme->sme_cookie; 598 const int flags = I2C_F_POLL; 599 600 switch (e->private) { 601 case AXP_SENSOR_BATT_CAPACITY_PERCENT: 602 case AXP_SENSOR_BATT_VOLTAGE: 603 case AXP_SENSOR_BATT_CHARGE_CURRENT: 604 case AXP_SENSOR_BATT_DISCHARGE_CURRENT: 605 /* Always update battery capacity and ADCs */ 606 iic_acquire_bus(sc->sc_i2c, flags); 607 axppmic_sensor_update(sme, e); 608 iic_release_bus(sc->sc_i2c, flags); 609 break; 610 default: 611 /* Refresh if the sensor is not in valid state */ 612 if (e->state != ENVSYS_SVALID) { 613 iic_acquire_bus(sc->sc_i2c, flags); 614 axppmic_sensor_update(sme, e); 615 iic_release_bus(sc->sc_i2c, flags); 616 } 617 break; 618 } 619 } 620 621 static int 622 axppmic_intr(void *priv) 623 { 624 struct axppmic_softc *sc = priv; 625 const struct axppmic_config *c = sc->sc_conf; 626 const int flags = I2C_F_POLL; 627 uint8_t stat; 628 u_int n; 629 630 iic_acquire_bus(sc->sc_i2c, flags); 631 for (n = 1; n <= c->irq_regs; n++) { 632 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_IRQ_STATUS_REG(n), &stat, flags) == 0) { 633 if (n == c->poklirq.reg && (stat & c->poklirq.mask) != 0) 634 sysmon_task_queue_sched(0, axppmic_task_shut, sc); 635 if (n == c->acinirq.reg && (stat & c->acinirq.mask) != 0) 636 axppmic_sensor_update(sc->sc_sme, &sc->sc_sensor[AXP_SENSOR_ACIN_PRESENT]); 637 if (n == c->vbusirq.reg && (stat & c->vbusirq.mask) != 0) 638 axppmic_sensor_update(sc->sc_sme, &sc->sc_sensor[AXP_SENSOR_VBUS_PRESENT]); 639 if (n == c->battirq.reg && (stat & c->battirq.mask) != 0) 640 axppmic_sensor_update(sc->sc_sme, &sc->sc_sensor[AXP_SENSOR_BATT_PRESENT]); 641 if (n == c->chargeirq.reg && (stat & c->chargeirq.mask) != 0) 642 axppmic_sensor_update(sc->sc_sme, &sc->sc_sensor[AXP_SENSOR_BATT_CHARGING]); 643 if (n == c->chargestirq.reg && (stat & c->chargestirq.mask) != 0) 644 axppmic_sensor_update(sc->sc_sme, &sc->sc_sensor[AXP_SENSOR_BATT_CHARGE_STATE]); 645 646 if (stat != 0) 647 axppmic_write(sc->sc_i2c, sc->sc_addr, 648 AXP_IRQ_STATUS_REG(n), stat, flags); 649 } 650 } 651 iic_release_bus(sc->sc_i2c, flags); 652 653 return 1; 654 } 655 656 static void 657 axppmic_attach_acadapter(struct axppmic_softc *sc) 658 { 659 envsys_data_t *e; 660 661 e = &sc->sc_sensor[AXP_SENSOR_ACIN_PRESENT]; 662 e->private = AXP_SENSOR_ACIN_PRESENT; 663 e->units = ENVSYS_INDICATOR; 664 e->state = ENVSYS_SINVALID; 665 strlcpy(e->desc, "ACIN present", sizeof(e->desc)); 666 sysmon_envsys_sensor_attach(sc->sc_sme, e); 667 668 e = &sc->sc_sensor[AXP_SENSOR_VBUS_PRESENT]; 669 e->private = AXP_SENSOR_VBUS_PRESENT; 670 e->units = ENVSYS_INDICATOR; 671 e->state = ENVSYS_SINVALID; 672 strlcpy(e->desc, "VBUS present", sizeof(e->desc)); 673 sysmon_envsys_sensor_attach(sc->sc_sme, e); 674 } 675 676 static void 677 axppmic_attach_battery(struct axppmic_softc *sc) 678 { 679 const struct axppmic_config *c = sc->sc_conf; 680 envsys_data_t *e; 681 uint8_t val; 682 683 iic_acquire_bus(sc->sc_i2c, I2C_F_POLL); 684 if (axppmic_read(sc->sc_i2c, sc->sc_addr, AXP_BATT_CAP_WARN_REG, &val, I2C_F_POLL) == 0) { 685 sc->sc_warn_thres = __SHIFTOUT(val, AXP_BATT_CAP_WARN_LV1) + 5; 686 sc->sc_shut_thres = __SHIFTOUT(val, AXP_BATT_CAP_WARN_LV2); 687 } 688 iic_release_bus(sc->sc_i2c, I2C_F_POLL); 689 690 e = &sc->sc_sensor[AXP_SENSOR_BATT_PRESENT]; 691 e->private = AXP_SENSOR_BATT_PRESENT; 692 e->units = ENVSYS_INDICATOR; 693 e->state = ENVSYS_SINVALID; 694 strlcpy(e->desc, "battery present", sizeof(e->desc)); 695 sysmon_envsys_sensor_attach(sc->sc_sme, e); 696 697 e = &sc->sc_sensor[AXP_SENSOR_BATT_CHARGING]; 698 e->private = AXP_SENSOR_BATT_CHARGING; 699 e->units = ENVSYS_BATTERY_CHARGE; 700 e->state = ENVSYS_SINVALID; 701 strlcpy(e->desc, "charging", sizeof(e->desc)); 702 sysmon_envsys_sensor_attach(sc->sc_sme, e); 703 704 e = &sc->sc_sensor[AXP_SENSOR_BATT_CHARGE_STATE]; 705 e->private = AXP_SENSOR_BATT_CHARGE_STATE; 706 e->units = ENVSYS_BATTERY_CAPACITY; 707 e->flags = ENVSYS_FMONSTCHANGED; 708 e->state = ENVSYS_SINVALID; 709 e->value_cur = ENVSYS_BATTERY_CAPACITY_NORMAL; 710 strlcpy(e->desc, "charge state", sizeof(e->desc)); 711 sysmon_envsys_sensor_attach(sc->sc_sme, e); 712 713 if (c->batsense_step) { 714 e = &sc->sc_sensor[AXP_SENSOR_BATT_VOLTAGE]; 715 e->private = AXP_SENSOR_BATT_VOLTAGE; 716 e->units = ENVSYS_SVOLTS_DC; 717 e->state = ENVSYS_SINVALID; 718 strlcpy(e->desc, "battery voltage", sizeof(e->desc)); 719 sysmon_envsys_sensor_attach(sc->sc_sme, e); 720 } 721 722 if (c->charge_step) { 723 e = &sc->sc_sensor[AXP_SENSOR_BATT_CHARGE_CURRENT]; 724 e->private = AXP_SENSOR_BATT_CHARGE_CURRENT; 725 e->units = ENVSYS_SAMPS; 726 e->state = ENVSYS_SINVALID; 727 strlcpy(e->desc, "battery charge current", sizeof(e->desc)); 728 sysmon_envsys_sensor_attach(sc->sc_sme, e); 729 } 730 731 if (c->discharge_step) { 732 e = &sc->sc_sensor[AXP_SENSOR_BATT_DISCHARGE_CURRENT]; 733 e->private = AXP_SENSOR_BATT_DISCHARGE_CURRENT; 734 e->units = ENVSYS_SAMPS; 735 e->state = ENVSYS_SINVALID; 736 strlcpy(e->desc, "battery discharge current", sizeof(e->desc)); 737 sysmon_envsys_sensor_attach(sc->sc_sme, e); 738 } 739 740 if (c->has_fuel_gauge) { 741 e = &sc->sc_sensor[AXP_SENSOR_BATT_CAPACITY_PERCENT]; 742 e->private = AXP_SENSOR_BATT_CAPACITY_PERCENT; 743 e->units = ENVSYS_INTEGER; 744 e->state = ENVSYS_SINVALID; 745 e->flags = ENVSYS_FPERCENT; 746 strlcpy(e->desc, "battery percent", sizeof(e->desc)); 747 sysmon_envsys_sensor_attach(sc->sc_sme, e); 748 } 749 750 if (c->maxcap_step) { 751 e = &sc->sc_sensor[AXP_SENSOR_BATT_MAXIMUM_CAPACITY]; 752 e->private = AXP_SENSOR_BATT_MAXIMUM_CAPACITY; 753 e->units = ENVSYS_SAMPHOUR; 754 e->state = ENVSYS_SINVALID; 755 strlcpy(e->desc, "battery maximum capacity", sizeof(e->desc)); 756 sysmon_envsys_sensor_attach(sc->sc_sme, e); 757 } 758 759 if (c->coulomb_step) { 760 e = &sc->sc_sensor[AXP_SENSOR_BATT_CURRENT_CAPACITY]; 761 e->private = AXP_SENSOR_BATT_CURRENT_CAPACITY; 762 e->units = ENVSYS_SAMPHOUR; 763 e->state = ENVSYS_SINVALID; 764 strlcpy(e->desc, "battery current capacity", sizeof(e->desc)); 765 sysmon_envsys_sensor_attach(sc->sc_sme, e); 766 } 767 } 768 769 static void 770 axppmic_attach_sensors(struct axppmic_softc *sc) 771 { 772 if (sc->sc_conf->has_battery) { 773 sc->sc_sme = sysmon_envsys_create(); 774 sc->sc_sme->sme_name = device_xname(sc->sc_dev); 775 sc->sc_sme->sme_cookie = sc; 776 sc->sc_sme->sme_refresh = axppmic_sensor_refresh; 777 sc->sc_sme->sme_class = SME_CLASS_BATTERY; 778 sc->sc_sme->sme_flags = SME_INIT_REFRESH; 779 780 axppmic_attach_acadapter(sc); 781 axppmic_attach_battery(sc); 782 783 sysmon_envsys_register(sc->sc_sme); 784 } 785 } 786 787 788 static int 789 axppmic_match(device_t parent, cfdata_t match, void *aux) 790 { 791 struct i2c_attach_args *ia = aux; 792 int match_result; 793 794 if (iic_use_direct_match(ia, match, compat_data, &match_result)) 795 return match_result; 796 797 /* This device is direct-config only. */ 798 799 return 0; 800 } 801 802 static void 803 axppmic_attach(device_t parent, device_t self, void *aux) 804 { 805 struct axppmic_softc *sc = device_private(self); 806 const struct device_compatible_entry *dce = NULL; 807 const struct axppmic_config *c; 808 struct axpreg_attach_args aaa; 809 struct i2c_attach_args *ia = aux; 810 int phandle, child, i; 811 uint32_t irq_mask; 812 void *ih; 813 814 (void) iic_compatible_match(ia, compat_data, &dce); 815 KASSERT(dce != NULL); 816 c = (void *)dce->data; 817 818 sc->sc_dev = self; 819 sc->sc_i2c = ia->ia_tag; 820 sc->sc_addr = ia->ia_addr; 821 sc->sc_phandle = ia->ia_cookie; 822 sc->sc_conf = c; 823 824 aprint_naive("\n"); 825 aprint_normal(": %s\n", c->name); 826 827 sc->sc_smpsw.smpsw_name = device_xname(self); 828 sc->sc_smpsw.smpsw_type = PSWITCH_TYPE_POWER; 829 sysmon_pswitch_register(&sc->sc_smpsw); 830 831 iic_acquire_bus(sc->sc_i2c, I2C_F_POLL); 832 for (i = 1; i <= c->irq_regs; i++) { 833 irq_mask = 0; 834 if (i == c->poklirq.reg) 835 irq_mask |= c->poklirq.mask; 836 if (i == c->acinirq.reg) 837 irq_mask |= c->acinirq.mask; 838 if (i == c->vbusirq.reg) 839 irq_mask |= c->vbusirq.mask; 840 if (i == c->battirq.reg) 841 irq_mask |= c->battirq.mask; 842 if (i == c->chargeirq.reg) 843 irq_mask |= c->chargeirq.mask; 844 if (i == c->chargestirq.reg) 845 irq_mask |= c->chargestirq.mask; 846 axppmic_write(sc->sc_i2c, sc->sc_addr, AXP_IRQ_ENABLE_REG(i), irq_mask, I2C_F_POLL); 847 } 848 iic_release_bus(sc->sc_i2c, I2C_F_POLL); 849 850 ih = fdtbus_intr_establish(sc->sc_phandle, 0, IPL_VM, FDT_INTR_MPSAFE, 851 axppmic_intr, sc); 852 if (ih == NULL) { 853 aprint_error_dev(self, "WARNING: couldn't establish interrupt handler\n"); 854 } 855 856 fdtbus_register_power_controller(sc->sc_dev, sc->sc_phandle, 857 &axppmic_power_funcs); 858 859 phandle = of_find_firstchild_byname(sc->sc_phandle, "regulators"); 860 if (phandle > 0) { 861 aaa.reg_i2c = sc->sc_i2c; 862 aaa.reg_addr = sc->sc_addr; 863 for (i = 0; i < c->ncontrols; i++) { 864 const struct axppmic_ctrl *ctrl = &c->controls[i]; 865 child = of_find_firstchild_byname(phandle, ctrl->c_name); 866 if (child <= 0) 867 continue; 868 aaa.reg_ctrl = ctrl; 869 aaa.reg_phandle = child; 870 config_found(sc->sc_dev, &aaa, NULL); 871 } 872 } 873 874 if (c->has_battery) 875 axppmic_attach_sensors(sc); 876 } 877 878 static int 879 axpreg_acquire(device_t dev) 880 { 881 return 0; 882 } 883 884 static void 885 axpreg_release(device_t dev) 886 { 887 } 888 889 static int 890 axpreg_enable(device_t dev, bool enable) 891 { 892 struct axpreg_softc *sc = device_private(dev); 893 const struct axppmic_ctrl *c = sc->sc_ctrl; 894 const int flags = (cold ? I2C_F_POLL : 0); 895 uint8_t val; 896 int error; 897 898 if (!c->c_enable_mask) 899 return EINVAL; 900 901 iic_acquire_bus(sc->sc_i2c, flags); 902 if ((error = axppmic_read(sc->sc_i2c, sc->sc_addr, c->c_enable_reg, &val, flags)) == 0) { 903 if (enable) 904 val |= c->c_enable_mask; 905 else 906 val &= ~c->c_enable_mask; 907 error = axppmic_write(sc->sc_i2c, sc->sc_addr, c->c_enable_reg, val, flags); 908 } 909 iic_release_bus(sc->sc_i2c, flags); 910 911 return error; 912 } 913 914 static int 915 axpreg_set_voltage(device_t dev, u_int min_uvol, u_int max_uvol) 916 { 917 struct axpreg_softc *sc = device_private(dev); 918 const struct axppmic_ctrl *c = sc->sc_ctrl; 919 920 return axppmic_set_voltage(sc->sc_i2c, sc->sc_addr, c, 921 min_uvol / 1000, max_uvol / 1000); 922 } 923 924 static int 925 axpreg_get_voltage(device_t dev, u_int *puvol) 926 { 927 struct axpreg_softc *sc = device_private(dev); 928 const struct axppmic_ctrl *c = sc->sc_ctrl; 929 int error; 930 u_int vol; 931 932 error = axppmic_get_voltage(sc->sc_i2c, sc->sc_addr, c, &vol); 933 if (error) 934 return error; 935 936 *puvol = vol * 1000; 937 return 0; 938 } 939 940 static struct fdtbus_regulator_controller_func axpreg_funcs = { 941 .acquire = axpreg_acquire, 942 .release = axpreg_release, 943 .enable = axpreg_enable, 944 .set_voltage = axpreg_set_voltage, 945 .get_voltage = axpreg_get_voltage, 946 }; 947 948 static int 949 axpreg_match(device_t parent, cfdata_t match, void *aux) 950 { 951 return 1; 952 } 953 954 static void 955 axpreg_attach(device_t parent, device_t self, void *aux) 956 { 957 struct axpreg_softc *sc = device_private(self); 958 struct axpreg_attach_args *aaa = aux; 959 const int phandle = aaa->reg_phandle; 960 const char *name; 961 962 sc->sc_dev = self; 963 sc->sc_i2c = aaa->reg_i2c; 964 sc->sc_addr = aaa->reg_addr; 965 sc->sc_ctrl = aaa->reg_ctrl; 966 967 fdtbus_register_regulator_controller(self, phandle, 968 &axpreg_funcs); 969 970 aprint_naive("\n"); 971 name = fdtbus_get_string(phandle, "regulator-name"); 972 if (name) 973 aprint_normal(": %s\n", name); 974 else 975 aprint_normal("\n"); 976 } 977 978 CFATTACH_DECL_NEW(axppmic, sizeof(struct axppmic_softc), 979 axppmic_match, axppmic_attach, NULL, NULL); 980 981 CFATTACH_DECL_NEW(axpreg, sizeof(struct axpreg_softc), 982 axpreg_match, axpreg_attach, NULL, NULL); 983
Indexes created Fri Oct 03 02:09:57 GMT 2025