dbcool.c revision 1.10
1 /* $NetBSD: dbcool.c,v 1.10 2009/02/08 17:48:02 pgoyette Exp $ */ 2 3 /*- 4 * Copyright (c) 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Goyette 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * a driver for the dbCool(tm) family of environmental controllers 34 * 35 * Data sheets for the various supported chips are available at 36 * 37 * http://www.onsemi.com/pub/Collateral/ADM1027-D.PDF 38 * http://www.onsemi.com/pub/Collateral/ADM1030-D.PDF 39 * http://www.onsemi.com/pub/Collateral/ADT7463-D.PDF 40 * http://www.onsemi.com/pub/Collateral/ADT7466.PDF 41 * http://www.onsemi.com/pub/Collateral/ADT7467-D.PDF 42 * http://www.onsemi.com/pub/Collateral/ADT7468-D.PDF 43 * http://www.onsemi.com/pub/Collateral/ADT7473-D.PDF 44 * http://www.onsemi.com/pub/Collateral/ADT7475-D.PDF 45 * http://www.onsemi.com/pub/Collateral/ADT7476-D.PDF 46 * http://www.onsemi.com/pub/Collateral/ADT7490-D.PDF 47 * 48 * (URLs are correct as of October 5, 2008) 49 */ 50 51 #include <sys/cdefs.h> 52 __KERNEL_RCSID(0, "$NetBSD: dbcool.c,v 1.10 2009/02/08 17:48:02 pgoyette Exp $"); 53 54 #include <sys/param.h> 55 #include <sys/systm.h> 56 #include <sys/kernel.h> 57 #include <sys/device.h> 58 #include <sys/malloc.h> 59 #include <sys/sysctl.h> 60 61 #include <uvm/uvm_extern.h> 62 63 #include <dev/i2c/dbcool_var.h> 64 #include <dev/i2c/dbcool_reg.h> 65 66 /* Config interface */ 67 static int dbcool_match(device_t, cfdata_t, void *); 68 static void dbcool_attach(device_t, device_t, void *); 69 static int dbcool_detach(device_t, int); 70 71 /* Device attributes */ 72 static int dbcool_supply_voltage(struct dbcool_softc *); 73 static bool dbcool_islocked(struct dbcool_softc *); 74 75 /* Sensor read functions */ 76 static void dbcool_refresh(struct sysmon_envsys *, envsys_data_t *); 77 static int dbcool_read_rpm(struct dbcool_softc *, uint8_t); 78 static int dbcool_read_temp(struct dbcool_softc *, uint8_t, bool); 79 static int dbcool_read_volt(struct dbcool_softc *, uint8_t, int, bool); 80 81 /* SYSCTL Helpers */ 82 static int sysctl_dbcool_temp(SYSCTLFN_PROTO); 83 static int sysctl_adm1030_temp(SYSCTLFN_PROTO); 84 static int sysctl_adm1030_trange(SYSCTLFN_PROTO); 85 static int sysctl_dbcool_duty(SYSCTLFN_PROTO); 86 static int sysctl_dbcool_behavior(SYSCTLFN_PROTO); 87 static int sysctl_dbcool_slope(SYSCTLFN_PROTO); 88 static int sysctl_dbcool_volt_limit(SYSCTLFN_PROTO); 89 static int sysctl_dbcool_temp_limit(SYSCTLFN_PROTO); 90 static int sysctl_dbcool_fan_limit(SYSCTLFN_PROTO); 91 static int sysctl_dbcool_thyst(SYSCTLFN_PROTO); 92 static int sysctl_dbcool_vid(SYSCTLFN_PROTO); 93 94 /* Set-up subroutines */ 95 static void dbcool_setup_controllers(struct dbcool_softc *, 96 const struct sysctlnode *, int, int); 97 static int dbcool_setup_sensors(struct dbcool_softc *, 98 const struct sysctlnode *, int, int); 99 static int dbcool_attach_sensor(struct dbcool_softc *, 100 const struct sysctlnode *, int, int (*)(SYSCTLFN_PROTO)); 101 102 #ifdef DBCOOL_DEBUG 103 static int sysctl_dbcool_reg_select(SYSCTLFN_PROTO); 104 static int sysctl_dbcool_reg_access(SYSCTLFN_PROTO); 105 #endif /* DBCOOL_DEBUG */ 106 107 /* 108 * Descriptions for SYSCTL entries 109 */ 110 struct dbc_sysctl_info { 111 const char *name; 112 const char *desc; 113 bool lockable; 114 int (*helper)(SYSCTLFN_PROTO); 115 }; 116 117 static struct dbc_sysctl_info dbc_sysctl_table[] = { 118 /* 119 * The first several entries must remain in the same order as the 120 * corresponding entries in enum dbc_pwm_params 121 */ 122 { "behavior", "operating behavior and temp selector", 123 true, sysctl_dbcool_behavior }, 124 { "min_duty", "minimum fan controller PWM duty cycle", 125 true, sysctl_dbcool_duty }, 126 { "max_duty", "maximum fan controller PWM duty cycle", 127 true, sysctl_dbcool_duty }, 128 { "cur_duty", "current fan controller PWM duty cycle", 129 false, sysctl_dbcool_duty }, 130 131 /* 132 * The rest of these should be in the order in which they 133 * are to be stored in the sysctl tree; the table index is 134 * used as the high-order bits of the sysctl_num to maintain 135 * the sequence. 136 * 137 * If you rearrange the order of these items, be sure to 138 * update the sysctl_index in the XXX_sensor_table[] for 139 * the various chips! 140 */ 141 { "Trange", "temp slope/range to reach 100% duty cycle", 142 true, sysctl_dbcool_slope }, 143 { "Tmin", "temp at which to start fan controller", 144 true, sysctl_dbcool_temp }, 145 { "Ttherm", "temp at which THERM is asserted", 146 true, sysctl_dbcool_temp }, 147 { "Thyst", "temp hysteresis for stopping fan controller", 148 true, sysctl_dbcool_thyst }, 149 { "Tmin", "temp at which to start fan controller", 150 true, sysctl_adm1030_temp }, 151 { "Trange", "temp slope/range to reach 100% duty cycle", 152 true, sysctl_adm1030_trange }, 153 }; 154 155 static const char *dbc_sensor_names[] = { 156 "l_temp", "r1_temp", "r2_temp", "Vccp", "Vcc", "fan1", 157 "fan2", "fan3", "fan4", "AIN1", "AIN2", "V2dot5", 158 "V5", "V12", "Vtt", "Imon" 159 }; 160 161 /* 162 * Following table derived from product data-sheets 163 */ 164 static int64_t nominal_voltages[] = { 165 -1, /* Vcc can be either 3.3 or 5.0V 166 at 3/4 scale */ 167 2249939, /* Vccp 2.25V 3/4 scale */ 168 2497436, /* 2.5VIN 2.5V 3/4 scale */ 169 5002466, /* 5VIN 5V 3/4 scale */ 170 12000000, /* 12VIN 12V 3/4 scale */ 171 1690809, /* Vtt, Imon 2.25V full scale */ 172 1689600, /* AIN1, AIN2 2.25V full scale */ 173 0 174 }; 175 176 /* 177 * Sensor-type, { val-reg, hilim-reg, lolim-reg}, name-idx, sysctl-table-idx, 178 * nom-voltage-index 179 */ 180 struct dbcool_sensor ADT7490_sensor_table[] = { 181 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 182 DBCOOL_LOCAL_HIGHLIM, 183 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 184 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 185 DBCOOL_REMOTE1_HIGHLIM, 186 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 187 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 188 DBCOOL_REMOTE2_HIGHLIM, 189 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 190 { DBC_VOLT, { DBCOOL_VCCP, 191 DBCOOL_VCCP_HIGHLIM, 192 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 193 { DBC_VOLT, { DBCOOL_VCC, 194 DBCOOL_VCC_HIGHLIM, 195 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 196 { DBC_VOLT, { DBCOOL_25VIN, 197 DBCOOL_25VIN_HIGHLIM, 198 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 }, 199 { DBC_VOLT, { DBCOOL_5VIN, 200 DBCOOL_5VIN_HIGHLIM, 201 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 }, 202 { DBC_VOLT, { DBCOOL_12VIN, 203 DBCOOL_12VIN_HIGHLIM, 204 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 }, 205 { DBC_VOLT, { DBCOOL_VTT, 206 DBCOOL_VTT_HIGHLIM, 207 DBCOOL_VTT_LOWLIM }, 14, 0, 5 }, 208 { DBC_VOLT, { DBCOOL_IMON, 209 DBCOOL_IMON_HIGHLIM, 210 DBCOOL_IMON_LOWLIM }, 15, 0, 5 }, 211 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 212 DBCOOL_NO_REG, 213 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 214 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 215 DBCOOL_NO_REG, 216 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 217 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 218 DBCOOL_NO_REG, 219 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 220 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 221 DBCOOL_NO_REG, 222 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 223 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 224 DBCOOL_NO_REG, 225 DBCOOL_NO_REG }, 0, 5, 0 }, 226 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 227 DBCOOL_NO_REG, 228 DBCOOL_NO_REG }, 0, 6, 0 }, 229 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 230 DBCOOL_NO_REG, 231 DBCOOL_NO_REG }, 0, 7, 0 }, 232 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 233 DBCOOL_NO_REG, 234 DBCOOL_NO_REG }, 1, 5, 0 }, 235 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 236 DBCOOL_NO_REG, 237 DBCOOL_NO_REG }, 1, 6, 0 }, 238 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 239 DBCOOL_NO_REG, 240 DBCOOL_NO_REG }, 1, 7, 0 }, 241 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 242 DBCOOL_NO_REG, 243 DBCOOL_NO_REG }, 2, 5, 0 }, 244 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 245 DBCOOL_NO_REG, 246 DBCOOL_NO_REG }, 2, 6, 0 }, 247 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 248 DBCOOL_NO_REG, 249 DBCOOL_NO_REG }, 2, 7, 0 }, 250 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 251 }; 252 253 struct dbcool_sensor ADT7476_sensor_table[] = { 254 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 255 DBCOOL_LOCAL_HIGHLIM, 256 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 257 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 258 DBCOOL_REMOTE1_HIGHLIM, 259 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 260 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 261 DBCOOL_REMOTE2_HIGHLIM, 262 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 263 { DBC_VOLT, { DBCOOL_VCCP, 264 DBCOOL_VCCP_HIGHLIM, 265 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 266 { DBC_VOLT, { DBCOOL_VCC, 267 DBCOOL_VCC_HIGHLIM, 268 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 269 { DBC_VOLT, { DBCOOL_25VIN, 270 DBCOOL_25VIN_HIGHLIM, 271 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 }, 272 { DBC_VOLT, { DBCOOL_5VIN, 273 DBCOOL_5VIN_HIGHLIM, 274 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 }, 275 { DBC_VOLT, { DBCOOL_12VIN, 276 DBCOOL_12VIN_HIGHLIM, 277 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 }, 278 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 279 DBCOOL_NO_REG, 280 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 281 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 282 DBCOOL_NO_REG, 283 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 284 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 285 DBCOOL_NO_REG, 286 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 287 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 288 DBCOOL_NO_REG, 289 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 290 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 291 DBCOOL_NO_REG, 292 DBCOOL_NO_REG }, 0, 5, 0 }, 293 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 294 DBCOOL_NO_REG, 295 DBCOOL_NO_REG }, 0, 6, 0 }, 296 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 297 DBCOOL_NO_REG, 298 DBCOOL_NO_REG }, 0, 7, 0 }, 299 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 300 DBCOOL_NO_REG, 301 DBCOOL_NO_REG }, 1, 5, 0 }, 302 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 303 DBCOOL_NO_REG, 304 DBCOOL_NO_REG }, 1, 6, 0 }, 305 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 306 DBCOOL_NO_REG, 307 DBCOOL_NO_REG }, 1, 7, 0 }, 308 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 309 DBCOOL_NO_REG, 310 DBCOOL_NO_REG }, 2, 5, 0 }, 311 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 312 DBCOOL_NO_REG, 313 DBCOOL_NO_REG }, 2, 6, 0 }, 314 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 315 DBCOOL_NO_REG, 316 DBCOOL_NO_REG }, 2, 7, 0 }, 317 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 318 }; 319 320 struct dbcool_sensor ADT7475_sensor_table[] = { 321 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 322 DBCOOL_LOCAL_HIGHLIM, 323 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 324 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 325 DBCOOL_REMOTE1_HIGHLIM, 326 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 327 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 328 DBCOOL_REMOTE2_HIGHLIM, 329 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 330 { DBC_VOLT, { DBCOOL_VCCP, 331 DBCOOL_VCCP_HIGHLIM, 332 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 333 { DBC_VOLT, { DBCOOL_VCC, 334 DBCOOL_VCC_HIGHLIM, 335 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 336 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 337 DBCOOL_NO_REG, 338 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 339 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 340 DBCOOL_NO_REG, 341 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 342 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 343 DBCOOL_NO_REG, 344 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 345 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 346 DBCOOL_NO_REG, 347 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 348 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 349 DBCOOL_NO_REG, 350 DBCOOL_NO_REG }, 0, 5, 0 }, 351 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 352 DBCOOL_NO_REG, 353 DBCOOL_NO_REG }, 0, 6, 0 }, 354 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 355 DBCOOL_NO_REG, 356 DBCOOL_NO_REG }, 0, 7, 0 }, 357 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 358 DBCOOL_NO_REG, 359 DBCOOL_NO_REG }, 1, 5, 0 }, 360 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 361 DBCOOL_NO_REG, 362 DBCOOL_NO_REG }, 1, 6, 0 }, 363 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 364 DBCOOL_NO_REG, 365 DBCOOL_NO_REG }, 1, 7, 0 }, 366 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 367 DBCOOL_NO_REG, 368 DBCOOL_NO_REG }, 2, 5, 0 }, 369 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 370 DBCOOL_NO_REG, 371 DBCOOL_NO_REG }, 2, 6, 0 }, 372 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 373 DBCOOL_NO_REG, 374 DBCOOL_NO_REG }, 2, 7, 0 }, 375 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 376 }; 377 378 /* 379 * The registers of dbcool_power_control must be in the same order as 380 * in enum dbc_pwm_params 381 */ 382 struct dbcool_power_control ADT7475_power_table[] = { 383 { { DBCOOL_PWM1_CTL, DBCOOL_PWM1_MINDUTY, 384 DBCOOL_PWM1_MAXDUTY, DBCOOL_PWM1_CURDUTY }, 385 "fan_control_1" }, 386 { { DBCOOL_PWM2_CTL, DBCOOL_PWM2_MINDUTY, 387 DBCOOL_PWM2_MAXDUTY, DBCOOL_PWM2_CURDUTY }, 388 "fan_control_2" }, 389 { { DBCOOL_PWM3_CTL, DBCOOL_PWM3_MINDUTY, 390 DBCOOL_PWM3_MAXDUTY, DBCOOL_PWM3_CURDUTY }, 391 "fan_control_3" }, 392 { { 0, 0, 0, 0 }, NULL } 393 }; 394 395 struct dbcool_sensor ADT7466_sensor_table[] = { 396 { DBC_TEMP, { DBCOOL_ADT7466_LCL_TEMP_MSB, 397 DBCOOL_ADT7466_LCL_TEMP_HILIM, 398 DBCOOL_ADT7466_LCL_TEMP_LOLIM }, 0, 0, 0 }, 399 { DBC_TEMP, { DBCOOL_ADT7466_REM_TEMP_MSB, 400 DBCOOL_ADT7466_REM_TEMP_HILIM, 401 DBCOOL_ADT7466_REM_TEMP_LOLIM }, 1, 0, 0 }, 402 { DBC_VOLT, { DBCOOL_ADT7466_VCC, 403 DBCOOL_ADT7466_VCC_HILIM, 404 DBCOOL_ADT7466_VCC_LOLIM }, 4, 0, 0 }, 405 { DBC_VOLT, { DBCOOL_ADT7466_AIN1, 406 DBCOOL_ADT7466_AIN1_HILIM, 407 DBCOOL_ADT7466_AIN1_LOLIM }, 9, 0, 6 }, 408 { DBC_VOLT, { DBCOOL_ADT7466_AIN2, 409 DBCOOL_ADT7466_AIN2_HILIM, 410 DBCOOL_ADT7466_AIN2_LOLIM }, 10, 0, 6 }, 411 { DBC_FAN, { DBCOOL_ADT7466_FANA_LSB, 412 DBCOOL_NO_REG, 413 DBCOOL_ADT7466_FANA_LOLIM_LSB }, 5, 0, 0 }, 414 { DBC_FAN, { DBCOOL_ADT7466_FANB_LSB, 415 DBCOOL_NO_REG, 416 DBCOOL_ADT7466_FANB_LOLIM_LSB }, 6, 0, 0 }, 417 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 418 }; 419 420 struct dbcool_sensor ADM1027_sensor_table[] = { 421 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 422 DBCOOL_LOCAL_HIGHLIM, 423 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 424 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 425 DBCOOL_REMOTE1_HIGHLIM, 426 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 427 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 428 DBCOOL_REMOTE2_HIGHLIM, 429 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 430 { DBC_VOLT, { DBCOOL_VCCP, 431 DBCOOL_VCCP_HIGHLIM, 432 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 433 { DBC_VOLT, { DBCOOL_VCC, 434 DBCOOL_VCC_HIGHLIM, 435 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 436 { DBC_VOLT, { DBCOOL_25VIN, 437 DBCOOL_25VIN_HIGHLIM, 438 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 }, 439 { DBC_VOLT, { DBCOOL_5VIN, 440 DBCOOL_5VIN_HIGHLIM, 441 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 }, 442 { DBC_VOLT, { DBCOOL_12VIN, 443 DBCOOL_12VIN_HIGHLIM, 444 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 }, 445 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 446 DBCOOL_NO_REG, 447 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 448 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 449 DBCOOL_NO_REG, 450 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 451 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 452 DBCOOL_NO_REG, 453 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 454 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 455 DBCOOL_NO_REG, 456 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 457 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 458 DBCOOL_NO_REG, 459 DBCOOL_NO_REG }, 0, 5, 0 }, 460 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 461 DBCOOL_NO_REG, 462 DBCOOL_NO_REG }, 0, 6, 0 }, 463 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 464 DBCOOL_NO_REG, 465 DBCOOL_NO_REG }, 0, 7, 0 }, 466 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 467 DBCOOL_NO_REG, 468 DBCOOL_NO_REG }, 1, 5, 0 }, 469 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 470 DBCOOL_NO_REG, 471 DBCOOL_NO_REG }, 1, 6, 0 }, 472 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 473 DBCOOL_NO_REG, 474 DBCOOL_NO_REG }, 1, 7, 0 }, 475 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 476 DBCOOL_NO_REG, 477 DBCOOL_NO_REG }, 2, 5, 0 }, 478 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 479 DBCOOL_NO_REG, 480 DBCOOL_NO_REG }, 2, 6, 0 }, 481 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 482 DBCOOL_NO_REG, 483 DBCOOL_NO_REG }, 2, 7, 0 }, 484 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 485 }; 486 487 struct dbcool_sensor ADM1030_sensor_table[] = { 488 { DBC_TEMP, { DBCOOL_ADM1030_L_TEMP, 489 DBCOOL_ADM1030_L_HI_LIM, 490 DBCOOL_ADM1030_L_LO_LIM }, 0, 0, 0 }, 491 { DBC_TEMP, { DBCOOL_ADM1030_R_TEMP, 492 DBCOOL_ADM1030_R_HI_LIM, 493 DBCOOL_ADM1030_R_LO_LIM }, 1, 0, 0 }, 494 { DBC_FAN, { DBCOOL_ADM1030_FAN_TACH, 495 DBCOOL_NO_REG, 496 DBCOOL_ADM1030_FAN_LO_LIM }, 5, 0, 0 }, 497 { DBC_CTL, { DBCOOL_ADM1030_L_TMIN, 498 DBCOOL_NO_REG, 499 DBCOOL_NO_REG }, 0, 8, 0 }, 500 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH, 501 DBCOOL_NO_REG, 502 DBCOOL_NO_REG }, 0, 9, 0 }, 503 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH, 504 DBCOOL_NO_REG, 505 DBCOOL_NO_REG }, 0, 6, 0 }, 506 { DBC_CTL, { DBCOOL_ADM1030_R_TMIN, 507 DBCOOL_NO_REG, 508 DBCOOL_NO_REG }, 1, 8, 0 }, 509 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH, 510 DBCOOL_NO_REG, 511 DBCOOL_NO_REG }, 1, 9, 0 }, 512 { DBC_CTL, { DBCOOL_ADM1030_R_TTHRESH, 513 DBCOOL_NO_REG, 514 DBCOOL_NO_REG }, 1, 6, 0 }, 515 { DBC_EOF, {0, 0, 0 }, 0, 0, 0 } 516 }; 517 518 struct dbcool_power_control ADM1030_power_table[] = { 519 { { DBCOOL_ADM1030_CFG1, DBCOOL_NO_REG, DBCOOL_NO_REG, 520 DBCOOL_ADM1030_FAN_SPEED_CFG }, 521 "fan_control_1" }, 522 { { 0, 0, 0, 0 }, NULL } 523 }; 524 525 struct chip_id chip_table[] = { 526 { DBCOOL_COMPANYID, ADT7490_DEVICEID, ADT7490_REV_ID, 527 ADT7475_sensor_table, ADT7475_power_table, 528 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_VID | 529 DBCFLAG_HAS_PECI, 530 90000 * 60, "ADT7490" }, 531 { DBCOOL_COMPANYID, ADT7476_DEVICEID, 0xff, 532 ADT7476_sensor_table, ADT7475_power_table, 533 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_VID, 534 90000 * 60, "ADT7476" }, 535 { DBCOOL_COMPANYID, ADT7475_DEVICEID, 0xff, 536 ADT7475_sensor_table, ADT7475_power_table, 537 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_SHDN, 538 90000 * 60, "ADT7475" }, 539 { DBCOOL_COMPANYID, ADT7473_DEVICEID, ADT7473_REV_ID1, 540 ADT7475_sensor_table, ADT7475_power_table, 541 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_SHDN, 542 90000 * 60, "ADT7460/ADT7463" }, 543 { DBCOOL_COMPANYID, ADT7473_DEVICEID, ADT7473_REV_ID2, 544 ADT7475_sensor_table, ADT7475_power_table, 545 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_SHDN, 546 90000 * 60, "ADT7463-1" }, 547 { DBCOOL_COMPANYID, ADT7468_DEVICEID, 0xff, 548 ADT7476_sensor_table, ADT7475_power_table, 549 DBCFLAG_TEMPOFFSET | DBCFLAG_MULTI_VCC | DBCFLAG_HAS_MAXDUTY | 550 DBCFLAG_4BIT_VER | DBCFLAG_HAS_SHDN | DBCFLAG_HAS_VID, 551 90000 * 60, "ADT7467/ADT7468" }, 552 { DBCOOL_COMPANYID, ADT7466_DEVICEID, 0xff, 553 ADT7466_sensor_table, NULL, 554 DBCFLAG_ADT7466 | DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_SHDN, 555 82000 * 60, "ADT7466" }, 556 { DBCOOL_COMPANYID, ADT7463_DEVICEID, ADT7463_REV_ID1, 557 ADM1027_sensor_table, ADT7475_power_table, 558 DBCFLAG_MULTI_VCC | DBCFLAG_4BIT_VER | DBCFLAG_HAS_SHDN | 559 DBCFLAG_ADM1027 | DBCFLAG_HAS_VID, 560 90000 * 60, "ADT7463" }, 561 { DBCOOL_COMPANYID, ADT7463_DEVICEID, ADT7463_REV_ID2, 562 ADM1027_sensor_table, ADT7475_power_table, 563 DBCFLAG_MULTI_VCC | DBCFLAG_4BIT_VER | DBCFLAG_HAS_SHDN | 564 DBCFLAG_HAS_VID | DBCFLAG_HAS_VID_SEL, 565 90000 * 60, "ADT7463" }, 566 { DBCOOL_COMPANYID, ADM1027_DEVICEID, ADM1027_REV_ID, 567 ADM1027_sensor_table, ADT7475_power_table, 568 DBCFLAG_MULTI_VCC | DBCFLAG_4BIT_VER | DBCFLAG_HAS_VID, 569 90000 * 60, "ADM1027" }, 570 { DBCOOL_COMPANYID, ADM1030_DEVICEID, 0xff, 571 ADM1030_sensor_table, ADM1030_power_table, 572 DBCFLAG_ADM1030, 573 11250 * 60, "ADM1030" }, 574 { 0, 0, 0, NULL, NULL, 0, 0, NULL } 575 }; 576 577 static const char *behavior[] = { 578 "remote1", "local", "remote2", "full-speed", 579 "disabled", "local+remote2","all-temps", "manual" 580 }; 581 582 static char dbcool_cur_behav[16]; 583 584 CFATTACH_DECL_NEW(dbcool, sizeof(struct dbcool_softc), 585 dbcool_match, dbcool_attach, dbcool_detach, NULL); 586 587 int 588 dbcool_match(device_t parent, cfdata_t cf, void *aux) 589 { 590 struct i2c_attach_args *ia = aux; 591 struct dbcool_softc sc; 592 sc.sc_tag = ia->ia_tag; 593 sc.sc_addr = ia->ia_addr; 594 sc.sc_readreg = dbcool_readreg; 595 sc.sc_writereg = dbcool_writereg; 596 597 /* no probing if we attach to iic, but verify chip id and address */ 598 if ((ia->ia_addr & DBCOOL_ADDRMASK) != DBCOOL_ADDR) 599 return 0; 600 if (dbcool_chip_ident(&sc) >= 0) 601 return 1; 602 603 return 0; 604 } 605 606 void 607 dbcool_attach(device_t parent, device_t self, void *aux) 608 { 609 struct dbcool_softc *sc = device_private(self); 610 struct i2c_attach_args *args = aux; 611 uint8_t ver; 612 613 sc->sc_addr = args->ia_addr; 614 sc->sc_tag = args->ia_tag; 615 sc->sc_dev = self; 616 sc->sc_readreg = dbcool_readreg; 617 sc->sc_writereg = dbcool_writereg; 618 (void)dbcool_chip_ident(sc); 619 620 aprint_naive("\n"); 621 aprint_normal("\n"); 622 623 ver = sc->sc_readreg(sc, DBCOOL_REVISION_REG); 624 if (sc->sc_chip->flags & DBCFLAG_4BIT_VER) 625 aprint_normal_dev(self, "%s dBCool(tm) Controller " 626 "(rev 0x%02x, stepping 0x%02x)\n", sc->sc_chip->name, 627 ver >> 4, ver & 0x0f); 628 else 629 aprint_normal_dev(self, "%s dBCool(tm) Controller " 630 "(rev 0x%04x)\n", sc->sc_chip->name, ver); 631 632 dbcool_setup(self); 633 634 if (!pmf_device_register(self, dbcool_pmf_suspend, dbcool_pmf_resume)) 635 aprint_error_dev(self, "couldn't establish power handler\n"); 636 } 637 638 static int 639 dbcool_detach(device_t self, int flags) 640 { 641 struct dbcool_softc *sc = device_private(self); 642 643 sysmon_envsys_unregister(sc->sc_sme); 644 sc->sc_sme = NULL; 645 return 0; 646 } 647 648 /* On suspend, we save the state of the SHDN bit, then set it */ 649 bool dbcool_pmf_suspend(device_t dev PMF_FN_ARGS) 650 { 651 struct dbcool_softc *sc = device_private(dev); 652 uint8_t reg, bit, cfg; 653 654 if ((sc->sc_chip->flags && DBCFLAG_HAS_SHDN) == 0) 655 return true; 656 657 if (sc->sc_chip->flags && DBCFLAG_ADT7466) { 658 reg = DBCOOL_ADT7466_CONFIG2; 659 bit = DBCOOL_ADT7466_CFG2_SHDN; 660 } else { 661 reg = DBCOOL_CONFIG2_REG; 662 bit = DBCOOL_CFG2_SHDN; 663 } 664 cfg = sc->sc_readreg(sc, reg); 665 sc->sc_suspend = cfg & bit; 666 cfg |= bit; 667 sc->sc_writereg(sc, reg, cfg); 668 669 return true; 670 } 671 672 /* On resume, we restore the previous state of the SHDN bit */ 673 bool dbcool_pmf_resume(device_t dev PMF_FN_ARGS) 674 { 675 struct dbcool_softc *sc = device_private(dev); 676 uint8_t reg, bit, cfg; 677 678 if ((sc->sc_chip->flags && DBCFLAG_HAS_SHDN) == 0) 679 return true; 680 681 if (sc->sc_chip->flags && DBCFLAG_ADT7466) { 682 reg = DBCOOL_ADT7466_CONFIG2; 683 bit = DBCOOL_ADT7466_CFG2_SHDN; 684 } else { 685 reg = DBCOOL_CONFIG2_REG; 686 bit = DBCOOL_CFG2_SHDN; 687 } 688 cfg = sc->sc_readreg(sc, reg); 689 cfg &= ~sc->sc_suspend; 690 sc->sc_writereg(sc, reg, cfg); 691 692 return true; 693 694 } 695 696 uint8_t 697 dbcool_readreg(struct dbcool_softc *sc, uint8_t reg) 698 { 699 uint8_t data = 0; 700 701 if (iic_acquire_bus(sc->sc_tag, 0) != 0) 702 goto bad; 703 704 if (sc->sc_chip->flags & DBCFLAG_ADM1027) { 705 /* ADM1027 doesn't support i2c read_byte protocol */ 706 if (iic_smbus_send_byte(sc->sc_tag, sc->sc_addr, reg, 0) != 0) 707 goto bad; 708 (void)iic_smbus_receive_byte(sc->sc_tag, sc->sc_addr, &data, 0); 709 } else 710 (void)iic_smbus_read_byte(sc->sc_tag, sc->sc_addr, reg, &data, 711 0); 712 713 bad: 714 iic_release_bus(sc->sc_tag, 0); 715 return data; 716 } 717 718 void 719 dbcool_writereg(struct dbcool_softc *sc, uint8_t reg, uint8_t val) 720 { 721 if (iic_acquire_bus(sc->sc_tag, 0) != 0) 722 return; 723 724 (void)iic_smbus_write_byte(sc->sc_tag, sc->sc_addr, reg, val, 0); 725 726 iic_release_bus(sc->sc_tag, 0); 727 return; 728 } 729 730 static bool 731 dbcool_islocked(struct dbcool_softc *sc) 732 { 733 uint8_t cfg_reg; 734 735 if (sc->sc_chip->flags & DBCFLAG_ADM1030) 736 return 0; 737 738 if (sc->sc_chip->flags & DBCFLAG_ADT7466) 739 cfg_reg = DBCOOL_ADT7466_CONFIG1; 740 else 741 cfg_reg = DBCOOL_CONFIG1_REG; 742 743 if (sc->sc_readreg(sc, cfg_reg) & DBCOOL_CFG1_LOCK) 744 return 1; 745 else 746 return 0; 747 } 748 749 static int 750 dbcool_read_temp(struct dbcool_softc *sc, uint8_t reg, bool extres) 751 { 752 uint8_t t1, t2, t3, val, ext = 0; 753 int temp; 754 755 if (sc->sc_chip->flags & DBCFLAG_ADT7466) { 756 /* 757 * ADT7466 temps are in strange location 758 */ 759 ext = sc->sc_readreg(sc, DBCOOL_ADT7466_CONFIG1); 760 val = sc->sc_readreg(sc, reg); 761 if (extres) 762 ext = sc->sc_readreg(sc, reg + 1); 763 } else if (sc->sc_chip->flags & DBCFLAG_ADM1030) { 764 /* 765 * ADM1030 temps are in their own special place, too 766 */ 767 if (extres) { 768 ext = sc->sc_readreg(sc, DBCOOL_ADM1030_TEMP_EXTRES); 769 if (reg == DBCOOL_ADM1030_L_TEMP) 770 ext >>= 6; 771 else 772 ext >>= 1; 773 ext &= 0x03; 774 } 775 val = sc->sc_readreg(sc, reg); 776 } else if (extres) { 777 ext = sc->sc_readreg(sc, DBCOOL_EXTRES2_REG); 778 779 /* Read all msb regs to unlatch them */ 780 t1 = sc->sc_readreg(sc, DBCOOL_12VIN); 781 t1 = sc->sc_readreg(sc, DBCOOL_REMOTE1_TEMP); 782 t2 = sc->sc_readreg(sc, DBCOOL_REMOTE2_TEMP); 783 t3 = sc->sc_readreg(sc, DBCOOL_LOCAL_TEMP); 784 switch (reg) { 785 case DBCOOL_REMOTE1_TEMP: 786 val = t1; 787 ext >>= 2; 788 break; 789 case DBCOOL_LOCAL_TEMP: 790 val = t3; 791 ext >>= 4; 792 break; 793 case DBCOOL_REMOTE2_TEMP: 794 val = t2; 795 ext >>= 6; 796 break; 797 default: 798 val = 0; 799 break; 800 } 801 ext &= 0x03; 802 } 803 else 804 val = sc->sc_readreg(sc, reg); 805 806 /* Check for invalid temp values */ 807 if ((sc->sc_temp_offset == 0 && val == 0x80) || 808 (sc->sc_temp_offset != 0 && val == 0)) 809 return 0; 810 811 /* If using offset mode, adjust, else treat as signed */ 812 if (sc->sc_temp_offset) { 813 temp = val; 814 temp -= sc->sc_temp_offset; 815 } else 816 temp = (int8_t)val; 817 818 /* Convert degC to uK and include extended precision bits */ 819 temp *= 1000000; 820 temp += 250000 * (int)ext; 821 temp += 273150000U; 822 823 return temp; 824 } 825 826 static int 827 dbcool_read_rpm(struct dbcool_softc *sc, uint8_t reg) 828 { 829 int rpm; 830 uint8_t rpm_lo, rpm_hi; 831 832 rpm_lo = sc->sc_readreg(sc, reg); 833 if (sc->sc_chip->flags & DBCFLAG_ADM1030) 834 rpm_hi = (rpm_lo == 0xff)?0xff:0x0; 835 else 836 rpm_hi = sc->sc_readreg(sc, reg + 1); 837 838 rpm = (rpm_hi << 8) | rpm_lo; 839 if (rpm == 0xffff) 840 return 0; /* 0xffff indicates stalled/failed fan */ 841 842 return (sc->sc_chip->rpm_dividend / rpm); 843 } 844 845 /* Provide chip's supply voltage, in microvolts */ 846 static int 847 dbcool_supply_voltage(struct dbcool_softc *sc) 848 { 849 if (sc->sc_chip->flags & DBCFLAG_MULTI_VCC) { 850 if (sc->sc_readreg(sc, DBCOOL_CONFIG1_REG) & DBCOOL_CFG1_Vcc) 851 return 5002500; 852 else 853 return 3300000; 854 } else if (sc->sc_chip->flags & DBCFLAG_ADT7466) { 855 if (sc->sc_readreg(sc, DBCOOL_ADT7466_CONFIG1) & 856 DBCOOL_ADT7466_CFG1_Vcc) 857 return 5000000; 858 else 859 return 3300000; 860 } else 861 return 3300000; 862 } 863 864 /* 865 * Nominal voltages are calculated in microvolts 866 */ 867 static int 868 dbcool_read_volt(struct dbcool_softc *sc, uint8_t reg, int nom_idx, bool extres) 869 { 870 uint8_t ext = 0, v1, v2, v3, v4, val; 871 int64_t ret; 872 int64_t nom; 873 874 nom = nominal_voltages[nom_idx]; 875 if (nom < 0) 876 nom = sc->sc_supply_voltage; 877 878 /* ADT7466 voltages are in strange locations with only 8-bits */ 879 if (sc->sc_chip->flags & DBCFLAG_ADT7466) 880 val = sc->sc_readreg(sc, reg); 881 else 882 /* 883 * It's a "normal" dbCool chip - check for regs that 884 * share extended resolution bits since we have to 885 * read all the MSB registers to unlatch them. 886 */ 887 if (!extres) 888 val = sc->sc_readreg(sc, reg); 889 else if (reg == DBCOOL_12VIN) { 890 ext = sc->sc_readreg(sc, DBCOOL_EXTRES2_REG) && 0x03; 891 val = sc->sc_readreg(sc, reg); 892 (void)dbcool_read_temp(sc, DBCOOL_LOCAL_TEMP, true); 893 } else if (reg == DBCOOL_VTT || reg == DBCOOL_IMON) { 894 ext = sc->sc_readreg(sc, DBCOOL_EXTRES_VTT_IMON); 895 v1 = sc->sc_readreg(sc, DBCOOL_IMON); 896 v2 = sc->sc_readreg(sc, DBCOOL_VTT); 897 if (reg == DBCOOL_IMON) { 898 val = v1; 899 ext >>= 6; 900 } else 901 val = v2; 902 ext >>= 4; 903 ext &= 0x0f; 904 } else { 905 ext = sc->sc_readreg(sc, DBCOOL_EXTRES1_REG); 906 v1 = sc->sc_readreg(sc, DBCOOL_25VIN); 907 v2 = sc->sc_readreg(sc, DBCOOL_VCCP); 908 v3 = sc->sc_readreg(sc, DBCOOL_VCC); 909 v4 = sc->sc_readreg(sc, DBCOOL_5VIN); 910 911 switch (reg) { 912 case DBCOOL_25VIN: 913 val = v1; 914 break; 915 case DBCOOL_VCCP: 916 val = v2; 917 ext >>= 2; 918 break; 919 case DBCOOL_VCC: 920 val = v3; 921 ext >>= 4; 922 break; 923 case DBCOOL_5VIN: 924 val = v4; 925 ext >>= 6; 926 break; 927 default: 928 val = nom = 0; 929 } 930 ext &= 0x03; 931 } 932 933 /* 934 * Scale the nominal value by the 10-bit fraction 935 * 936 * Returned value is in microvolts. 937 */ 938 ret = val; 939 ret <<= 2; 940 ret |= ext; 941 ret = (ret * nom) / 0x300; 942 943 return ret; 944 } 945 946 SYSCTL_SETUP(sysctl_dbcoolsetup, "sysctl dBCool subtree setup") 947 { 948 sysctl_createv(NULL, 0, NULL, NULL, 949 CTLFLAG_PERMANENT, 950 CTLTYPE_NODE, "hw", NULL, 951 NULL, 0, NULL, 0, 952 CTL_HW, CTL_EOL); 953 } 954 955 static int 956 sysctl_dbcool_temp(SYSCTLFN_ARGS) 957 { 958 struct sysctlnode node; 959 struct dbcool_softc *sc; 960 int reg, error; 961 uint8_t chipreg; 962 uint8_t newreg; 963 964 node = *rnode; 965 sc = (struct dbcool_softc *)node.sysctl_data; 966 chipreg = node.sysctl_num & 0xff; 967 968 if (sc->sc_temp_offset) { 969 reg = sc->sc_readreg(sc, chipreg); 970 reg -= sc->sc_temp_offset; 971 } else 972 reg = (int8_t)sc->sc_readreg(sc, chipreg); 973 974 node.sysctl_data = ® 975 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 976 977 if (error || newp == NULL) 978 return error; 979 980 /* We were asked to update the value - sanity check before writing */ 981 if (*(int *)node.sysctl_data < -64 || 982 *(int *)node.sysctl_data > 127 + sc->sc_temp_offset) 983 return EINVAL; 984 985 newreg = *(int *)node.sysctl_data; 986 newreg += sc->sc_temp_offset; 987 sc->sc_writereg(sc, chipreg, newreg); 988 return 0; 989 } 990 991 static int 992 sysctl_adm1030_temp(SYSCTLFN_ARGS) 993 { 994 struct sysctlnode node; 995 struct dbcool_softc *sc; 996 int reg, error; 997 uint8_t chipreg, oldreg, newreg; 998 999 node = *rnode; 1000 sc = (struct dbcool_softc *)node.sysctl_data; 1001 chipreg = node.sysctl_num & 0xff; 1002 1003 oldreg = (int8_t)sc->sc_readreg(sc, chipreg); 1004 reg = (oldreg >> 1) & ~0x03; 1005 1006 node.sysctl_data = ® 1007 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1008 1009 if (error || newp == NULL) 1010 return error; 1011 1012 /* We were asked to update the value - sanity check before writing */ 1013 if (*(int *)node.sysctl_data < 0 || *(int *)node.sysctl_data > 127) 1014 return EINVAL; 1015 1016 newreg = *(int *)node.sysctl_data; 1017 newreg &= ~0x03; 1018 newreg <<= 1; 1019 newreg |= (oldreg & 0x07); 1020 sc->sc_writereg(sc, chipreg, newreg); 1021 return 0; 1022 } 1023 1024 static int 1025 sysctl_adm1030_trange(SYSCTLFN_ARGS) 1026 { 1027 struct sysctlnode node; 1028 struct dbcool_softc *sc; 1029 int reg, error, newval; 1030 uint8_t chipreg, oldreg, newreg; 1031 1032 node = *rnode; 1033 sc = (struct dbcool_softc *)node.sysctl_data; 1034 chipreg = node.sysctl_num & 0xff; 1035 1036 oldreg = (int8_t)sc->sc_readreg(sc, chipreg); 1037 reg = oldreg & 0x07; 1038 1039 node.sysctl_data = ® 1040 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1041 1042 if (error || newp == NULL) 1043 return error; 1044 1045 /* We were asked to update the value - sanity check before writing */ 1046 newval = *(int *)node.sysctl_data; 1047 1048 if (newval == 5) 1049 newreg = 0; 1050 else if (newval == 10) 1051 newreg = 1; 1052 else if (newval == 20) 1053 newreg = 2; 1054 else if (newval == 40) 1055 newreg = 3; 1056 else if (newval == 80) 1057 newreg = 4; 1058 else 1059 return EINVAL; 1060 1061 newreg |= (oldreg & ~0x07); 1062 sc->sc_writereg(sc, chipreg, newreg); 1063 return 0; 1064 } 1065 1066 static int 1067 sysctl_dbcool_duty(SYSCTLFN_ARGS) 1068 { 1069 struct sysctlnode node; 1070 struct dbcool_softc *sc; 1071 int reg, error; 1072 uint8_t chipreg, oldreg, newreg; 1073 1074 node = *rnode; 1075 sc = (struct dbcool_softc *)node.sysctl_data; 1076 chipreg = node.sysctl_num & 0xff; 1077 1078 oldreg = sc->sc_readreg(sc, chipreg); 1079 reg = (uint32_t)oldreg; 1080 if (sc->sc_chip->flags & DBCFLAG_ADM1030) 1081 reg = ((reg & 0x0f) * 100) / 15; 1082 else 1083 reg = (reg * 100) / 255; 1084 node.sysctl_data = ® 1085 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1086 1087 if (error || newp == NULL) 1088 return error; 1089 1090 /* We were asked to update the value - sanity check before writing */ 1091 if (*(int *)node.sysctl_data < 0 || *(int *)node.sysctl_data > 100) 1092 return EINVAL; 1093 1094 if (sc->sc_chip->flags & DBCFLAG_ADM1030) { 1095 newreg = *(uint8_t *)(node.sysctl_data) * 15 / 100; 1096 newreg |= oldreg & 0xf0; 1097 } else 1098 newreg = *(uint8_t *)(node.sysctl_data) * 255 / 100; 1099 sc->sc_writereg(sc, chipreg, newreg); 1100 return 0; 1101 } 1102 1103 static int 1104 sysctl_dbcool_behavior(SYSCTLFN_ARGS) 1105 { 1106 struct sysctlnode node; 1107 struct dbcool_softc *sc; 1108 int i, reg, error; 1109 uint8_t chipreg, oldreg, newreg; 1110 1111 node = *rnode; 1112 sc = (struct dbcool_softc *)node.sysctl_data; 1113 chipreg = node.sysctl_num & 0xff; 1114 1115 oldreg = sc->sc_readreg(sc, chipreg); 1116 1117 if (sc->sc_chip->flags & DBCFLAG_ADM1030) { 1118 if ((sc->sc_readreg(sc, DBCOOL_ADM1030_CFG2) & 1) == 0) 1119 reg = 4; 1120 else if ((oldreg & 0x80) == 0) 1121 reg = 7; 1122 else if ((oldreg & 0x60) == 0) 1123 reg = 4; 1124 else 1125 reg = 6; 1126 } else 1127 reg = (oldreg >> 5) & 0x07; 1128 1129 strlcpy(dbcool_cur_behav, behavior[reg], sizeof(dbcool_cur_behav)); 1130 node.sysctl_data = dbcool_cur_behav; 1131 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1132 1133 if (error || newp == NULL) 1134 return error; 1135 1136 /* We were asked to update the value - convert string to value */ 1137 newreg = __arraycount(behavior); 1138 for (i = 0; i < __arraycount(behavior); i++) 1139 if (strcmp(node.sysctl_data, behavior[i]) == 0) 1140 break; 1141 if (i >= __arraycount(behavior)) 1142 return EINVAL; 1143 1144 if (sc->sc_chip->flags & DBCFLAG_ADM1030) { 1145 /* 1146 * ADM1030 splits fan controller behavior across two 1147 * registers. We also do not support Auto-Filter mode 1148 * nor do we support Manual-RPM-feedback. 1149 */ 1150 if (newreg == 4) { 1151 oldreg = sc->sc_readreg(sc, DBCOOL_ADM1030_CFG2); 1152 oldreg &= ~0x01; 1153 sc->sc_writereg(sc, DBCOOL_ADM1030_CFG2, oldreg); 1154 } else { 1155 if (newreg == 0) 1156 newreg = 4; 1157 else if (newreg == 6) 1158 newreg = 7; 1159 else if (newreg == 7) 1160 newreg = 0; 1161 else 1162 return EINVAL; 1163 newreg <<= 5; 1164 newreg |= (oldreg & 0x1f); 1165 sc->sc_writereg(sc, chipreg, newreg); 1166 oldreg = sc->sc_readreg(sc, DBCOOL_ADM1030_CFG2) | 1; 1167 sc->sc_writereg(sc, DBCOOL_ADM1030_CFG2, oldreg); 1168 } 1169 } else { 1170 newreg = (sc->sc_readreg(sc, chipreg) & 0x1f) | (i << 5); 1171 sc->sc_writereg(sc, chipreg, newreg); 1172 } 1173 return 0; 1174 } 1175 1176 static int 1177 sysctl_dbcool_slope(SYSCTLFN_ARGS) 1178 { 1179 struct sysctlnode node; 1180 struct dbcool_softc *sc; 1181 int reg, error; 1182 uint8_t chipreg; 1183 uint8_t newreg; 1184 1185 node = *rnode; 1186 sc = (struct dbcool_softc *)node.sysctl_data; 1187 chipreg = node.sysctl_num & 0xff; 1188 1189 reg = (sc->sc_readreg(sc, chipreg) >> 4) & 0x0f; 1190 node.sysctl_data = ® 1191 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1192 1193 if (error || newp == NULL) 1194 return error; 1195 1196 /* We were asked to update the value - sanity check before writing */ 1197 if (*(int *)node.sysctl_data < 0 || *(int *)node.sysctl_data > 0x0f) 1198 return EINVAL; 1199 1200 newreg = (sc->sc_readreg(sc, chipreg) & 0x0f) | 1201 (*(int *)node.sysctl_data << 4); 1202 sc->sc_writereg(sc, chipreg, newreg); 1203 return 0; 1204 } 1205 1206 static int 1207 sysctl_dbcool_volt_limit(SYSCTLFN_ARGS) 1208 { 1209 struct sysctlnode node; 1210 struct dbcool_softc *sc; 1211 int reg, error; 1212 int nom, sensor_index; 1213 int64_t val, newval; 1214 uint8_t chipreg, newreg; 1215 1216 node = *rnode; 1217 sc = (struct dbcool_softc *)node.sysctl_data; 1218 chipreg = node.sysctl_num & 0xff; 1219 1220 /* 1221 * Retrieve the nominal value for the voltage sensor 1222 */ 1223 sensor_index = (node.sysctl_num >> 8 ) & 0xff; 1224 nom = nominal_voltages[sc->sc_chip->table[sensor_index].nom_volt_index]; 1225 if (nom < 0) 1226 nom = dbcool_supply_voltage(sc); 1227 1228 /* 1229 * Use int64_t for calculation to avoid overflow 1230 */ 1231 val = sc->sc_readreg(sc, chipreg); 1232 val *= nom; 1233 val /= 0xc0; /* values are scaled so 0xc0 == nominal voltage */ 1234 reg = val; 1235 node.sysctl_data = ® 1236 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1237 1238 if (error || newp == NULL) 1239 return error; 1240 1241 /* 1242 * We were asked to update the value, so scale it and sanity 1243 * check before writing 1244 */ 1245 if (nom == 0) 1246 return EINVAL; 1247 newval = *(int *)node.sysctl_data; 1248 newval *= 0xc0; 1249 newval /= nom; 1250 if (newval < 0 || newval > 0xff) 1251 return EINVAL; 1252 1253 newreg = newval; 1254 sc->sc_writereg(sc, chipreg, newreg); 1255 return 0; 1256 } 1257 1258 static int 1259 sysctl_dbcool_temp_limit(SYSCTLFN_ARGS) 1260 { 1261 struct sysctlnode node; 1262 struct dbcool_softc *sc; 1263 int reg, error, newtemp; 1264 uint8_t chipreg; 1265 1266 node = *rnode; 1267 sc = (struct dbcool_softc *)node.sysctl_data; 1268 chipreg = node.sysctl_num & 0xff; 1269 1270 /* If using offset mode, adjust, else treat as signed */ 1271 if (sc->sc_temp_offset) { 1272 reg = sc->sc_readreg(sc, chipreg); 1273 reg -= sc->sc_temp_offset; 1274 } else 1275 reg = (int8_t)sc->sc_readreg(sc, chipreg); 1276 1277 node.sysctl_data = ® 1278 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1279 1280 if (error || newp == NULL) 1281 return error; 1282 1283 /* We were asked to update the value - sanity check before writing */ 1284 newtemp = *(int *)node.sysctl_data + sc->sc_temp_offset; 1285 if (newtemp < 0 || newtemp > 0xff) 1286 return EINVAL; 1287 1288 sc->sc_writereg(sc, chipreg, newtemp); 1289 return 0; 1290 } 1291 1292 static int 1293 sysctl_dbcool_fan_limit(SYSCTLFN_ARGS) 1294 { 1295 struct sysctlnode node; 1296 struct dbcool_softc *sc; 1297 int reg, error, newrpm, dividend; 1298 uint8_t chipreg; 1299 uint8_t newreg; 1300 1301 node = *rnode; 1302 sc = (struct dbcool_softc *)node.sysctl_data; 1303 chipreg = node.sysctl_num & 0xff; 1304 1305 /* retrieve two-byte limit */ 1306 reg = dbcool_read_rpm(sc, chipreg); 1307 1308 node.sysctl_data = ® 1309 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1310 1311 if (error || newp == NULL) 1312 return error; 1313 1314 /* 1315 * We were asked to update the value. Calculate the two-byte 1316 * limit and validate it. Due to the way fan RPM is calculated, 1317 * the new value must be at least 83 RPM (331 RPM for ADM1030)! 1318 * Allow a value of -1 or 0 to indicate no limit. 1319 */ 1320 newrpm = *(int *)node.sysctl_data; 1321 if (newrpm == 0 || newrpm == -1) 1322 newrpm = 0xffff; 1323 else { 1324 if (sc->sc_chip->flags & DBCFLAG_ADM1030) 1325 dividend = 11250 * 60; 1326 else 1327 dividend = 90000 * 60; 1328 newrpm = dividend / newrpm; 1329 if (newrpm & ~0xffff) 1330 return EINVAL; 1331 } 1332 1333 /* Update the on-chip registers with new value */ 1334 newreg = newrpm & 0xff; 1335 sc->sc_writereg(sc, chipreg, newreg); 1336 newreg = (newrpm >> 8) & 0xff; 1337 sc->sc_writereg(sc, chipreg + 1, newreg); 1338 return 0; 1339 } 1340 1341 static int 1342 sysctl_dbcool_vid(SYSCTLFN_ARGS) 1343 { 1344 struct sysctlnode node; 1345 struct dbcool_softc *sc; 1346 int reg, error; 1347 uint8_t chipreg, newreg; 1348 1349 node = *rnode; 1350 sc = (struct dbcool_softc *)node.sysctl_data; 1351 chipreg = node.sysctl_num; 1352 1353 /* retrieve 5- or 6-bit value */ 1354 newreg = sc->sc_readreg(sc, chipreg); 1355 if ((sc->sc_chip->flags & DBCFLAG_HAS_VID_SEL) && 1356 (reg & 0x80)) 1357 reg = newreg & 0x3f; 1358 else 1359 reg = newreg & 0x1f; 1360 1361 node.sysctl_data = ® 1362 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1363 1364 if (error == 0 && newp != NULL) 1365 error = EINVAL; 1366 1367 return error; 1368 } 1369 1370 static int 1371 sysctl_dbcool_thyst(SYSCTLFN_ARGS) 1372 { 1373 struct sysctlnode node; 1374 struct dbcool_softc *sc; 1375 int reg, error; 1376 uint8_t chipreg; 1377 uint8_t newreg, newhyst; 1378 1379 node = *rnode; 1380 sc = (struct dbcool_softc *)node.sysctl_data; 1381 chipreg = node.sysctl_num & 0x7f; 1382 1383 /* retrieve 4-bit value */ 1384 newreg = sc->sc_readreg(sc, chipreg); 1385 if ((node.sysctl_num & 0x80) == 0) 1386 reg = newreg >> 4; 1387 else 1388 reg = newreg; 1389 reg = reg & 0x0f; 1390 1391 node.sysctl_data = ® 1392 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1393 1394 if (error || newp == NULL) 1395 return error; 1396 1397 /* We were asked to update the value - sanity check before writing */ 1398 newhyst = *(int *)node.sysctl_data; 1399 if (newhyst > 0x0f) 1400 return EINVAL; 1401 1402 /* Insert new value into field and update register */ 1403 if ((node.sysctl_num & 0x80) == 0) { 1404 newreg &= 0x0f; 1405 newreg |= (newhyst << 4); 1406 } else { 1407 newreg &= 0xf0; 1408 newreg |= newhyst; 1409 } 1410 sc->sc_writereg(sc, chipreg, newreg); 1411 return 0; 1412 } 1413 1414 #ifdef DBCOOL_DEBUG 1415 1416 /* 1417 * These routines can be used for debugging. reg_select is used to 1418 * select any arbitrary register in the device. reg_access is used 1419 * to read (and optionally update) the selected register. 1420 * 1421 * No attempt is made to validate the data passed. If you use these 1422 * routines, you are assumed to know what you're doing! 1423 * 1424 * Caveat user 1425 */ 1426 static int 1427 sysctl_dbcool_reg_select(SYSCTLFN_ARGS) 1428 { 1429 struct sysctlnode node; 1430 struct dbcool_softc *sc; 1431 int reg, error; 1432 1433 node = *rnode; 1434 sc = (struct dbcool_softc *)node.sysctl_data; 1435 1436 reg = sc->sc_user_reg; 1437 node.sysctl_data = ® 1438 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1439 1440 if (error || newp == NULL) 1441 return error; 1442 1443 sc->sc_user_reg = *(int *)node.sysctl_data; 1444 return 0; 1445 } 1446 1447 static int 1448 sysctl_dbcool_reg_access(SYSCTLFN_ARGS) 1449 { 1450 struct sysctlnode node; 1451 struct dbcool_softc *sc; 1452 int reg, error; 1453 uint8_t chipreg; 1454 uint8_t newreg; 1455 1456 node = *rnode; 1457 sc = (struct dbcool_softc *)node.sysctl_data; 1458 chipreg = sc->sc_user_reg; 1459 1460 reg = sc->sc_readreg(sc, chipreg); 1461 node.sysctl_data = ® 1462 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1463 1464 if (error || newp == NULL) 1465 return error; 1466 1467 newreg = *(int *)node.sysctl_data; 1468 sc->sc_writereg(sc, chipreg, newreg); 1469 return 0; 1470 } 1471 #endif /* DBCOOL_DEBUG */ 1472 1473 /* 1474 * Encode an index number and register number for use as a sysctl_num 1475 * so we can select the correct device register later. 1476 */ 1477 #define DBC_PWM_SYSCTL(seq, reg) ((seq << 8) | reg) 1478 1479 void 1480 dbcool_setup(device_t self) 1481 { 1482 struct dbcool_softc *sc = device_private(self); 1483 const struct sysctlnode *me = NULL; 1484 struct sysctlnode *node = NULL; 1485 uint8_t cfg_val, cfg_reg; 1486 int ro_flag, rw_flag, ret, error; 1487 1488 /* 1489 * Some chips are capable of reporting an extended temperature range 1490 * by default. On these models, config register 5 bit 0 can be set 1491 * to 1 for compatability with other chips that report 2s complement. 1492 */ 1493 if (sc->sc_chip->flags & DBCFLAG_ADT7466) { 1494 if (sc->sc_readreg(sc, DBCOOL_ADT7466_CONFIG1) & 0x80) 1495 sc->sc_temp_offset = 64; 1496 else 1497 sc->sc_temp_offset = 0; 1498 } else if (sc->sc_chip->flags & DBCFLAG_TEMPOFFSET) { 1499 if (sc->sc_readreg(sc, DBCOOL_CONFIG5_REG) & 1500 DBCOOL_CFG5_TWOSCOMP) 1501 sc->sc_temp_offset = 0; 1502 else 1503 sc->sc_temp_offset = 64; 1504 } else 1505 sc->sc_temp_offset = 0; 1506 1507 /* Determine Vcc for this chip */ 1508 sc->sc_supply_voltage = dbcool_supply_voltage(sc); 1509 1510 sc->sc_sme = sysmon_envsys_create(); 1511 1512 ro_flag = dbcool_islocked(sc)?CTLFLAG_READONLY:CTLFLAG_READWRITE; 1513 ro_flag |= CTLFLAG_OWNDESC; 1514 rw_flag = CTLFLAG_READWRITE | CTLFLAG_OWNDESC; 1515 ret = sysctl_createv(NULL, 0, NULL, &me, 1516 CTLFLAG_READWRITE, 1517 CTLTYPE_NODE, device_xname(self), NULL, 1518 NULL, 0, NULL, 0, 1519 CTL_HW, CTL_CREATE, CTL_EOL); 1520 if (sc->sc_chip->flags & DBCFLAG_HAS_VID) { 1521 ret = sysctl_createv(NULL, 0, NULL, 1522 (const struct sysctlnode **)&node, 1523 CTLFLAG_READONLY, CTLTYPE_INT, "CPU_VID_bits", NULL, 1524 sysctl_dbcool_vid, 1525 0, sc, sizeof(int), 1526 CTL_HW, me->sysctl_num, DBCOOL_VID_REG, CTL_EOL); 1527 if (node != NULL) 1528 node->sysctl_data = sc; 1529 } 1530 1531 #ifdef DBCOOL_DEBUG 1532 ret = sysctl_createv(NULL, 0, NULL, 1533 (const struct sysctlnode **)&node, 1534 CTLFLAG_READWRITE, CTLTYPE_INT, "reg_select", NULL, 1535 sysctl_dbcool_reg_select, 1536 0, sc, sizeof(int), 1537 CTL_HW, me->sysctl_num, CTL_CREATE, CTL_EOL); 1538 if (node != NULL) 1539 node->sysctl_data = sc; 1540 1541 ret = sysctl_createv(NULL, 0, NULL, 1542 (const struct sysctlnode **)&node, 1543 CTLFLAG_READWRITE, CTLTYPE_INT, "reg_access", NULL, 1544 sysctl_dbcool_reg_access, 1545 0, sc, sizeof(int), 1546 CTL_HW, me->sysctl_num, CTL_CREATE, CTL_EOL); 1547 if (node != NULL) 1548 node->sysctl_data = sc; 1549 #endif /* DBCOOL_DEBUG */ 1550 1551 /* Create the sensors for this device */ 1552 if (dbcool_setup_sensors(sc, me, rw_flag, ro_flag)) 1553 goto out; 1554 1555 /* If supported, create sysctl tree for fan PWM controllers */ 1556 if (sc->sc_chip->power != NULL) 1557 dbcool_setup_controllers(sc, me, rw_flag, ro_flag); 1558 1559 /* 1560 * Read and rewrite config register to activate device 1561 */ 1562 if (sc->sc_chip->flags & DBCFLAG_ADM1030) 1563 cfg_reg = DBCOOL_ADM1030_CFG1; 1564 else if (sc->sc_chip->flags & DBCFLAG_ADT7466) 1565 cfg_reg = DBCOOL_ADT7466_CONFIG1; 1566 else 1567 cfg_reg = DBCOOL_CONFIG1_REG; 1568 cfg_val = sc->sc_readreg(sc, DBCOOL_CONFIG1_REG); 1569 if ((cfg_val & DBCOOL_CFG1_START) == 0) { 1570 cfg_val |= DBCOOL_CFG1_START; 1571 sc->sc_writereg(sc, cfg_reg, cfg_val); 1572 } 1573 if (dbcool_islocked(sc)) 1574 aprint_normal_dev(self, "configuration locked\n"); 1575 1576 sc->sc_sme->sme_name = device_xname(self); 1577 sc->sc_sme->sme_cookie = sc; 1578 sc->sc_sme->sme_refresh = dbcool_refresh; 1579 1580 if ((error = sysmon_envsys_register(sc->sc_sme)) != 0) { 1581 aprint_error_dev(self, 1582 "unable to register with sysmon (%d)\n", error); 1583 goto out; 1584 } 1585 1586 return; 1587 1588 out: 1589 sysmon_envsys_destroy(sc->sc_sme); 1590 } 1591 1592 static int 1593 dbcool_setup_sensors(struct dbcool_softc *sc, const struct sysctlnode *me, 1594 int rw_flag, int ro_flag) 1595 { 1596 int i, j, ret; 1597 int error = 0; 1598 uint8_t sysctl_reg; 1599 struct sysctlnode *node = NULL; 1600 int sysctl_index, sysctl_num; 1601 char name[SYSCTL_NAMELEN]; 1602 1603 for (i=0; sc->sc_chip->table[i].type != DBC_EOF; i++) { 1604 if (i >= DBCOOL_MAXSENSORS && 1605 sc->sc_chip->table[i].type != DBC_CTL) { 1606 aprint_normal_dev(sc->sc_dev, "chip table too big!\n"); 1607 break; 1608 } 1609 switch (sc->sc_chip->table[i].type) { 1610 case DBC_TEMP: 1611 sc->sc_sensor[i].units = ENVSYS_STEMP; 1612 error = dbcool_attach_sensor(sc, me, i, 1613 sysctl_dbcool_temp_limit); 1614 break; 1615 case DBC_VOLT: 1616 sc->sc_sensor[i].units = ENVSYS_SVOLTS_DC; 1617 error = dbcool_attach_sensor(sc, me, i, 1618 sysctl_dbcool_volt_limit); 1619 break; 1620 case DBC_FAN: 1621 sc->sc_sensor[i].units = ENVSYS_SFANRPM; 1622 error = dbcool_attach_sensor(sc, me, i, 1623 sysctl_dbcool_fan_limit); 1624 break; 1625 case DBC_CTL: 1626 /* 1627 * Search for the corresponding temp sensor 1628 * (temp sensors need to be created first!) 1629 */ 1630 sysctl_num = -1; 1631 for (j = 0; j < i; j++) { 1632 if (j > DBCOOL_MAXSENSORS || 1633 sc->sc_chip->table[j].type != DBC_TEMP) 1634 continue; 1635 if (sc->sc_chip->table[j].name_index == 1636 sc->sc_chip->table[i].name_index) { 1637 sysctl_num = sc->sc_sysctl_num[j]; 1638 break; 1639 } 1640 } 1641 if (sysctl_num == -1) 1642 break; 1643 sysctl_index = sc->sc_chip->table[i].sysctl_index; 1644 sysctl_reg = sc->sc_chip->table[i].reg.val_reg; 1645 strlcpy(name, dbc_sysctl_table[sysctl_index].name, 1646 sizeof(name)); 1647 ret = sysctl_createv(NULL, 0, NULL, 1648 (const struct sysctlnode **)&node, 1649 dbc_sysctl_table[sysctl_index].lockable? 1650 ro_flag:rw_flag, 1651 CTLTYPE_INT, name, 1652 dbc_sysctl_table[sysctl_index].desc, 1653 dbc_sysctl_table[sysctl_index].helper, 1654 0, sc, sizeof(int), 1655 CTL_HW, me->sysctl_num, sysctl_num, 1656 DBC_PWM_SYSCTL(i, sysctl_reg), CTL_EOL); 1657 if (node != NULL) 1658 node->sysctl_data = sc; 1659 break; 1660 default: 1661 aprint_error_dev(sc->sc_dev, 1662 "sensor_table index %d has bad type %d\n", 1663 i, sc->sc_chip->table[i].type); 1664 break; 1665 } 1666 if (error) 1667 break; 1668 } 1669 return error; 1670 } 1671 1672 static int 1673 dbcool_attach_sensor(struct dbcool_softc *sc, const struct sysctlnode *me, 1674 int idx, int (*helper)(SYSCTLFN_PROTO)) 1675 { 1676 struct sysctlnode *node = NULL; 1677 const struct sysctlnode *me2 = NULL; 1678 uint8_t sysctl_reg; 1679 int name_index; 1680 int ret; 1681 int error = 0; 1682 1683 name_index = sc->sc_chip->table[idx].name_index; 1684 strlcpy(sc->sc_sensor[idx].desc, dbc_sensor_names[name_index], 1685 sizeof(sc->sc_sensor[idx].desc)); 1686 sc->sc_regs[idx] = &sc->sc_chip->table[idx].reg; 1687 sc->sc_nom_volt[idx] = sc->sc_chip->table[idx].nom_volt_index; 1688 1689 sc->sc_sensor[idx].flags |= ENVSYS_FMONCRITUNDER; 1690 if (sc->sc_chip->table[idx].type != DBC_FAN) 1691 sc->sc_sensor[idx].flags |= ENVSYS_FMONCRITOVER; 1692 1693 error = sysmon_envsys_sensor_attach(sc->sc_sme, &sc->sc_sensor[idx]); 1694 if (error) 1695 return error; 1696 1697 /* 1698 * create sysctl node for the sensor, and the nodes for 1699 * the sensor's high and low limit values 1700 */ 1701 ret = sysctl_createv(NULL, 0, NULL, &me2, CTLFLAG_READWRITE, 1702 CTLTYPE_NODE, sc->sc_sensor[idx].desc, NULL, 1703 NULL, 0, NULL, 0, 1704 CTL_HW, me->sysctl_num, CTL_CREATE, CTL_EOL); 1705 if (me2 == NULL) 1706 return 0; 1707 1708 sc->sc_sysctl_num[idx] = me2->sysctl_num; 1709 1710 /* create sysctl node for the low limit */ 1711 sysctl_reg = sc->sc_regs[idx]->lo_lim_reg; 1712 ret = sysctl_createv(NULL, 0, NULL, 1713 (const struct sysctlnode **)&node, 1714 CTLFLAG_READWRITE, 1715 CTLTYPE_INT, "low_lim", NULL, helper, 0, sc, 0, 1716 CTL_HW, me->sysctl_num, me2->sysctl_num, 1717 DBC_PWM_SYSCTL(idx, sysctl_reg), CTL_EOL); 1718 if (node != NULL) 1719 node->sysctl_data = sc; 1720 1721 /* Fans do not have a high limit */ 1722 if (sc->sc_chip->table[idx].type == DBC_FAN) 1723 return 0; 1724 1725 sysctl_reg = sc->sc_regs[idx]->hi_lim_reg; 1726 ret = sysctl_createv(NULL, 0, NULL, 1727 (const struct sysctlnode **)&node, 1728 CTLFLAG_READWRITE, 1729 CTLTYPE_INT, "hi_lim", NULL, helper, 0, sc, 0, 1730 CTL_HW, me->sysctl_num, me2->sysctl_num, 1731 DBC_PWM_SYSCTL(idx, sysctl_reg), CTL_EOL); 1732 if (node != NULL) 1733 node->sysctl_data = sc; 1734 1735 return 0; 1736 } 1737 1738 static void 1739 dbcool_setup_controllers(struct dbcool_softc *sc, const struct sysctlnode *me, 1740 int rw_flag, int ro_flag) 1741 { 1742 int i, j, ret; 1743 uint8_t sysctl_reg; 1744 const struct sysctlnode *me2 = NULL; 1745 struct sysctlnode *node = NULL; 1746 char name[SYSCTL_NAMELEN]; 1747 1748 for (i = 0; sc->sc_chip->power[i].desc != NULL; i++) { 1749 snprintf(name, sizeof(name), "fan_ctl_%d", i); 1750 ret = sysctl_createv(NULL, 0, NULL, &me2, 1751 rw_flag, 1752 CTLTYPE_NODE, name, NULL, 1753 NULL, 0, NULL, 0, 1754 CTL_HW, me->sysctl_num, CTL_CREATE, CTL_EOL); 1755 1756 for (j = DBC_PWM_BEHAVIOR; j < DBC_PWM_LAST_PARAM; j++) { 1757 if (j == DBC_PWM_MAX_DUTY && 1758 (sc->sc_chip->flags & DBCFLAG_HAS_MAXDUTY) == 0) 1759 continue; 1760 sysctl_reg = sc->sc_chip->power[i].power_regs[j]; 1761 if (sysctl_reg == DBCOOL_NO_REG) 1762 continue; 1763 strlcpy(name, dbc_sysctl_table[j].name, sizeof(name)); 1764 ret = sysctl_createv(NULL, 0, NULL, 1765 (const struct sysctlnode **)&node, 1766 (dbc_sysctl_table[j].lockable)?ro_flag:rw_flag, 1767 (j == DBC_PWM_BEHAVIOR)? 1768 CTLTYPE_STRING:CTLTYPE_INT, 1769 name, 1770 dbc_sysctl_table[j].desc, 1771 dbc_sysctl_table[j].helper, 1772 0, sc, 1773 ( j == DBC_PWM_BEHAVIOR)? 1774 sizeof(dbcool_cur_behav): sizeof(int), 1775 CTL_HW, me->sysctl_num, me2->sysctl_num, 1776 DBC_PWM_SYSCTL(j, sysctl_reg), CTL_EOL); 1777 if (node != NULL) 1778 node->sysctl_data = sc; 1779 } 1780 } 1781 } 1782 1783 static void 1784 dbcool_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 1785 { 1786 struct dbcool_softc *sc=sme->sme_cookie; 1787 int i, nom_volt_idx; 1788 int cur, hi, low; 1789 struct reg_list *reg; 1790 1791 i = edata->sensor; 1792 reg = sc->sc_regs[i]; 1793 switch (edata->units) 1794 { 1795 case ENVSYS_STEMP: 1796 cur = dbcool_read_temp(sc, reg->val_reg, true); 1797 low = dbcool_read_temp(sc, reg->lo_lim_reg, false); 1798 hi = dbcool_read_temp(sc, reg->hi_lim_reg, false); 1799 break; 1800 case ENVSYS_SVOLTS_DC: 1801 nom_volt_idx = sc->sc_nom_volt[i]; 1802 cur = dbcool_read_volt(sc, reg->val_reg, nom_volt_idx, 1803 true); 1804 low = dbcool_read_volt(sc, reg->lo_lim_reg, 1805 nom_volt_idx, false); 1806 hi = dbcool_read_volt(sc, reg->hi_lim_reg, 1807 nom_volt_idx, false); 1808 break; 1809 case ENVSYS_SFANRPM: 1810 cur = dbcool_read_rpm(sc, reg->val_reg); 1811 low = dbcool_read_rpm(sc, reg->lo_lim_reg); 1812 hi = 1 << 16; 1813 break; 1814 default: 1815 edata->state = ENVSYS_SINVALID; 1816 return; 1817 } 1818 1819 if (cur == 0 && edata->units != ENVSYS_SFANRPM) 1820 edata->state = ENVSYS_SINVALID; 1821 1822 /* Make sure limits are sensible */ 1823 else if (hi <= low) 1824 edata->state = ENVSYS_SVALID; 1825 1826 /* 1827 * If fan is "stalled" but has no low limit, treat 1828 * it as though the fan is not installed. 1829 */ 1830 else if (edata->units == ENVSYS_SFANRPM && cur == 0 && 1831 (low == 0 || low == -1)) 1832 edata->state = ENVSYS_SINVALID; 1833 1834 /* 1835 * Compare current value against the limits 1836 */ 1837 else if (cur < low) 1838 edata->state = ENVSYS_SCRITUNDER; 1839 else if (cur > hi) 1840 edata->state = ENVSYS_SCRITOVER; 1841 else 1842 edata->state = ENVSYS_SVALID; 1843 1844 edata->value_cur = cur; 1845 } 1846 1847 int 1848 dbcool_chip_ident(struct dbcool_softc *sc) 1849 { 1850 /* verify this is a supported dbCool chip */ 1851 uint8_t c_id, d_id, r_id; 1852 int i; 1853 1854 c_id = sc->sc_readreg(sc, DBCOOL_COMPANYID_REG); 1855 d_id = sc->sc_readreg(sc, DBCOOL_DEVICEID_REG); 1856 r_id = sc->sc_readreg(sc, DBCOOL_REVISION_REG); 1857 1858 for (i = 0; chip_table[i].company != 0; i++) 1859 if ((c_id == chip_table[i].company) && 1860 (d_id == chip_table[i].device || 1861 chip_table[i].device == 0xff) && 1862 (r_id == chip_table[i].rev || 1863 chip_table[i].rev == 0xff)) { 1864 sc->sc_chip = &chip_table[i]; 1865 return i; 1866 } 1867 1868 aprint_verbose("dbcool_chip_ident: addr 0x%02x c_id 0x%02x d_id 0x%02x" 1869 " r_id 0x%02x: No match.\n", sc->sc_addr, c_id, d_id, 1870 r_id); 1871 1872 return -1; 1873 } 1874
Indexes created Thu Sep 25 16:09:42 GMT 2025