dbcool.c revision 1.18
1 /* $NetBSD: dbcool.c,v 1.18 2010/03/01 03:14:49 pgoyette Exp $ */ 2 3 /*- 4 * Copyright (c) 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Goyette 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * a driver for the dbCool(tm) family of environmental controllers 34 * 35 * Data sheets for the various supported chips are available at 36 * 37 * http://www.onsemi.com/pub/Collateral/ADM1027-D.PDF 38 * http://www.onsemi.com/pub/Collateral/ADM1030-D.PDF 39 * http://www.onsemi.com/pub/Collateral/ADT7463-D.PDF 40 * http://www.onsemi.com/pub/Collateral/ADT7466.PDF 41 * http://www.onsemi.com/pub/Collateral/ADT7467-D.PDF 42 * http://www.onsemi.com/pub/Collateral/ADT7468-D.PDF 43 * http://www.onsemi.com/pub/Collateral/ADT7473-D.PDF 44 * http://www.onsemi.com/pub/Collateral/ADT7475-D.PDF 45 * http://www.onsemi.com/pub/Collateral/ADT7476-D.PDF 46 * http://www.onsemi.com/pub/Collateral/ADT7490-D.PDF 47 * 48 * (URLs are correct as of October 5, 2008) 49 */ 50 51 #include <sys/cdefs.h> 52 __KERNEL_RCSID(0, "$NetBSD: dbcool.c,v 1.18 2010/03/01 03:14:49 pgoyette Exp $"); 53 54 #include <sys/param.h> 55 #include <sys/systm.h> 56 #include <sys/kernel.h> 57 #include <sys/device.h> 58 #include <sys/malloc.h> 59 #include <sys/sysctl.h> 60 61 #include <uvm/uvm_extern.h> 62 63 #include <dev/i2c/dbcool_var.h> 64 #include <dev/i2c/dbcool_reg.h> 65 66 /* Config interface */ 67 static int dbcool_match(device_t, cfdata_t, void *); 68 static void dbcool_attach(device_t, device_t, void *); 69 static int dbcool_detach(device_t, int); 70 71 /* Device attributes */ 72 static int dbcool_supply_voltage(struct dbcool_softc *); 73 static bool dbcool_islocked(struct dbcool_softc *); 74 75 /* Sensor read functions */ 76 static void dbcool_refresh(struct sysmon_envsys *, envsys_data_t *); 77 static int dbcool_read_rpm(struct dbcool_softc *, uint8_t); 78 static int dbcool_read_temp(struct dbcool_softc *, uint8_t, bool); 79 static int dbcool_read_volt(struct dbcool_softc *, uint8_t, int, bool); 80 81 /* Sensor get/set limit functions */ 82 static void dbcool_get_limits(struct sysmon_envsys *, envsys_data_t *, 83 sysmon_envsys_lim_t *, uint32_t *); 84 static void dbcool_get_temp_limits(struct dbcool_softc *, int, 85 sysmon_envsys_lim_t *, uint32_t *); 86 static void dbcool_get_volt_limits(struct dbcool_softc *, int, 87 sysmon_envsys_lim_t *, uint32_t *); 88 static void dbcool_get_fan_limits(struct dbcool_softc *, int, 89 sysmon_envsys_lim_t *, uint32_t *); 90 91 static void dbcool_set_limits(struct sysmon_envsys *, envsys_data_t *, 92 sysmon_envsys_lim_t *, uint32_t *); 93 static void dbcool_set_temp_limits(struct dbcool_softc *, int, 94 sysmon_envsys_lim_t *, uint32_t *); 95 static void dbcool_set_volt_limits(struct dbcool_softc *, int, 96 sysmon_envsys_lim_t *, uint32_t *); 97 static void dbcool_set_fan_limits(struct dbcool_softc *, int, 98 sysmon_envsys_lim_t *, uint32_t *); 99 100 /* SYSCTL Helpers */ 101 static int sysctl_dbcool_temp(SYSCTLFN_PROTO); 102 static int sysctl_adm1030_temp(SYSCTLFN_PROTO); 103 static int sysctl_adm1030_trange(SYSCTLFN_PROTO); 104 static int sysctl_dbcool_duty(SYSCTLFN_PROTO); 105 static int sysctl_dbcool_behavior(SYSCTLFN_PROTO); 106 static int sysctl_dbcool_slope(SYSCTLFN_PROTO); 107 static int sysctl_dbcool_thyst(SYSCTLFN_PROTO); 108 109 /* Set-up subroutines */ 110 static void dbcool_setup_controllers(struct dbcool_softc *); 111 static int dbcool_setup_sensors(struct dbcool_softc *); 112 static int dbcool_attach_sensor(struct dbcool_softc *, int); 113 static int dbcool_attach_temp_control(struct dbcool_softc *, int, 114 struct chip_id *); 115 116 #ifdef DBCOOL_DEBUG 117 static int sysctl_dbcool_reg_select(SYSCTLFN_PROTO); 118 static int sysctl_dbcool_reg_access(SYSCTLFN_PROTO); 119 #endif /* DBCOOL_DEBUG */ 120 121 /* 122 * Descriptions for SYSCTL entries 123 */ 124 struct dbc_sysctl_info { 125 const char *name; 126 const char *desc; 127 bool lockable; 128 int (*helper)(SYSCTLFN_PROTO); 129 }; 130 131 static struct dbc_sysctl_info dbc_sysctl_table[] = { 132 /* 133 * The first several entries must remain in the same order as the 134 * corresponding entries in enum dbc_pwm_params 135 */ 136 { "behavior", "operating behavior and temp selector", 137 true, sysctl_dbcool_behavior }, 138 { "min_duty", "minimum fan controller PWM duty cycle", 139 true, sysctl_dbcool_duty }, 140 { "max_duty", "maximum fan controller PWM duty cycle", 141 true, sysctl_dbcool_duty }, 142 { "cur_duty", "current fan controller PWM duty cycle", 143 false, sysctl_dbcool_duty }, 144 145 /* 146 * The rest of these should be in the order in which they 147 * are to be stored in the sysctl tree; the table index is 148 * used as the high-order bits of the sysctl_num to maintain 149 * the sequence. 150 * 151 * If you rearrange the order of these items, be sure to 152 * update the sysctl_index in the XXX_sensor_table[] for 153 * the various chips! 154 */ 155 { "Trange", "temp slope/range to reach 100% duty cycle", 156 true, sysctl_dbcool_slope }, 157 { "Tmin", "temp at which to start fan controller", 158 true, sysctl_dbcool_temp }, 159 { "Ttherm", "temp at which THERM is asserted", 160 true, sysctl_dbcool_temp }, 161 { "Thyst", "temp hysteresis for stopping fan controller", 162 true, sysctl_dbcool_thyst }, 163 { "Tmin", "temp at which to start fan controller", 164 true, sysctl_adm1030_temp }, 165 { "Trange", "temp slope/range to reach 100% duty cycle", 166 true, sysctl_adm1030_trange }, 167 }; 168 169 static const char *dbc_sensor_names[] = { 170 "l_temp", "r1_temp", "r2_temp", "Vccp", "Vcc", "fan1", 171 "fan2", "fan3", "fan4", "AIN1", "AIN2", "V2dot5", 172 "V5", "V12", "Vtt", "Imon", "VID" 173 }; 174 175 /* 176 * Following table derived from product data-sheets 177 */ 178 static int64_t nominal_voltages[] = { 179 -1, /* Vcc can be either 3.3 or 5.0V 180 at 3/4 scale */ 181 2249939, /* Vccp 2.25V 3/4 scale */ 182 2497436, /* 2.5VIN 2.5V 3/4 scale */ 183 5002466, /* 5VIN 5V 3/4 scale */ 184 12000000, /* 12VIN 12V 3/4 scale */ 185 1690809, /* Vtt, Imon 2.25V full scale */ 186 1689600, /* AIN1, AIN2 2.25V full scale */ 187 0 188 }; 189 190 /* 191 * Sensor-type, { val-reg, hilim-reg, lolim-reg}, name-idx, sysctl-table-idx, 192 * nom-voltage-index 193 */ 194 struct dbcool_sensor ADT7490_sensor_table[] = { 195 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 196 DBCOOL_LOCAL_HIGHLIM, 197 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 198 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 199 DBCOOL_REMOTE1_HIGHLIM, 200 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 201 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 202 DBCOOL_REMOTE2_HIGHLIM, 203 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 204 { DBC_VOLT, { DBCOOL_VCCP, 205 DBCOOL_VCCP_HIGHLIM, 206 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 207 { DBC_VOLT, { DBCOOL_VCC, 208 DBCOOL_VCC_HIGHLIM, 209 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 210 { DBC_VOLT, { DBCOOL_25VIN, 211 DBCOOL_25VIN_HIGHLIM, 212 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 }, 213 { DBC_VOLT, { DBCOOL_5VIN, 214 DBCOOL_5VIN_HIGHLIM, 215 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 }, 216 { DBC_VOLT, { DBCOOL_12VIN, 217 DBCOOL_12VIN_HIGHLIM, 218 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 }, 219 { DBC_VOLT, { DBCOOL_VTT, 220 DBCOOL_VTT_HIGHLIM, 221 DBCOOL_VTT_LOWLIM }, 14, 0, 5 }, 222 { DBC_VOLT, { DBCOOL_IMON, 223 DBCOOL_IMON_HIGHLIM, 224 DBCOOL_IMON_LOWLIM }, 15, 0, 5 }, 225 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 226 DBCOOL_NO_REG, 227 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 228 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 229 DBCOOL_NO_REG, 230 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 231 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 232 DBCOOL_NO_REG, 233 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 234 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 235 DBCOOL_NO_REG, 236 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 237 { DBC_VID, { DBCOOL_VID_REG, 238 DBCOOL_NO_REG, 239 DBCOOL_NO_REG }, 16, 0, 0 }, 240 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 241 DBCOOL_NO_REG, 242 DBCOOL_NO_REG }, 0, 5, 0 }, 243 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 244 DBCOOL_NO_REG, 245 DBCOOL_NO_REG }, 0, 6, 0 }, 246 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 247 DBCOOL_NO_REG, 248 DBCOOL_NO_REG }, 0, 7, 0 }, 249 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 250 DBCOOL_NO_REG, 251 DBCOOL_NO_REG }, 1, 5, 0 }, 252 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 253 DBCOOL_NO_REG, 254 DBCOOL_NO_REG }, 1, 6, 0 }, 255 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 256 DBCOOL_NO_REG, 257 DBCOOL_NO_REG }, 1, 7, 0 }, 258 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 259 DBCOOL_NO_REG, 260 DBCOOL_NO_REG }, 2, 5, 0 }, 261 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 262 DBCOOL_NO_REG, 263 DBCOOL_NO_REG }, 2, 6, 0 }, 264 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 265 DBCOOL_NO_REG, 266 DBCOOL_NO_REG }, 2, 7, 0 }, 267 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 268 }; 269 270 struct dbcool_sensor ADT7476_sensor_table[] = { 271 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 272 DBCOOL_LOCAL_HIGHLIM, 273 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 274 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 275 DBCOOL_REMOTE1_HIGHLIM, 276 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 277 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 278 DBCOOL_REMOTE2_HIGHLIM, 279 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 280 { DBC_VOLT, { DBCOOL_VCCP, 281 DBCOOL_VCCP_HIGHLIM, 282 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 283 { DBC_VOLT, { DBCOOL_VCC, 284 DBCOOL_VCC_HIGHLIM, 285 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 286 { DBC_VOLT, { DBCOOL_25VIN, 287 DBCOOL_25VIN_HIGHLIM, 288 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 }, 289 { DBC_VOLT, { DBCOOL_5VIN, 290 DBCOOL_5VIN_HIGHLIM, 291 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 }, 292 { DBC_VOLT, { DBCOOL_12VIN, 293 DBCOOL_12VIN_HIGHLIM, 294 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 }, 295 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 296 DBCOOL_NO_REG, 297 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 298 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 299 DBCOOL_NO_REG, 300 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 301 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 302 DBCOOL_NO_REG, 303 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 304 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 305 DBCOOL_NO_REG, 306 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 307 { DBC_VID, { DBCOOL_VID_REG, 308 DBCOOL_NO_REG, 309 DBCOOL_NO_REG }, 16, 0, 0 }, 310 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 311 DBCOOL_NO_REG, 312 DBCOOL_NO_REG }, 0, 5, 0 }, 313 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 314 DBCOOL_NO_REG, 315 DBCOOL_NO_REG }, 0, 6, 0 }, 316 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 317 DBCOOL_NO_REG, 318 DBCOOL_NO_REG }, 0, 7, 0 }, 319 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 320 DBCOOL_NO_REG, 321 DBCOOL_NO_REG }, 1, 5, 0 }, 322 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 323 DBCOOL_NO_REG, 324 DBCOOL_NO_REG }, 1, 6, 0 }, 325 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 326 DBCOOL_NO_REG, 327 DBCOOL_NO_REG }, 1, 7, 0 }, 328 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 329 DBCOOL_NO_REG, 330 DBCOOL_NO_REG }, 2, 5, 0 }, 331 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 332 DBCOOL_NO_REG, 333 DBCOOL_NO_REG }, 2, 6, 0 }, 334 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 335 DBCOOL_NO_REG, 336 DBCOOL_NO_REG }, 2, 7, 0 }, 337 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 338 }; 339 340 struct dbcool_sensor ADT7475_sensor_table[] = { 341 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 342 DBCOOL_LOCAL_HIGHLIM, 343 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 344 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 345 DBCOOL_REMOTE1_HIGHLIM, 346 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 347 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 348 DBCOOL_REMOTE2_HIGHLIM, 349 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 350 { DBC_VOLT, { DBCOOL_VCCP, 351 DBCOOL_VCCP_HIGHLIM, 352 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 353 { DBC_VOLT, { DBCOOL_VCC, 354 DBCOOL_VCC_HIGHLIM, 355 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 356 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 357 DBCOOL_NO_REG, 358 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 359 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 360 DBCOOL_NO_REG, 361 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 362 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 363 DBCOOL_NO_REG, 364 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 365 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 366 DBCOOL_NO_REG, 367 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 368 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 369 DBCOOL_NO_REG, 370 DBCOOL_NO_REG }, 0, 5, 0 }, 371 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 372 DBCOOL_NO_REG, 373 DBCOOL_NO_REG }, 0, 6, 0 }, 374 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 375 DBCOOL_NO_REG, 376 DBCOOL_NO_REG }, 0, 7, 0 }, 377 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 378 DBCOOL_NO_REG, 379 DBCOOL_NO_REG }, 1, 5, 0 }, 380 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 381 DBCOOL_NO_REG, 382 DBCOOL_NO_REG }, 1, 6, 0 }, 383 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 384 DBCOOL_NO_REG, 385 DBCOOL_NO_REG }, 1, 7, 0 }, 386 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 387 DBCOOL_NO_REG, 388 DBCOOL_NO_REG }, 2, 5, 0 }, 389 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 390 DBCOOL_NO_REG, 391 DBCOOL_NO_REG }, 2, 6, 0 }, 392 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 393 DBCOOL_NO_REG, 394 DBCOOL_NO_REG }, 2, 7, 0 }, 395 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 396 }; 397 398 /* 399 * The registers of dbcool_power_control must be in the same order as 400 * in enum dbc_pwm_params 401 */ 402 struct dbcool_power_control ADT7475_power_table[] = { 403 { { DBCOOL_PWM1_CTL, DBCOOL_PWM1_MINDUTY, 404 DBCOOL_PWM1_MAXDUTY, DBCOOL_PWM1_CURDUTY }, 405 "fan_control_1" }, 406 { { DBCOOL_PWM2_CTL, DBCOOL_PWM2_MINDUTY, 407 DBCOOL_PWM2_MAXDUTY, DBCOOL_PWM2_CURDUTY }, 408 "fan_control_2" }, 409 { { DBCOOL_PWM3_CTL, DBCOOL_PWM3_MINDUTY, 410 DBCOOL_PWM3_MAXDUTY, DBCOOL_PWM3_CURDUTY }, 411 "fan_control_3" }, 412 { { 0, 0, 0, 0 }, NULL } 413 }; 414 415 struct dbcool_sensor ADT7466_sensor_table[] = { 416 { DBC_TEMP, { DBCOOL_ADT7466_LCL_TEMP_MSB, 417 DBCOOL_ADT7466_LCL_TEMP_HILIM, 418 DBCOOL_ADT7466_LCL_TEMP_LOLIM }, 0, 0, 0 }, 419 { DBC_TEMP, { DBCOOL_ADT7466_REM_TEMP_MSB, 420 DBCOOL_ADT7466_REM_TEMP_HILIM, 421 DBCOOL_ADT7466_REM_TEMP_LOLIM }, 1, 0, 0 }, 422 { DBC_VOLT, { DBCOOL_ADT7466_VCC, 423 DBCOOL_ADT7466_VCC_HILIM, 424 DBCOOL_ADT7466_VCC_LOLIM }, 4, 0, 0 }, 425 { DBC_VOLT, { DBCOOL_ADT7466_AIN1, 426 DBCOOL_ADT7466_AIN1_HILIM, 427 DBCOOL_ADT7466_AIN1_LOLIM }, 9, 0, 6 }, 428 { DBC_VOLT, { DBCOOL_ADT7466_AIN2, 429 DBCOOL_ADT7466_AIN2_HILIM, 430 DBCOOL_ADT7466_AIN2_LOLIM }, 10, 0, 6 }, 431 { DBC_FAN, { DBCOOL_ADT7466_FANA_LSB, 432 DBCOOL_NO_REG, 433 DBCOOL_ADT7466_FANA_LOLIM_LSB }, 5, 0, 0 }, 434 { DBC_FAN, { DBCOOL_ADT7466_FANB_LSB, 435 DBCOOL_NO_REG, 436 DBCOOL_ADT7466_FANB_LOLIM_LSB }, 6, 0, 0 }, 437 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 438 }; 439 440 struct dbcool_sensor ADM1027_sensor_table[] = { 441 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 442 DBCOOL_LOCAL_HIGHLIM, 443 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 444 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 445 DBCOOL_REMOTE1_HIGHLIM, 446 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 447 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 448 DBCOOL_REMOTE2_HIGHLIM, 449 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 450 { DBC_VOLT, { DBCOOL_VCCP, 451 DBCOOL_VCCP_HIGHLIM, 452 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 453 { DBC_VOLT, { DBCOOL_VCC, 454 DBCOOL_VCC_HIGHLIM, 455 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 456 { DBC_VOLT, { DBCOOL_25VIN, 457 DBCOOL_25VIN_HIGHLIM, 458 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 }, 459 { DBC_VOLT, { DBCOOL_5VIN, 460 DBCOOL_5VIN_HIGHLIM, 461 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 }, 462 { DBC_VOLT, { DBCOOL_12VIN, 463 DBCOOL_12VIN_HIGHLIM, 464 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 }, 465 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 466 DBCOOL_NO_REG, 467 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 468 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 469 DBCOOL_NO_REG, 470 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 471 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 472 DBCOOL_NO_REG, 473 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 474 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 475 DBCOOL_NO_REG, 476 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 477 { DBC_VID, { DBCOOL_VID_REG, 478 DBCOOL_NO_REG, 479 DBCOOL_NO_REG }, 16, 0, 0 }, 480 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 481 DBCOOL_NO_REG, 482 DBCOOL_NO_REG }, 0, 5, 0 }, 483 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 484 DBCOOL_NO_REG, 485 DBCOOL_NO_REG }, 0, 6, 0 }, 486 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 487 DBCOOL_NO_REG, 488 DBCOOL_NO_REG }, 0, 7, 0 }, 489 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 490 DBCOOL_NO_REG, 491 DBCOOL_NO_REG }, 1, 5, 0 }, 492 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 493 DBCOOL_NO_REG, 494 DBCOOL_NO_REG }, 1, 6, 0 }, 495 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 496 DBCOOL_NO_REG, 497 DBCOOL_NO_REG }, 1, 7, 0 }, 498 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 499 DBCOOL_NO_REG, 500 DBCOOL_NO_REG }, 2, 5, 0 }, 501 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 502 DBCOOL_NO_REG, 503 DBCOOL_NO_REG }, 2, 6, 0 }, 504 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 505 DBCOOL_NO_REG, 506 DBCOOL_NO_REG }, 2, 7, 0 }, 507 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 508 }; 509 510 struct dbcool_sensor ADM1030_sensor_table[] = { 511 { DBC_TEMP, { DBCOOL_ADM1030_L_TEMP, 512 DBCOOL_ADM1030_L_HI_LIM, 513 DBCOOL_ADM1030_L_LO_LIM }, 0, 0, 0 }, 514 { DBC_TEMP, { DBCOOL_ADM1030_R_TEMP, 515 DBCOOL_ADM1030_R_HI_LIM, 516 DBCOOL_ADM1030_R_LO_LIM }, 1, 0, 0 }, 517 { DBC_FAN, { DBCOOL_ADM1030_FAN_TACH, 518 DBCOOL_NO_REG, 519 DBCOOL_ADM1030_FAN_LO_LIM }, 5, 0, 0 }, 520 { DBC_CTL, { DBCOOL_ADM1030_L_TMIN, 521 DBCOOL_NO_REG, 522 DBCOOL_NO_REG }, 0, 8, 0 }, 523 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH, 524 DBCOOL_NO_REG, 525 DBCOOL_NO_REG }, 0, 9, 0 }, 526 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH, 527 DBCOOL_NO_REG, 528 DBCOOL_NO_REG }, 0, 6, 0 }, 529 { DBC_CTL, { DBCOOL_ADM1030_R_TMIN, 530 DBCOOL_NO_REG, 531 DBCOOL_NO_REG }, 1, 8, 0 }, 532 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH, 533 DBCOOL_NO_REG, 534 DBCOOL_NO_REG }, 1, 9, 0 }, 535 { DBC_CTL, { DBCOOL_ADM1030_R_TTHRESH, 536 DBCOOL_NO_REG, 537 DBCOOL_NO_REG }, 1, 6, 0 }, 538 { DBC_EOF, {0, 0, 0 }, 0, 0, 0 } 539 }; 540 541 struct dbcool_power_control ADM1030_power_table[] = { 542 { { DBCOOL_ADM1030_CFG1, DBCOOL_NO_REG, DBCOOL_NO_REG, 543 DBCOOL_ADM1030_FAN_SPEED_CFG }, 544 "fan_control_1" }, 545 { { 0, 0, 0, 0 }, NULL } 546 }; 547 548 struct chip_id chip_table[] = { 549 { DBCOOL_COMPANYID, ADT7490_DEVICEID, ADT7490_REV_ID, 550 ADT7490_sensor_table, ADT7475_power_table, 551 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_PECI, 552 90000 * 60, "ADT7490" }, 553 { DBCOOL_COMPANYID, ADT7476_DEVICEID, 0xff, 554 ADT7476_sensor_table, ADT7475_power_table, 555 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY, 556 90000 * 60, "ADT7476" }, 557 { DBCOOL_COMPANYID, ADT7475_DEVICEID, 0xff, 558 ADT7475_sensor_table, ADT7475_power_table, 559 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_SHDN, 560 90000 * 60, "ADT7475" }, 561 { DBCOOL_COMPANYID, ADT7473_DEVICEID, ADT7473_REV_ID1, 562 ADT7475_sensor_table, ADT7475_power_table, 563 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_SHDN, 564 90000 * 60, "ADT7460/ADT7463" }, 565 { DBCOOL_COMPANYID, ADT7473_DEVICEID, ADT7473_REV_ID2, 566 ADT7475_sensor_table, ADT7475_power_table, 567 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_SHDN, 568 90000 * 60, "ADT7463-1" }, 569 { DBCOOL_COMPANYID, ADT7468_DEVICEID, 0xff, 570 ADT7476_sensor_table, ADT7475_power_table, 571 DBCFLAG_TEMPOFFSET | DBCFLAG_MULTI_VCC | DBCFLAG_HAS_MAXDUTY | 572 DBCFLAG_4BIT_VER | DBCFLAG_HAS_SHDN, 573 90000 * 60, "ADT7467/ADT7468" }, 574 { DBCOOL_COMPANYID, ADT7466_DEVICEID, 0xff, 575 ADT7466_sensor_table, NULL, 576 DBCFLAG_ADT7466 | DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_SHDN, 577 82000 * 60, "ADT7466" }, 578 { DBCOOL_COMPANYID, ADT7463_DEVICEID, ADT7463_REV_ID1, 579 ADM1027_sensor_table, ADT7475_power_table, 580 DBCFLAG_MULTI_VCC | DBCFLAG_4BIT_VER | DBCFLAG_HAS_SHDN, 581 90000 * 60, "ADT7463" }, 582 { DBCOOL_COMPANYID, ADT7463_DEVICEID, ADT7463_REV_ID2, 583 ADM1027_sensor_table, ADT7475_power_table, 584 DBCFLAG_MULTI_VCC | DBCFLAG_4BIT_VER | DBCFLAG_HAS_SHDN | 585 DBCFLAG_HAS_VID_SEL, 586 90000 * 60, "ADT7463" }, 587 { DBCOOL_COMPANYID, ADM1027_DEVICEID, ADM1027_REV_ID, 588 ADM1027_sensor_table, ADT7475_power_table, 589 DBCFLAG_MULTI_VCC | DBCFLAG_4BIT_VER, 590 90000 * 60, "ADM1027" }, 591 { DBCOOL_COMPANYID, ADM1030_DEVICEID, 0xff, 592 ADM1030_sensor_table, ADM1030_power_table, 593 DBCFLAG_ADM1030 | DBCFLAG_NO_READBYTE, 594 11250 * 60, "ADM1030" }, 595 { 0, 0, 0, NULL, NULL, 0, 0, NULL } 596 }; 597 598 static const char *behavior[] = { 599 "remote1", "local", "remote2", "full-speed", 600 "disabled", "local+remote2","all-temps", "manual" 601 }; 602 603 static char dbcool_cur_behav[16]; 604 605 CFATTACH_DECL_NEW(dbcool, sizeof(struct dbcool_softc), 606 dbcool_match, dbcool_attach, dbcool_detach, NULL); 607 608 int 609 dbcool_match(device_t parent, cfdata_t cf, void *aux) 610 { 611 struct i2c_attach_args *ia = aux; 612 struct dbcool_chipset dc; 613 dc.dc_tag = ia->ia_tag; 614 dc.dc_addr = ia->ia_addr; 615 dc.dc_chip = NULL; 616 dc.dc_readreg = dbcool_readreg; 617 dc.dc_writereg = dbcool_writereg; 618 619 /* no probing if we attach to iic, but verify chip id and address */ 620 if ((ia->ia_addr & DBCOOL_ADDRMASK) != DBCOOL_ADDR) 621 return 0; 622 if (dbcool_chip_ident(&dc) >= 0) 623 return 1; 624 625 return 0; 626 } 627 628 void 629 dbcool_attach(device_t parent, device_t self, void *aux) 630 { 631 struct dbcool_softc *sc = device_private(self); 632 struct i2c_attach_args *args = aux; 633 uint8_t ver; 634 635 sc->sc_dc.dc_addr = args->ia_addr; 636 sc->sc_dc.dc_tag = args->ia_tag; 637 sc->sc_dc.dc_chip = NULL; 638 sc->sc_dc.dc_readreg = dbcool_readreg; 639 sc->sc_dc.dc_writereg = dbcool_writereg; 640 (void)dbcool_chip_ident(&sc->sc_dc); 641 sc->sc_dev = self; 642 643 aprint_naive("\n"); 644 aprint_normal("\n"); 645 646 ver = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_REVISION_REG); 647 if (sc->sc_dc.dc_chip->flags & DBCFLAG_4BIT_VER) 648 aprint_normal_dev(self, "%s dBCool(tm) Controller " 649 "(rev 0x%02x, stepping 0x%02x)\n", sc->sc_dc.dc_chip->name, 650 ver >> 4, ver & 0x0f); 651 else 652 aprint_normal_dev(self, "%s dBCool(tm) Controller " 653 "(rev 0x%04x)\n", sc->sc_dc.dc_chip->name, ver); 654 655 dbcool_setup(self); 656 657 if (!pmf_device_register(self, dbcool_pmf_suspend, dbcool_pmf_resume)) 658 aprint_error_dev(self, "couldn't establish power handler\n"); 659 } 660 661 static int 662 dbcool_detach(device_t self, int flags) 663 { 664 struct dbcool_softc *sc = device_private(self); 665 666 sysmon_envsys_unregister(sc->sc_sme); 667 sc->sc_sme = NULL; 668 return 0; 669 } 670 671 /* On suspend, we save the state of the SHDN bit, then set it */ 672 bool dbcool_pmf_suspend(device_t dev, const pmf_qual_t *qual) 673 { 674 struct dbcool_softc *sc = device_private(dev); 675 uint8_t reg, bit, cfg; 676 677 if ((sc->sc_dc.dc_chip->flags && DBCFLAG_HAS_SHDN) == 0) 678 return true; 679 680 if (sc->sc_dc.dc_chip->flags && DBCFLAG_ADT7466) { 681 reg = DBCOOL_ADT7466_CONFIG2; 682 bit = DBCOOL_ADT7466_CFG2_SHDN; 683 } else { 684 reg = DBCOOL_CONFIG2_REG; 685 bit = DBCOOL_CFG2_SHDN; 686 } 687 cfg = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 688 sc->sc_suspend = cfg & bit; 689 cfg |= bit; 690 sc->sc_dc.dc_writereg(&sc->sc_dc, reg, cfg); 691 692 return true; 693 } 694 695 /* On resume, we restore the previous state of the SHDN bit */ 696 bool dbcool_pmf_resume(device_t dev, const pmf_qual_t *qual) 697 { 698 struct dbcool_softc *sc = device_private(dev); 699 uint8_t reg, bit, cfg; 700 701 if ((sc->sc_dc.dc_chip->flags && DBCFLAG_HAS_SHDN) == 0) 702 return true; 703 704 if (sc->sc_dc.dc_chip->flags && DBCFLAG_ADT7466) { 705 reg = DBCOOL_ADT7466_CONFIG2; 706 bit = DBCOOL_ADT7466_CFG2_SHDN; 707 } else { 708 reg = DBCOOL_CONFIG2_REG; 709 bit = DBCOOL_CFG2_SHDN; 710 } 711 cfg = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 712 cfg &= ~sc->sc_suspend; 713 sc->sc_dc.dc_writereg(&sc->sc_dc, reg, cfg); 714 715 return true; 716 717 } 718 719 uint8_t 720 dbcool_readreg(struct dbcool_chipset *dc, uint8_t reg) 721 { 722 uint8_t data = 0; 723 724 if (iic_acquire_bus(dc->dc_tag, 0) != 0) 725 return data; 726 727 if (dc->dc_chip == NULL || dc->dc_chip->flags & DBCFLAG_NO_READBYTE) { 728 /* ADM1027 doesn't support i2c read_byte protocol */ 729 if (iic_smbus_send_byte(dc->dc_tag, dc->dc_addr, reg, 0) != 0) 730 goto bad; 731 (void)iic_smbus_receive_byte(dc->dc_tag, dc->dc_addr, &data, 0); 732 } else 733 (void)iic_smbus_read_byte(dc->dc_tag, dc->dc_addr, reg, &data, 734 0); 735 736 bad: 737 iic_release_bus(dc->dc_tag, 0); 738 return data; 739 } 740 741 void 742 dbcool_writereg(struct dbcool_chipset *dc, uint8_t reg, uint8_t val) 743 { 744 if (iic_acquire_bus(dc->dc_tag, 0) != 0) 745 return; 746 747 (void)iic_smbus_write_byte(dc->dc_tag, dc->dc_addr, reg, val, 0); 748 749 iic_release_bus(dc->dc_tag, 0); 750 } 751 752 static bool 753 dbcool_islocked(struct dbcool_softc *sc) 754 { 755 uint8_t cfg_reg; 756 757 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 758 return 0; 759 760 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) 761 cfg_reg = DBCOOL_ADT7466_CONFIG1; 762 else 763 cfg_reg = DBCOOL_CONFIG1_REG; 764 765 if (sc->sc_dc.dc_readreg(&sc->sc_dc, cfg_reg) & DBCOOL_CFG1_LOCK) 766 return 1; 767 else 768 return 0; 769 } 770 771 static int 772 dbcool_read_temp(struct dbcool_softc *sc, uint8_t reg, bool extres) 773 { 774 uint8_t t1, t2, t3, val, ext = 0; 775 int temp; 776 777 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) { 778 /* 779 * ADT7466 temps are in strange location 780 */ 781 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADT7466_CONFIG1); 782 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 783 if (extres) 784 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, reg + 1); 785 } else if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) { 786 /* 787 * ADM1030 temps are in their own special place, too 788 */ 789 if (extres) { 790 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_TEMP_EXTRES); 791 if (reg == DBCOOL_ADM1030_L_TEMP) 792 ext >>= 6; 793 else 794 ext >>= 1; 795 ext &= 0x03; 796 } 797 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 798 } else if (extres) { 799 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES2_REG); 800 801 /* Read all msb regs to unlatch them */ 802 t1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_12VIN); 803 t1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_REMOTE1_TEMP); 804 t2 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_REMOTE2_TEMP); 805 t3 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_LOCAL_TEMP); 806 switch (reg) { 807 case DBCOOL_REMOTE1_TEMP: 808 val = t1; 809 ext >>= 2; 810 break; 811 case DBCOOL_LOCAL_TEMP: 812 val = t3; 813 ext >>= 4; 814 break; 815 case DBCOOL_REMOTE2_TEMP: 816 val = t2; 817 ext >>= 6; 818 break; 819 default: 820 val = 0; 821 break; 822 } 823 ext &= 0x03; 824 } 825 else 826 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 827 828 /* Check for invalid temp values */ 829 if ((sc->sc_temp_offset == 0 && val == 0x80) || 830 (sc->sc_temp_offset != 0 && val == 0)) 831 return 0; 832 833 /* If using offset mode, adjust, else treat as signed */ 834 if (sc->sc_temp_offset) { 835 temp = val; 836 temp -= sc->sc_temp_offset; 837 } else 838 temp = (int8_t)val; 839 840 /* Convert degC to uK and include extended precision bits */ 841 temp *= 1000000; 842 temp += 250000 * (int)ext; 843 temp += 273150000U; 844 845 return temp; 846 } 847 848 static int 849 dbcool_read_rpm(struct dbcool_softc *sc, uint8_t reg) 850 { 851 int rpm; 852 uint8_t rpm_lo, rpm_hi; 853 854 rpm_lo = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 855 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 856 rpm_hi = (rpm_lo == 0xff)?0xff:0x0; 857 else 858 rpm_hi = sc->sc_dc.dc_readreg(&sc->sc_dc, reg + 1); 859 860 rpm = (rpm_hi << 8) | rpm_lo; 861 if (rpm == 0xffff) 862 return 0; /* 0xffff indicates stalled/failed fan */ 863 864 return (sc->sc_dc.dc_chip->rpm_dividend / rpm); 865 } 866 867 /* Provide chip's supply voltage, in microvolts */ 868 static int 869 dbcool_supply_voltage(struct dbcool_softc *sc) 870 { 871 if (sc->sc_dc.dc_chip->flags & DBCFLAG_MULTI_VCC) { 872 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_CONFIG1_REG) & DBCOOL_CFG1_Vcc) 873 return 5002500; 874 else 875 return 3300000; 876 } else if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) { 877 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADT7466_CONFIG1) & 878 DBCOOL_ADT7466_CFG1_Vcc) 879 return 5000000; 880 else 881 return 3300000; 882 } else 883 return 3300000; 884 } 885 886 /* 887 * Nominal voltages are calculated in microvolts 888 */ 889 static int 890 dbcool_read_volt(struct dbcool_softc *sc, uint8_t reg, int nom_idx, bool extres) 891 { 892 uint8_t ext = 0, v1, v2, v3, v4, val; 893 int64_t ret; 894 int64_t nom; 895 896 nom = nominal_voltages[nom_idx]; 897 if (nom < 0) 898 nom = sc->sc_supply_voltage; 899 900 /* ADT7466 voltages are in strange locations with only 8-bits */ 901 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) 902 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 903 else 904 /* 905 * It's a "normal" dbCool chip - check for regs that 906 * share extended resolution bits since we have to 907 * read all the MSB registers to unlatch them. 908 */ 909 if (!extres) 910 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 911 else if (reg == DBCOOL_12VIN) { 912 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES2_REG) && 0x03; 913 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 914 (void)dbcool_read_temp(sc, DBCOOL_LOCAL_TEMP, true); 915 } else if (reg == DBCOOL_VTT || reg == DBCOOL_IMON) { 916 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES_VTT_IMON); 917 v1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_IMON); 918 v2 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VTT); 919 if (reg == DBCOOL_IMON) { 920 val = v1; 921 ext >>= 6; 922 } else 923 val = v2; 924 ext >>= 4; 925 ext &= 0x0f; 926 } else { 927 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES1_REG); 928 v1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_25VIN); 929 v2 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VCCP); 930 v3 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VCC); 931 v4 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_5VIN); 932 933 switch (reg) { 934 case DBCOOL_25VIN: 935 val = v1; 936 break; 937 case DBCOOL_VCCP: 938 val = v2; 939 ext >>= 2; 940 break; 941 case DBCOOL_VCC: 942 val = v3; 943 ext >>= 4; 944 break; 945 case DBCOOL_5VIN: 946 val = v4; 947 ext >>= 6; 948 break; 949 default: 950 val = nom = 0; 951 } 952 ext &= 0x03; 953 } 954 955 /* 956 * Scale the nominal value by the 10-bit fraction 957 * 958 * Returned value is in microvolts. 959 */ 960 ret = val; 961 ret <<= 2; 962 ret |= ext; 963 ret = (ret * nom) / 0x300; 964 965 return ret; 966 } 967 968 SYSCTL_SETUP(sysctl_dbcoolsetup, "sysctl dBCool subtree setup") 969 { 970 sysctl_createv(NULL, 0, NULL, NULL, 971 CTLFLAG_PERMANENT, 972 CTLTYPE_NODE, "hw", NULL, 973 NULL, 0, NULL, 0, 974 CTL_HW, CTL_EOL); 975 } 976 977 static int 978 sysctl_dbcool_temp(SYSCTLFN_ARGS) 979 { 980 struct sysctlnode node; 981 struct dbcool_softc *sc; 982 int reg, error; 983 uint8_t chipreg; 984 uint8_t newreg; 985 986 node = *rnode; 987 sc = (struct dbcool_softc *)node.sysctl_data; 988 chipreg = node.sysctl_num & 0xff; 989 990 if (sc->sc_temp_offset) { 991 reg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 992 reg -= sc->sc_temp_offset; 993 } else 994 reg = (int8_t)sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 995 996 node.sysctl_data = ® 997 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 998 999 if (error || newp == NULL) 1000 return error; 1001 1002 /* We were asked to update the value - sanity check before writing */ 1003 if (*(int *)node.sysctl_data < -64 || 1004 *(int *)node.sysctl_data > 127 + sc->sc_temp_offset) 1005 return EINVAL; 1006 1007 newreg = *(int *)node.sysctl_data; 1008 newreg += sc->sc_temp_offset; 1009 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1010 return 0; 1011 } 1012 1013 static int 1014 sysctl_adm1030_temp(SYSCTLFN_ARGS) 1015 { 1016 struct sysctlnode node; 1017 struct dbcool_softc *sc; 1018 int reg, error; 1019 uint8_t chipreg, oldreg, newreg; 1020 1021 node = *rnode; 1022 sc = (struct dbcool_softc *)node.sysctl_data; 1023 chipreg = node.sysctl_num & 0xff; 1024 1025 oldreg = (int8_t)sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1026 reg = (oldreg >> 1) & ~0x03; 1027 1028 node.sysctl_data = ® 1029 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1030 1031 if (error || newp == NULL) 1032 return error; 1033 1034 /* We were asked to update the value - sanity check before writing */ 1035 if (*(int *)node.sysctl_data < 0 || *(int *)node.sysctl_data > 127) 1036 return EINVAL; 1037 1038 newreg = *(int *)node.sysctl_data; 1039 newreg &= ~0x03; 1040 newreg <<= 1; 1041 newreg |= (oldreg & 0x07); 1042 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1043 return 0; 1044 } 1045 1046 static int 1047 sysctl_adm1030_trange(SYSCTLFN_ARGS) 1048 { 1049 struct sysctlnode node; 1050 struct dbcool_softc *sc; 1051 int reg, error, newval; 1052 uint8_t chipreg, oldreg, newreg; 1053 1054 node = *rnode; 1055 sc = (struct dbcool_softc *)node.sysctl_data; 1056 chipreg = node.sysctl_num & 0xff; 1057 1058 oldreg = (int8_t)sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1059 reg = oldreg & 0x07; 1060 1061 node.sysctl_data = ® 1062 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1063 1064 if (error || newp == NULL) 1065 return error; 1066 1067 /* We were asked to update the value - sanity check before writing */ 1068 newval = *(int *)node.sysctl_data; 1069 1070 if (newval == 5) 1071 newreg = 0; 1072 else if (newval == 10) 1073 newreg = 1; 1074 else if (newval == 20) 1075 newreg = 2; 1076 else if (newval == 40) 1077 newreg = 3; 1078 else if (newval == 80) 1079 newreg = 4; 1080 else 1081 return EINVAL; 1082 1083 newreg |= (oldreg & ~0x07); 1084 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1085 return 0; 1086 } 1087 1088 static int 1089 sysctl_dbcool_duty(SYSCTLFN_ARGS) 1090 { 1091 struct sysctlnode node; 1092 struct dbcool_softc *sc; 1093 int reg, error; 1094 uint8_t chipreg, oldreg, newreg; 1095 1096 node = *rnode; 1097 sc = (struct dbcool_softc *)node.sysctl_data; 1098 chipreg = node.sysctl_num & 0xff; 1099 1100 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1101 reg = (uint32_t)oldreg; 1102 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 1103 reg = ((reg & 0x0f) * 100) / 15; 1104 else 1105 reg = (reg * 100) / 255; 1106 node.sysctl_data = ® 1107 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1108 1109 if (error || newp == NULL) 1110 return error; 1111 1112 /* We were asked to update the value - sanity check before writing */ 1113 if (*(int *)node.sysctl_data < 0 || *(int *)node.sysctl_data > 100) 1114 return EINVAL; 1115 1116 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) { 1117 newreg = *(uint8_t *)(node.sysctl_data) * 15 / 100; 1118 newreg |= oldreg & 0xf0; 1119 } else 1120 newreg = *(uint8_t *)(node.sysctl_data) * 255 / 100; 1121 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1122 return 0; 1123 } 1124 1125 static int 1126 sysctl_dbcool_behavior(SYSCTLFN_ARGS) 1127 { 1128 struct sysctlnode node; 1129 struct dbcool_softc *sc; 1130 int i, reg, error; 1131 uint8_t chipreg, oldreg, newreg; 1132 1133 node = *rnode; 1134 sc = (struct dbcool_softc *)node.sysctl_data; 1135 chipreg = node.sysctl_num & 0xff; 1136 1137 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1138 1139 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) { 1140 if ((sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_CFG2) & 1) == 0) 1141 reg = 4; 1142 else if ((oldreg & 0x80) == 0) 1143 reg = 7; 1144 else if ((oldreg & 0x60) == 0) 1145 reg = 4; 1146 else 1147 reg = 6; 1148 } else 1149 reg = (oldreg >> 5) & 0x07; 1150 1151 strlcpy(dbcool_cur_behav, behavior[reg], sizeof(dbcool_cur_behav)); 1152 node.sysctl_data = dbcool_cur_behav; 1153 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1154 1155 if (error || newp == NULL) 1156 return error; 1157 1158 /* We were asked to update the value - convert string to value */ 1159 newreg = __arraycount(behavior); 1160 for (i = 0; i < __arraycount(behavior); i++) 1161 if (strcmp(node.sysctl_data, behavior[i]) == 0) 1162 break; 1163 if (i >= __arraycount(behavior)) 1164 return EINVAL; 1165 1166 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) { 1167 /* 1168 * ADM1030 splits fan controller behavior across two 1169 * registers. We also do not support Auto-Filter mode 1170 * nor do we support Manual-RPM-feedback. 1171 */ 1172 if (newreg == 4) { 1173 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_CFG2); 1174 oldreg &= ~0x01; 1175 sc->sc_dc.dc_writereg(&sc->sc_dc, DBCOOL_ADM1030_CFG2, oldreg); 1176 } else { 1177 if (newreg == 0) 1178 newreg = 4; 1179 else if (newreg == 6) 1180 newreg = 7; 1181 else if (newreg == 7) 1182 newreg = 0; 1183 else 1184 return EINVAL; 1185 newreg <<= 5; 1186 newreg |= (oldreg & 0x1f); 1187 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1188 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_CFG2) | 1; 1189 sc->sc_dc.dc_writereg(&sc->sc_dc, DBCOOL_ADM1030_CFG2, oldreg); 1190 } 1191 } else { 1192 newreg = (sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg) & 0x1f) | (i << 5); 1193 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1194 } 1195 return 0; 1196 } 1197 1198 static int 1199 sysctl_dbcool_slope(SYSCTLFN_ARGS) 1200 { 1201 struct sysctlnode node; 1202 struct dbcool_softc *sc; 1203 int reg, error; 1204 uint8_t chipreg; 1205 uint8_t newreg; 1206 1207 node = *rnode; 1208 sc = (struct dbcool_softc *)node.sysctl_data; 1209 chipreg = node.sysctl_num & 0xff; 1210 1211 reg = (sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg) >> 4) & 0x0f; 1212 node.sysctl_data = ® 1213 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1214 1215 if (error || newp == NULL) 1216 return error; 1217 1218 /* We were asked to update the value - sanity check before writing */ 1219 if (*(int *)node.sysctl_data < 0 || *(int *)node.sysctl_data > 0x0f) 1220 return EINVAL; 1221 1222 newreg = (sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg) & 0x0f) | 1223 (*(int *)node.sysctl_data << 4); 1224 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1225 return 0; 1226 } 1227 1228 static int 1229 sysctl_dbcool_thyst(SYSCTLFN_ARGS) 1230 { 1231 struct sysctlnode node; 1232 struct dbcool_softc *sc; 1233 int reg, error; 1234 uint8_t chipreg; 1235 uint8_t newreg, newhyst; 1236 1237 node = *rnode; 1238 sc = (struct dbcool_softc *)node.sysctl_data; 1239 chipreg = node.sysctl_num & 0x7f; 1240 1241 /* retrieve 4-bit value */ 1242 newreg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1243 if ((node.sysctl_num & 0x80) == 0) 1244 reg = newreg >> 4; 1245 else 1246 reg = newreg; 1247 reg = reg & 0x0f; 1248 1249 node.sysctl_data = ® 1250 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1251 1252 if (error || newp == NULL) 1253 return error; 1254 1255 /* We were asked to update the value - sanity check before writing */ 1256 newhyst = *(int *)node.sysctl_data; 1257 if (newhyst > 0x0f) 1258 return EINVAL; 1259 1260 /* Insert new value into field and update register */ 1261 if ((node.sysctl_num & 0x80) == 0) { 1262 newreg &= 0x0f; 1263 newreg |= (newhyst << 4); 1264 } else { 1265 newreg &= 0xf0; 1266 newreg |= newhyst; 1267 } 1268 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1269 return 0; 1270 } 1271 1272 #ifdef DBCOOL_DEBUG 1273 1274 /* 1275 * These routines can be used for debugging. reg_select is used to 1276 * select any arbitrary register in the device. reg_access is used 1277 * to read (and optionally update) the selected register. 1278 * 1279 * No attempt is made to validate the data passed. If you use these 1280 * routines, you are assumed to know what you're doing! 1281 * 1282 * Caveat user 1283 */ 1284 static int 1285 sysctl_dbcool_reg_select(SYSCTLFN_ARGS) 1286 { 1287 struct sysctlnode node; 1288 struct dbcool_softc *sc; 1289 int reg, error; 1290 1291 node = *rnode; 1292 sc = (struct dbcool_softc *)node.sysctl_data; 1293 1294 reg = sc->sc_user_reg; 1295 node.sysctl_data = ® 1296 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1297 1298 if (error || newp == NULL) 1299 return error; 1300 1301 sc->sc_user_reg = *(int *)node.sysctl_data; 1302 return 0; 1303 } 1304 1305 static int 1306 sysctl_dbcool_reg_access(SYSCTLFN_ARGS) 1307 { 1308 struct sysctlnode node; 1309 struct dbcool_softc *sc; 1310 int reg, error; 1311 uint8_t chipreg; 1312 uint8_t newreg; 1313 1314 node = *rnode; 1315 sc = (struct dbcool_softc *)node.sysctl_data; 1316 chipreg = sc->sc_user_reg; 1317 1318 reg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1319 node.sysctl_data = ® 1320 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1321 1322 if (error || newp == NULL) 1323 return error; 1324 1325 newreg = *(int *)node.sysctl_data; 1326 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1327 return 0; 1328 } 1329 #endif /* DBCOOL_DEBUG */ 1330 1331 /* 1332 * Encode an index number and register number for use as a sysctl_num 1333 * so we can select the correct device register later. 1334 */ 1335 #define DBC_PWM_SYSCTL(seq, reg) ((seq << 8) | reg) 1336 1337 void 1338 dbcool_setup(device_t self) 1339 { 1340 struct dbcool_softc *sc = device_private(self); 1341 const struct sysctlnode *me = NULL; 1342 #ifdef DBCOOL_DEBUG 1343 struct sysctlnode *node = NULL; 1344 #endif 1345 uint8_t cfg_val, cfg_reg; 1346 int ret, error; 1347 1348 /* 1349 * Some chips are capable of reporting an extended temperature range 1350 * by default. On these models, config register 5 bit 0 can be set 1351 * to 1 for compatability with other chips that report 2s complement. 1352 */ 1353 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) { 1354 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADT7466_CONFIG1) & 0x80) 1355 sc->sc_temp_offset = 64; 1356 else 1357 sc->sc_temp_offset = 0; 1358 } else if (sc->sc_dc.dc_chip->flags & DBCFLAG_TEMPOFFSET) { 1359 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_CONFIG5_REG) & 1360 DBCOOL_CFG5_TWOSCOMP) 1361 sc->sc_temp_offset = 0; 1362 else 1363 sc->sc_temp_offset = 64; 1364 } else 1365 sc->sc_temp_offset = 0; 1366 1367 /* Determine Vcc for this chip */ 1368 sc->sc_supply_voltage = dbcool_supply_voltage(sc); 1369 1370 ret = sysctl_createv(NULL, 0, NULL, &me, 1371 CTLFLAG_READWRITE, 1372 CTLTYPE_NODE, device_xname(self), NULL, 1373 NULL, 0, NULL, 0, 1374 CTL_HW, CTL_CREATE, CTL_EOL); 1375 if (ret == 0) 1376 sc->sc_root_sysctl_num = me->sysctl_num; 1377 else 1378 sc->sc_root_sysctl_num = 0; 1379 1380 /* Create the sensors for this device */ 1381 sc->sc_sme = sysmon_envsys_create(); 1382 if (dbcool_setup_sensors(sc)) 1383 goto out; 1384 1385 if (sc->sc_root_sysctl_num != 0) { 1386 /* If supported, create sysctl tree for fan PWM controllers */ 1387 if (sc->sc_dc.dc_chip->power != NULL) 1388 dbcool_setup_controllers(sc); 1389 1390 #ifdef DBCOOL_DEBUG 1391 ret = sysctl_createv(NULL, 0, NULL, 1392 (const struct sysctlnode **)&node, 1393 CTLFLAG_READWRITE, CTLTYPE_INT, "reg_select", NULL, 1394 sysctl_dbcool_reg_select, 1395 0, sc, sizeof(int), 1396 CTL_HW, me->sysctl_num, CTL_CREATE, CTL_EOL); 1397 if (node != NULL) 1398 node->sysctl_data = sc; 1399 1400 ret = sysctl_createv(NULL, 0, NULL, 1401 (const struct sysctlnode **)&node, 1402 CTLFLAG_READWRITE, CTLTYPE_INT, "reg_access", NULL, 1403 sysctl_dbcool_reg_access, 1404 0, sc, sizeof(int), 1405 CTL_HW, me->sysctl_num, CTL_CREATE, CTL_EOL); 1406 if (node != NULL) 1407 node->sysctl_data = sc; 1408 #endif /* DBCOOL_DEBUG */ 1409 } 1410 1411 /* 1412 * Read and rewrite config register to activate device 1413 */ 1414 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 1415 cfg_reg = DBCOOL_ADM1030_CFG1; 1416 else if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) 1417 cfg_reg = DBCOOL_ADT7466_CONFIG1; 1418 else 1419 cfg_reg = DBCOOL_CONFIG1_REG; 1420 cfg_val = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_CONFIG1_REG); 1421 if ((cfg_val & DBCOOL_CFG1_START) == 0) { 1422 cfg_val |= DBCOOL_CFG1_START; 1423 sc->sc_dc.dc_writereg(&sc->sc_dc, cfg_reg, cfg_val); 1424 } 1425 if (dbcool_islocked(sc)) 1426 aprint_normal_dev(self, "configuration locked\n"); 1427 1428 sc->sc_sme->sme_name = device_xname(self); 1429 sc->sc_sme->sme_cookie = sc; 1430 sc->sc_sme->sme_refresh = dbcool_refresh; 1431 sc->sc_sme->sme_set_limits = dbcool_set_limits; 1432 sc->sc_sme->sme_get_limits = dbcool_get_limits; 1433 1434 if ((error = sysmon_envsys_register(sc->sc_sme)) != 0) { 1435 aprint_error_dev(self, 1436 "unable to register with sysmon (%d)\n", error); 1437 goto out; 1438 } 1439 1440 return; 1441 1442 out: 1443 sysmon_envsys_destroy(sc->sc_sme); 1444 } 1445 1446 static int 1447 dbcool_setup_sensors(struct dbcool_softc *sc) 1448 { 1449 int i; 1450 int error = 0; 1451 uint8_t vid_reg, vid_val; 1452 struct chip_id *chip = sc->sc_dc.dc_chip; 1453 1454 for (i=0; chip->table[i].type != DBC_EOF; i++) { 1455 if (i < DBCOOL_MAXSENSORS) 1456 sc->sc_sysctl_num[i] = -1; 1457 else if (chip->table[i].type != DBC_CTL) { 1458 aprint_normal_dev(sc->sc_dev, "chip table too big!\n"); 1459 break; 1460 } 1461 switch (chip->table[i].type) { 1462 case DBC_TEMP: 1463 sc->sc_sensor[i].units = ENVSYS_STEMP; 1464 sc->sc_sensor[i].flags |= ENVSYS_FMONLIMITS; 1465 error = dbcool_attach_sensor(sc, i); 1466 break; 1467 case DBC_VOLT: 1468 /* 1469 * If 12V-In pin has been reconfigured as 6th bit 1470 * of VID code, don't create a 12V-In sensor 1471 */ 1472 if ((chip->flags & DBCFLAG_HAS_VID_SEL) && 1473 (chip->table[i].reg.val_reg == DBCOOL_12VIN) && 1474 (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VID_REG) & 1475 0x80)) 1476 break; 1477 1478 sc->sc_sensor[i].units = ENVSYS_SVOLTS_DC; 1479 sc->sc_sensor[i].flags |= ENVSYS_FMONLIMITS; 1480 error = dbcool_attach_sensor(sc, i); 1481 break; 1482 case DBC_FAN: 1483 sc->sc_sensor[i].units = ENVSYS_SFANRPM; 1484 sc->sc_sensor[i].flags |= ENVSYS_FMONLIMITS; 1485 error = dbcool_attach_sensor(sc, i); 1486 break; 1487 case DBC_VID: 1488 sc->sc_sensor[i].units = ENVSYS_INTEGER; 1489 sc->sc_sensor[i].flags |= ENVSYS_FMONNOTSUPP; 1490 1491 /* retrieve 5- or 6-bit value */ 1492 vid_reg = chip->table[i].reg.val_reg; 1493 vid_val = sc->sc_dc.dc_readreg(&sc->sc_dc, vid_reg); 1494 if (chip->flags & DBCFLAG_HAS_VID_SEL) 1495 vid_val &= 0x3f; 1496 else 1497 vid_val &= 0x1f; 1498 sc->sc_sensor[i].value_cur = vid_val; 1499 1500 error = dbcool_attach_sensor(sc, i); 1501 break; 1502 case DBC_CTL: 1503 error = dbcool_attach_temp_control(sc, i, chip); 1504 if (error) { 1505 aprint_error_dev(sc->sc_dev, 1506 "attach index %d failed %d\n", 1507 i, error); 1508 error = 0; 1509 } 1510 break; 1511 default: 1512 aprint_error_dev(sc->sc_dev, 1513 "sensor_table index %d has bad type %d\n", 1514 i, chip->table[i].type); 1515 break; 1516 } 1517 if (error) 1518 break; 1519 } 1520 return error; 1521 } 1522 1523 static int 1524 dbcool_attach_sensor(struct dbcool_softc *sc, int idx) 1525 { 1526 int name_index; 1527 int error = 0; 1528 1529 name_index = sc->sc_dc.dc_chip->table[idx].name_index; 1530 strlcpy(sc->sc_sensor[idx].desc, dbc_sensor_names[name_index], 1531 sizeof(sc->sc_sensor[idx].desc)); 1532 sc->sc_regs[idx] = &sc->sc_dc.dc_chip->table[idx].reg; 1533 sc->sc_nom_volt[idx] = sc->sc_dc.dc_chip->table[idx].nom_volt_index; 1534 1535 error = sysmon_envsys_sensor_attach(sc->sc_sme, &sc->sc_sensor[idx]); 1536 return error; 1537 } 1538 1539 static int 1540 dbcool_attach_temp_control(struct dbcool_softc *sc, int idx, 1541 struct chip_id *chip) 1542 { 1543 const struct sysctlnode *me2 = NULL; 1544 struct sysctlnode *node = NULL; 1545 int j, ret, sysctl_index, rw_flag; 1546 uint8_t sysctl_reg; 1547 char name[SYSCTL_NAMELEN]; 1548 1549 /* Search for the corresponding temp sensor */ 1550 for (j = 0; j < idx; j++) { 1551 if (j >= DBCOOL_MAXSENSORS || chip->table[j].type != DBC_TEMP) 1552 continue; 1553 if (chip->table[j].name_index == chip->table[idx].name_index) 1554 break; 1555 } 1556 if (j >= idx) /* Temp sensor not found */ 1557 return ENOENT; 1558 1559 /* create sysctl node for the sensor if not one already there */ 1560 if (sc->sc_sysctl_num[j] == -1) { 1561 ret = sysctl_createv(NULL, 0, NULL, &me2, CTLFLAG_READWRITE, 1562 CTLTYPE_NODE, sc->sc_sensor[j].desc, NULL, 1563 NULL, 0, NULL, 0, 1564 CTL_HW, sc->sc_root_sysctl_num, CTL_CREATE, 1565 CTL_EOL); 1566 if (me2 != NULL) 1567 sc->sc_sysctl_num[j] = me2->sysctl_num; 1568 else 1569 return ret; 1570 } 1571 /* add sysctl leaf node for this control variable */ 1572 sysctl_index = chip->table[idx].sysctl_index; 1573 sysctl_reg = chip->table[idx].reg.val_reg; 1574 strlcpy(name, dbc_sysctl_table[sysctl_index].name, sizeof(name)); 1575 if (dbc_sysctl_table[sysctl_index].lockable && dbcool_islocked(sc)) 1576 rw_flag = CTLFLAG_READONLY | CTLFLAG_OWNDESC; 1577 else 1578 rw_flag = CTLFLAG_READWRITE | CTLFLAG_OWNDESC; 1579 ret = sysctl_createv(NULL, 0, NULL, 1580 (const struct sysctlnode **)&node, rw_flag, 1581 CTLTYPE_INT, name, 1582 dbc_sysctl_table[sysctl_index].desc, 1583 dbc_sysctl_table[sysctl_index].helper, 1584 0, sc, sizeof(int), 1585 CTL_HW, sc->sc_root_sysctl_num, 1586 sc->sc_sysctl_num[j], 1587 DBC_PWM_SYSCTL(idx, sysctl_reg), CTL_EOL); 1588 if (node != NULL) 1589 node->sysctl_data = sc; 1590 1591 return ret; 1592 } 1593 1594 static void 1595 dbcool_setup_controllers(struct dbcool_softc *sc) 1596 { 1597 int i, j, ret, rw_flag; 1598 uint8_t sysctl_reg; 1599 struct chip_id *chip = sc->sc_dc.dc_chip; 1600 const struct sysctlnode *me2 = NULL; 1601 struct sysctlnode *node = NULL; 1602 char name[SYSCTL_NAMELEN]; 1603 1604 for (i = 0; chip->power[i].desc != NULL; i++) { 1605 snprintf(name, sizeof(name), "fan_ctl_%d", i); 1606 ret = sysctl_createv(NULL, 0, NULL, &me2, 1607 CTLFLAG_READWRITE | CTLFLAG_OWNDESC, 1608 CTLTYPE_NODE, name, NULL, 1609 NULL, 0, NULL, 0, 1610 CTL_HW, sc->sc_root_sysctl_num, CTL_CREATE, CTL_EOL); 1611 1612 for (j = DBC_PWM_BEHAVIOR; j < DBC_PWM_LAST_PARAM; j++) { 1613 if (j == DBC_PWM_MAX_DUTY && 1614 (chip->flags & DBCFLAG_HAS_MAXDUTY) == 0) 1615 continue; 1616 sysctl_reg = chip->power[i].power_regs[j]; 1617 if (sysctl_reg == DBCOOL_NO_REG) 1618 continue; 1619 strlcpy(name, dbc_sysctl_table[j].name, sizeof(name)); 1620 if (dbc_sysctl_table[j].lockable && dbcool_islocked(sc)) 1621 rw_flag = CTLFLAG_READONLY | CTLFLAG_OWNDESC; 1622 else 1623 rw_flag = CTLFLAG_READWRITE | CTLFLAG_OWNDESC; 1624 ret = sysctl_createv(NULL, 0, NULL, 1625 (const struct sysctlnode **)&node, rw_flag, 1626 (j == DBC_PWM_BEHAVIOR)? 1627 CTLTYPE_STRING:CTLTYPE_INT, 1628 name, 1629 dbc_sysctl_table[j].desc, 1630 dbc_sysctl_table[j].helper, 1631 0, sc, 1632 ( j == DBC_PWM_BEHAVIOR)? 1633 sizeof(dbcool_cur_behav): sizeof(int), 1634 CTL_HW, sc->sc_root_sysctl_num, me2->sysctl_num, 1635 DBC_PWM_SYSCTL(j, sysctl_reg), CTL_EOL); 1636 if (node != NULL) 1637 node->sysctl_data = sc; 1638 } 1639 } 1640 } 1641 1642 static void 1643 dbcool_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 1644 { 1645 struct dbcool_softc *sc=sme->sme_cookie; 1646 int i, nom_volt_idx, cur; 1647 struct reg_list *reg; 1648 1649 i = edata->sensor; 1650 reg = sc->sc_regs[i]; 1651 1652 edata->state = ENVSYS_SVALID; 1653 switch (edata->units) 1654 { 1655 case ENVSYS_STEMP: 1656 cur = dbcool_read_temp(sc, reg->val_reg, true); 1657 break; 1658 case ENVSYS_SVOLTS_DC: 1659 nom_volt_idx = sc->sc_nom_volt[i]; 1660 cur = dbcool_read_volt(sc, reg->val_reg, nom_volt_idx, 1661 true); 1662 break; 1663 case ENVSYS_SFANRPM: 1664 cur = dbcool_read_rpm(sc, reg->val_reg); 1665 break; 1666 case ENVSYS_INTEGER: 1667 return; 1668 default: 1669 edata->state = ENVSYS_SINVALID; 1670 return; 1671 } 1672 1673 if (cur == 0 && (edata->units != ENVSYS_SFANRPM)) 1674 edata->state = ENVSYS_SINVALID; 1675 1676 /* 1677 * If fan is "stalled" but has no low limit, treat 1678 * it as though the fan is not installed. 1679 */ 1680 else if (edata->units == ENVSYS_SFANRPM && cur == 0 && 1681 !(edata->upropset & (PROP_CRITMIN | PROP_WARNMIN))) 1682 edata->state = ENVSYS_SINVALID; 1683 1684 edata->value_cur = cur; 1685 } 1686 1687 int 1688 dbcool_chip_ident(struct dbcool_chipset *dc) 1689 { 1690 /* verify this is a supported dbCool chip */ 1691 uint8_t c_id, d_id, r_id; 1692 int i; 1693 1694 c_id = dc->dc_readreg(dc, DBCOOL_COMPANYID_REG); 1695 d_id = dc->dc_readreg(dc, DBCOOL_DEVICEID_REG); 1696 r_id = dc->dc_readreg(dc, DBCOOL_REVISION_REG); 1697 1698 for (i = 0; chip_table[i].company != 0; i++) 1699 if ((c_id == chip_table[i].company) && 1700 (d_id == chip_table[i].device || 1701 chip_table[i].device == 0xff) && 1702 (r_id == chip_table[i].rev || 1703 chip_table[i].rev == 0xff)) { 1704 dc->dc_chip = &chip_table[i]; 1705 return i; 1706 } 1707 1708 aprint_verbose("dbcool_chip_ident: addr 0x%02x c_id 0x%02x d_id 0x%02x" 1709 " r_id 0x%02x: No match.\n", dc->dc_addr, c_id, d_id, 1710 r_id); 1711 1712 return -1; 1713 } 1714 1715 /* 1716 * Retrieve sensor limits from the chip registers 1717 */ 1718 static void 1719 dbcool_get_limits(struct sysmon_envsys *sme, envsys_data_t *edata, 1720 sysmon_envsys_lim_t *limits, uint32_t *props) 1721 { 1722 int index = edata->sensor; 1723 struct dbcool_softc *sc = sme->sme_cookie; 1724 1725 switch (edata->units) { 1726 case ENVSYS_STEMP: 1727 dbcool_get_temp_limits(sc, index, limits, props); 1728 break; 1729 case ENVSYS_SVOLTS_DC: 1730 dbcool_get_volt_limits(sc, index, limits, props); 1731 break; 1732 case ENVSYS_SFANRPM: 1733 dbcool_get_fan_limits(sc, index, limits, props); 1734 1735 /* FALLTHROUGH */ 1736 default: 1737 break; 1738 } 1739 *props &= ~PROP_DRIVER_LIMITS; 1740 } 1741 1742 static void 1743 dbcool_get_temp_limits(struct dbcool_softc *sc, int idx, 1744 sysmon_envsys_lim_t *lims, uint32_t *props) 1745 { 1746 struct reg_list *reg = sc->sc_regs[idx]; 1747 int32_t limit; 1748 1749 if (sc->sc_temp_offset) { 1750 limit = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->lo_lim_reg); 1751 limit -= sc->sc_temp_offset; 1752 } else 1753 limit = (int8_t)sc->sc_dc.dc_readreg(&sc->sc_dc, 1754 reg->lo_lim_reg); 1755 1756 if (limit) { 1757 limit *= 1000000; 1758 limit += 273150000; 1759 lims->sel_critmin = limit; 1760 *props |= PROP_CRITMIN; 1761 } else 1762 *props &= ~PROP_CRITMIN; 1763 1764 if (sc->sc_temp_offset) { 1765 limit = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->hi_lim_reg); 1766 limit -= sc->sc_temp_offset; 1767 } else 1768 limit = (int8_t)sc->sc_dc.dc_readreg(&sc->sc_dc, 1769 reg->hi_lim_reg); 1770 if (limit) { 1771 limit *= 1000000; 1772 limit += 273150000; 1773 lims->sel_critmax = limit; 1774 *props |= PROP_CRITMAX; 1775 } else 1776 *props &= ~PROP_CRITMAX; 1777 1778 } 1779 1780 static void 1781 dbcool_get_volt_limits(struct dbcool_softc *sc, int idx, 1782 sysmon_envsys_lim_t *lims, uint32_t *props) 1783 { 1784 struct reg_list *reg = sc->sc_regs[idx]; 1785 int64_t limit; 1786 int nom; 1787 1788 nom = nominal_voltages[sc->sc_dc.dc_chip->table[idx].nom_volt_index]; 1789 if (nom < 0) 1790 nom = dbcool_supply_voltage(sc); 1791 nom *= 1000000; /* scale for microvolts */ 1792 1793 limit = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->lo_lim_reg); 1794 if (limit == 0x00 || limit == 0xff) 1795 *props &= ~PROP_CRITMIN; 1796 else { 1797 limit *= nom; 1798 limit /= 0xc0; 1799 lims->sel_critmin = limit; 1800 *props |= PROP_CRITMIN; 1801 } 1802 limit = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->hi_lim_reg); 1803 if (limit == 0x00 || limit == 0xff) 1804 *props &= ~PROP_CRITMAX; 1805 else { 1806 limit *= nom; 1807 limit /= 0xc0; 1808 lims->sel_critmax = limit; 1809 *props |= PROP_CRITMAX; 1810 } 1811 } 1812 1813 static void 1814 dbcool_get_fan_limits(struct dbcool_softc *sc, int idx, 1815 sysmon_envsys_lim_t *lims, uint32_t *props) 1816 { 1817 struct reg_list *reg = sc->sc_regs[idx]; 1818 int32_t limit; 1819 1820 limit = dbcool_read_rpm(sc, reg->lo_lim_reg); 1821 if (limit) { 1822 lims->sel_critmin = limit; 1823 *props |= PROP_CRITMIN; 1824 } else 1825 *props &= ~PROP_CRITMIN; 1826 } 1827 1828 /* 1829 * Update sensor limits in the chip registers 1830 */ 1831 static void 1832 dbcool_set_limits(struct sysmon_envsys *sme, envsys_data_t *edata, 1833 sysmon_envsys_lim_t *limits, uint32_t *props) 1834 { 1835 int index = edata->sensor; 1836 struct dbcool_softc *sc = sme->sme_cookie; 1837 1838 switch (edata->units) { 1839 case ENVSYS_STEMP: 1840 dbcool_set_temp_limits(sc, index, limits, props); 1841 break; 1842 case ENVSYS_SVOLTS_DC: 1843 dbcool_set_volt_limits(sc, index, limits, props); 1844 break; 1845 case ENVSYS_SFANRPM: 1846 dbcool_set_fan_limits(sc, index, limits, props); 1847 1848 /* FALLTHROUGH */ 1849 default: 1850 break; 1851 } 1852 *props &= ~PROP_DRIVER_LIMITS; 1853 } 1854 1855 static void 1856 dbcool_set_temp_limits(struct dbcool_softc *sc, int idx, 1857 sysmon_envsys_lim_t *lims, uint32_t *props) 1858 { 1859 struct reg_list *reg = sc->sc_regs[idx]; 1860 int32_t limit; 1861 1862 if (*props & PROP_CRITMIN) { 1863 limit = lims->sel_critmin - 273150000; 1864 limit /= 1000000; 1865 limit += sc->sc_temp_offset; 1866 if (limit < 0) 1867 limit = 0; 1868 else if (limit > 0xff) 1869 limit = 0xff; 1870 } else 1871 limit = 0; 1872 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, (uint8_t)limit); 1873 1874 if (*props & PROP_CRITMAX) { 1875 limit = lims->sel_critmax - 273150000; 1876 limit /= 1000000; 1877 limit += sc->sc_temp_offset; 1878 if (limit < 0) 1879 limit = 0; 1880 else if (limit > 0xff) 1881 limit = 0xff; 1882 } else 1883 limit = 0xff; 1884 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg, (uint8_t)limit); 1885 } 1886 1887 static void 1888 dbcool_set_volt_limits(struct dbcool_softc *sc, int idx, 1889 sysmon_envsys_lim_t *lims, uint32_t *props) 1890 { 1891 struct reg_list *reg = sc->sc_regs[idx]; 1892 int64_t limit; 1893 int nom; 1894 1895 nom = nominal_voltages[sc->sc_dc.dc_chip->table[idx].nom_volt_index]; 1896 if (nom < 0) 1897 nom = dbcool_supply_voltage(sc); 1898 nom *= 1000000; /* scale for microvolts */ 1899 1900 if (*props & PROP_CRITMIN) { 1901 limit = lims->sel_critmin; 1902 limit *= 0xc0; 1903 limit /= nom; 1904 if (limit > 0xff) 1905 limit = 0xff; 1906 else if (limit < 0) 1907 limit = 0; 1908 } else 1909 limit = 0; 1910 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, limit); 1911 1912 if (*props & PROP_CRITMAX) { 1913 limit = lims->sel_critmax; 1914 limit *= 0xc0; 1915 limit /= nom; 1916 if (limit > 0xff) 1917 limit = 0xff; 1918 else if (limit < 0) 1919 limit = 0; 1920 } else 1921 limit = 0xff; 1922 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg, limit); 1923 } 1924 1925 static void 1926 dbcool_set_fan_limits(struct dbcool_softc *sc, int idx, 1927 sysmon_envsys_lim_t *lims, uint32_t *props) 1928 { 1929 struct reg_list *reg = sc->sc_regs[idx]; 1930 int32_t limit, dividend; 1931 1932 if (*props & PROP_CRITMIN) { 1933 limit = lims->sel_critmin; 1934 if (limit == 0) 1935 limit = 0xffff; 1936 else { 1937 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 1938 dividend = 11250 * 60; 1939 else 1940 dividend = 90000 * 60; 1941 limit = limit / dividend; 1942 if (limit > 0xffff) 1943 limit = 0xffff; 1944 } 1945 } else 1946 limit = 0xffff; 1947 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, limit & 0xff); 1948 limit >>= 8; 1949 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg + 1, limit & 0xff); 1950 } 1951
Indexes created Wed Sep 24 14:09:57 GMT 2025