dbcool.c revision 1.21
1 /* $NetBSD: dbcool.c,v 1.21 2010/03/31 18:07:13 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Goyette 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * a driver for the dbCool(tm) family of environmental controllers 34 * 35 * Data sheets for the various supported chips are available at 36 * 37 * http://www.onsemi.com/pub/Collateral/ADM1027-D.PDF 38 * http://www.onsemi.com/pub/Collateral/ADM1030-D.PDF 39 * http://www.onsemi.com/pub/Collateral/ADT7463-D.PDF 40 * http://www.onsemi.com/pub/Collateral/ADT7466.PDF 41 * http://www.onsemi.com/pub/Collateral/ADT7467-D.PDF 42 * http://www.onsemi.com/pub/Collateral/ADT7468-D.PDF 43 * http://www.onsemi.com/pub/Collateral/ADT7473-D.PDF 44 * http://www.onsemi.com/pub/Collateral/ADT7475-D.PDF 45 * http://www.onsemi.com/pub/Collateral/ADT7476-D.PDF 46 * http://www.onsemi.com/pub/Collateral/ADT7490-D.PDF 47 * 48 * (URLs are correct as of October 5, 2008) 49 */ 50 51 #include <sys/cdefs.h> 52 __KERNEL_RCSID(0, "$NetBSD: dbcool.c,v 1.21 2010/03/31 18:07:13 macallan Exp $"); 53 54 #include <sys/param.h> 55 #include <sys/systm.h> 56 #include <sys/kernel.h> 57 #include <sys/device.h> 58 #include <sys/malloc.h> 59 #include <sys/sysctl.h> 60 61 #include <uvm/uvm_extern.h> 62 63 #include <dev/i2c/dbcool_var.h> 64 #include <dev/i2c/dbcool_reg.h> 65 66 /* Config interface */ 67 static int dbcool_match(device_t, cfdata_t, void *); 68 static void dbcool_attach(device_t, device_t, void *); 69 static int dbcool_detach(device_t, int); 70 71 /* Device attributes */ 72 static int dbcool_supply_voltage(struct dbcool_softc *); 73 static bool dbcool_islocked(struct dbcool_softc *); 74 75 /* Sensor read functions */ 76 static void dbcool_refresh(struct sysmon_envsys *, envsys_data_t *); 77 static int dbcool_read_rpm(struct dbcool_softc *, uint8_t); 78 static int dbcool_read_temp(struct dbcool_softc *, uint8_t, bool); 79 static int dbcool_read_volt(struct dbcool_softc *, uint8_t, int, bool); 80 81 /* Sensor get/set limit functions */ 82 static void dbcool_get_limits(struct sysmon_envsys *, envsys_data_t *, 83 sysmon_envsys_lim_t *, uint32_t *); 84 static void dbcool_get_temp_limits(struct dbcool_softc *, int, 85 sysmon_envsys_lim_t *, uint32_t *); 86 static void dbcool_get_volt_limits(struct dbcool_softc *, int, 87 sysmon_envsys_lim_t *, uint32_t *); 88 static void dbcool_get_fan_limits(struct dbcool_softc *, int, 89 sysmon_envsys_lim_t *, uint32_t *); 90 91 static void dbcool_set_limits(struct sysmon_envsys *, envsys_data_t *, 92 sysmon_envsys_lim_t *, uint32_t *); 93 static void dbcool_set_temp_limits(struct dbcool_softc *, int, 94 sysmon_envsys_lim_t *, uint32_t *); 95 static void dbcool_set_volt_limits(struct dbcool_softc *, int, 96 sysmon_envsys_lim_t *, uint32_t *); 97 static void dbcool_set_fan_limits(struct dbcool_softc *, int, 98 sysmon_envsys_lim_t *, uint32_t *); 99 100 /* SYSCTL Helpers */ 101 static int sysctl_dbcool_temp(SYSCTLFN_PROTO); 102 static int sysctl_adm1030_temp(SYSCTLFN_PROTO); 103 static int sysctl_adm1030_trange(SYSCTLFN_PROTO); 104 static int sysctl_dbcool_duty(SYSCTLFN_PROTO); 105 static int sysctl_dbcool_behavior(SYSCTLFN_PROTO); 106 static int sysctl_dbcool_slope(SYSCTLFN_PROTO); 107 static int sysctl_dbcool_thyst(SYSCTLFN_PROTO); 108 109 /* Set-up subroutines */ 110 static void dbcool_setup_controllers(struct dbcool_softc *); 111 static int dbcool_setup_sensors(struct dbcool_softc *); 112 static int dbcool_attach_sensor(struct dbcool_softc *, int); 113 static int dbcool_attach_temp_control(struct dbcool_softc *, int, 114 struct chip_id *); 115 116 #ifdef DBCOOL_DEBUG 117 static int sysctl_dbcool_reg_select(SYSCTLFN_PROTO); 118 static int sysctl_dbcool_reg_access(SYSCTLFN_PROTO); 119 #endif /* DBCOOL_DEBUG */ 120 121 /* 122 * Descriptions for SYSCTL entries 123 */ 124 struct dbc_sysctl_info { 125 const char *name; 126 const char *desc; 127 bool lockable; 128 int (*helper)(SYSCTLFN_PROTO); 129 }; 130 131 static struct dbc_sysctl_info dbc_sysctl_table[] = { 132 /* 133 * The first several entries must remain in the same order as the 134 * corresponding entries in enum dbc_pwm_params 135 */ 136 { "behavior", "operating behavior and temp selector", 137 true, sysctl_dbcool_behavior }, 138 { "min_duty", "minimum fan controller PWM duty cycle", 139 true, sysctl_dbcool_duty }, 140 { "max_duty", "maximum fan controller PWM duty cycle", 141 true, sysctl_dbcool_duty }, 142 { "cur_duty", "current fan controller PWM duty cycle", 143 false, sysctl_dbcool_duty }, 144 145 /* 146 * The rest of these should be in the order in which they 147 * are to be stored in the sysctl tree; the table index is 148 * used as the high-order bits of the sysctl_num to maintain 149 * the sequence. 150 * 151 * If you rearrange the order of these items, be sure to 152 * update the sysctl_index in the XXX_sensor_table[] for 153 * the various chips! 154 */ 155 { "Trange", "temp slope/range to reach 100% duty cycle", 156 true, sysctl_dbcool_slope }, 157 { "Tmin", "temp at which to start fan controller", 158 true, sysctl_dbcool_temp }, 159 { "Ttherm", "temp at which THERM is asserted", 160 true, sysctl_dbcool_temp }, 161 { "Thyst", "temp hysteresis for stopping fan controller", 162 true, sysctl_dbcool_thyst }, 163 { "Tmin", "temp at which to start fan controller", 164 true, sysctl_adm1030_temp }, 165 { "Trange", "temp slope/range to reach 100% duty cycle", 166 true, sysctl_adm1030_trange }, 167 }; 168 169 static const char *dbc_sensor_names[] = { 170 "l_temp", "r1_temp", "r2_temp", "Vccp", "Vcc", "fan1", 171 "fan2", "fan3", "fan4", "AIN1", "AIN2", "V2dot5", 172 "V5", "V12", "Vtt", "Imon", "VID" 173 }; 174 175 /* 176 * Following table derived from product data-sheets 177 */ 178 static int64_t nominal_voltages[] = { 179 -1, /* Vcc can be either 3.3 or 5.0V 180 at 3/4 scale */ 181 2249939, /* Vccp 2.25V 3/4 scale */ 182 2497436, /* 2.5VIN 2.5V 3/4 scale */ 183 5002466, /* 5VIN 5V 3/4 scale */ 184 12000000, /* 12VIN 12V 3/4 scale */ 185 1690809, /* Vtt, Imon 2.25V full scale */ 186 1689600, /* AIN1, AIN2 2.25V full scale */ 187 0 188 }; 189 190 /* 191 * Sensor-type, { val-reg, hilim-reg, lolim-reg}, name-idx, sysctl-table-idx, 192 * nom-voltage-index 193 */ 194 struct dbcool_sensor ADT7490_sensor_table[] = { 195 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 196 DBCOOL_LOCAL_HIGHLIM, 197 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 198 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 199 DBCOOL_REMOTE1_HIGHLIM, 200 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 201 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 202 DBCOOL_REMOTE2_HIGHLIM, 203 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 204 { DBC_VOLT, { DBCOOL_VCCP, 205 DBCOOL_VCCP_HIGHLIM, 206 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 207 { DBC_VOLT, { DBCOOL_VCC, 208 DBCOOL_VCC_HIGHLIM, 209 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 210 { DBC_VOLT, { DBCOOL_25VIN, 211 DBCOOL_25VIN_HIGHLIM, 212 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 }, 213 { DBC_VOLT, { DBCOOL_5VIN, 214 DBCOOL_5VIN_HIGHLIM, 215 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 }, 216 { DBC_VOLT, { DBCOOL_12VIN, 217 DBCOOL_12VIN_HIGHLIM, 218 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 }, 219 { DBC_VOLT, { DBCOOL_VTT, 220 DBCOOL_VTT_HIGHLIM, 221 DBCOOL_VTT_LOWLIM }, 14, 0, 5 }, 222 { DBC_VOLT, { DBCOOL_IMON, 223 DBCOOL_IMON_HIGHLIM, 224 DBCOOL_IMON_LOWLIM }, 15, 0, 5 }, 225 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 226 DBCOOL_NO_REG, 227 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 228 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 229 DBCOOL_NO_REG, 230 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 231 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 232 DBCOOL_NO_REG, 233 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 234 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 235 DBCOOL_NO_REG, 236 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 237 { DBC_VID, { DBCOOL_VID_REG, 238 DBCOOL_NO_REG, 239 DBCOOL_NO_REG }, 16, 0, 0 }, 240 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 241 DBCOOL_NO_REG, 242 DBCOOL_NO_REG }, 0, 5, 0 }, 243 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 244 DBCOOL_NO_REG, 245 DBCOOL_NO_REG }, 0, 6, 0 }, 246 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 247 DBCOOL_NO_REG, 248 DBCOOL_NO_REG }, 0, 7, 0 }, 249 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 250 DBCOOL_NO_REG, 251 DBCOOL_NO_REG }, 1, 5, 0 }, 252 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 253 DBCOOL_NO_REG, 254 DBCOOL_NO_REG }, 1, 6, 0 }, 255 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 256 DBCOOL_NO_REG, 257 DBCOOL_NO_REG }, 1, 7, 0 }, 258 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 259 DBCOOL_NO_REG, 260 DBCOOL_NO_REG }, 2, 5, 0 }, 261 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 262 DBCOOL_NO_REG, 263 DBCOOL_NO_REG }, 2, 6, 0 }, 264 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 265 DBCOOL_NO_REG, 266 DBCOOL_NO_REG }, 2, 7, 0 }, 267 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 268 }; 269 270 struct dbcool_sensor ADT7476_sensor_table[] = { 271 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 272 DBCOOL_LOCAL_HIGHLIM, 273 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 274 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 275 DBCOOL_REMOTE1_HIGHLIM, 276 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 277 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 278 DBCOOL_REMOTE2_HIGHLIM, 279 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 280 { DBC_VOLT, { DBCOOL_VCCP, 281 DBCOOL_VCCP_HIGHLIM, 282 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 283 { DBC_VOLT, { DBCOOL_VCC, 284 DBCOOL_VCC_HIGHLIM, 285 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 286 { DBC_VOLT, { DBCOOL_25VIN, 287 DBCOOL_25VIN_HIGHLIM, 288 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 }, 289 { DBC_VOLT, { DBCOOL_5VIN, 290 DBCOOL_5VIN_HIGHLIM, 291 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 }, 292 { DBC_VOLT, { DBCOOL_12VIN, 293 DBCOOL_12VIN_HIGHLIM, 294 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 }, 295 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 296 DBCOOL_NO_REG, 297 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 298 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 299 DBCOOL_NO_REG, 300 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 301 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 302 DBCOOL_NO_REG, 303 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 304 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 305 DBCOOL_NO_REG, 306 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 307 { DBC_VID, { DBCOOL_VID_REG, 308 DBCOOL_NO_REG, 309 DBCOOL_NO_REG }, 16, 0, 0 }, 310 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 311 DBCOOL_NO_REG, 312 DBCOOL_NO_REG }, 0, 5, 0 }, 313 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 314 DBCOOL_NO_REG, 315 DBCOOL_NO_REG }, 0, 6, 0 }, 316 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 317 DBCOOL_NO_REG, 318 DBCOOL_NO_REG }, 0, 7, 0 }, 319 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 320 DBCOOL_NO_REG, 321 DBCOOL_NO_REG }, 1, 5, 0 }, 322 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 323 DBCOOL_NO_REG, 324 DBCOOL_NO_REG }, 1, 6, 0 }, 325 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 326 DBCOOL_NO_REG, 327 DBCOOL_NO_REG }, 1, 7, 0 }, 328 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 329 DBCOOL_NO_REG, 330 DBCOOL_NO_REG }, 2, 5, 0 }, 331 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 332 DBCOOL_NO_REG, 333 DBCOOL_NO_REG }, 2, 6, 0 }, 334 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 335 DBCOOL_NO_REG, 336 DBCOOL_NO_REG }, 2, 7, 0 }, 337 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 338 }; 339 340 struct dbcool_sensor ADT7475_sensor_table[] = { 341 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 342 DBCOOL_LOCAL_HIGHLIM, 343 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 344 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 345 DBCOOL_REMOTE1_HIGHLIM, 346 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 347 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 348 DBCOOL_REMOTE2_HIGHLIM, 349 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 350 { DBC_VOLT, { DBCOOL_VCCP, 351 DBCOOL_VCCP_HIGHLIM, 352 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 353 { DBC_VOLT, { DBCOOL_VCC, 354 DBCOOL_VCC_HIGHLIM, 355 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 356 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 357 DBCOOL_NO_REG, 358 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 359 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 360 DBCOOL_NO_REG, 361 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 362 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 363 DBCOOL_NO_REG, 364 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 365 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 366 DBCOOL_NO_REG, 367 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 368 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 369 DBCOOL_NO_REG, 370 DBCOOL_NO_REG }, 0, 5, 0 }, 371 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 372 DBCOOL_NO_REG, 373 DBCOOL_NO_REG }, 0, 6, 0 }, 374 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 375 DBCOOL_NO_REG, 376 DBCOOL_NO_REG }, 0, 7, 0 }, 377 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 378 DBCOOL_NO_REG, 379 DBCOOL_NO_REG }, 1, 5, 0 }, 380 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 381 DBCOOL_NO_REG, 382 DBCOOL_NO_REG }, 1, 6, 0 }, 383 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 384 DBCOOL_NO_REG, 385 DBCOOL_NO_REG }, 1, 7, 0 }, 386 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 387 DBCOOL_NO_REG, 388 DBCOOL_NO_REG }, 2, 5, 0 }, 389 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 390 DBCOOL_NO_REG, 391 DBCOOL_NO_REG }, 2, 6, 0 }, 392 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 393 DBCOOL_NO_REG, 394 DBCOOL_NO_REG }, 2, 7, 0 }, 395 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 396 }; 397 398 /* 399 * The registers of dbcool_power_control must be in the same order as 400 * in enum dbc_pwm_params 401 */ 402 struct dbcool_power_control ADT7475_power_table[] = { 403 { { DBCOOL_PWM1_CTL, DBCOOL_PWM1_MINDUTY, 404 DBCOOL_PWM1_MAXDUTY, DBCOOL_PWM1_CURDUTY }, 405 "fan_control_1" }, 406 { { DBCOOL_PWM2_CTL, DBCOOL_PWM2_MINDUTY, 407 DBCOOL_PWM2_MAXDUTY, DBCOOL_PWM2_CURDUTY }, 408 "fan_control_2" }, 409 { { DBCOOL_PWM3_CTL, DBCOOL_PWM3_MINDUTY, 410 DBCOOL_PWM3_MAXDUTY, DBCOOL_PWM3_CURDUTY }, 411 "fan_control_3" }, 412 { { 0, 0, 0, 0 }, NULL } 413 }; 414 415 struct dbcool_sensor ADT7466_sensor_table[] = { 416 { DBC_TEMP, { DBCOOL_ADT7466_LCL_TEMP_MSB, 417 DBCOOL_ADT7466_LCL_TEMP_HILIM, 418 DBCOOL_ADT7466_LCL_TEMP_LOLIM }, 0, 0, 0 }, 419 { DBC_TEMP, { DBCOOL_ADT7466_REM_TEMP_MSB, 420 DBCOOL_ADT7466_REM_TEMP_HILIM, 421 DBCOOL_ADT7466_REM_TEMP_LOLIM }, 1, 0, 0 }, 422 { DBC_VOLT, { DBCOOL_ADT7466_VCC, 423 DBCOOL_ADT7466_VCC_HILIM, 424 DBCOOL_ADT7466_VCC_LOLIM }, 4, 0, 0 }, 425 { DBC_VOLT, { DBCOOL_ADT7466_AIN1, 426 DBCOOL_ADT7466_AIN1_HILIM, 427 DBCOOL_ADT7466_AIN1_LOLIM }, 9, 0, 6 }, 428 { DBC_VOLT, { DBCOOL_ADT7466_AIN2, 429 DBCOOL_ADT7466_AIN2_HILIM, 430 DBCOOL_ADT7466_AIN2_LOLIM }, 10, 0, 6 }, 431 { DBC_FAN, { DBCOOL_ADT7466_FANA_LSB, 432 DBCOOL_NO_REG, 433 DBCOOL_ADT7466_FANA_LOLIM_LSB }, 5, 0, 0 }, 434 { DBC_FAN, { DBCOOL_ADT7466_FANB_LSB, 435 DBCOOL_NO_REG, 436 DBCOOL_ADT7466_FANB_LOLIM_LSB }, 6, 0, 0 }, 437 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 438 }; 439 440 struct dbcool_sensor ADM1027_sensor_table[] = { 441 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 442 DBCOOL_LOCAL_HIGHLIM, 443 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 444 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 445 DBCOOL_REMOTE1_HIGHLIM, 446 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 447 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 448 DBCOOL_REMOTE2_HIGHLIM, 449 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 450 { DBC_VOLT, { DBCOOL_VCCP, 451 DBCOOL_VCCP_HIGHLIM, 452 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 453 { DBC_VOLT, { DBCOOL_VCC, 454 DBCOOL_VCC_HIGHLIM, 455 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 456 { DBC_VOLT, { DBCOOL_25VIN, 457 DBCOOL_25VIN_HIGHLIM, 458 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 }, 459 { DBC_VOLT, { DBCOOL_5VIN, 460 DBCOOL_5VIN_HIGHLIM, 461 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 }, 462 { DBC_VOLT, { DBCOOL_12VIN, 463 DBCOOL_12VIN_HIGHLIM, 464 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 }, 465 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 466 DBCOOL_NO_REG, 467 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 468 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 469 DBCOOL_NO_REG, 470 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 471 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 472 DBCOOL_NO_REG, 473 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 474 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 475 DBCOOL_NO_REG, 476 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 477 { DBC_VID, { DBCOOL_VID_REG, 478 DBCOOL_NO_REG, 479 DBCOOL_NO_REG }, 16, 0, 0 }, 480 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 481 DBCOOL_NO_REG, 482 DBCOOL_NO_REG }, 0, 5, 0 }, 483 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 484 DBCOOL_NO_REG, 485 DBCOOL_NO_REG }, 0, 6, 0 }, 486 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 487 DBCOOL_NO_REG, 488 DBCOOL_NO_REG }, 0, 7, 0 }, 489 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 490 DBCOOL_NO_REG, 491 DBCOOL_NO_REG }, 1, 5, 0 }, 492 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 493 DBCOOL_NO_REG, 494 DBCOOL_NO_REG }, 1, 6, 0 }, 495 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 496 DBCOOL_NO_REG, 497 DBCOOL_NO_REG }, 1, 7, 0 }, 498 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 499 DBCOOL_NO_REG, 500 DBCOOL_NO_REG }, 2, 5, 0 }, 501 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 502 DBCOOL_NO_REG, 503 DBCOOL_NO_REG }, 2, 6, 0 }, 504 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 505 DBCOOL_NO_REG, 506 DBCOOL_NO_REG }, 2, 7, 0 }, 507 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 508 }; 509 510 struct dbcool_sensor ADM1030_sensor_table[] = { 511 { DBC_TEMP, { DBCOOL_ADM1030_L_TEMP, 512 DBCOOL_ADM1030_L_HI_LIM, 513 DBCOOL_ADM1030_L_LO_LIM }, 0, 0, 0 }, 514 { DBC_TEMP, { DBCOOL_ADM1030_R_TEMP, 515 DBCOOL_ADM1030_R_HI_LIM, 516 DBCOOL_ADM1030_R_LO_LIM }, 1, 0, 0 }, 517 { DBC_FAN, { DBCOOL_ADM1030_FAN_TACH, 518 DBCOOL_NO_REG, 519 DBCOOL_ADM1030_FAN_LO_LIM }, 5, 0, 0 }, 520 { DBC_CTL, { DBCOOL_ADM1030_L_TMIN, 521 DBCOOL_NO_REG, 522 DBCOOL_NO_REG }, 0, 8, 0 }, 523 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH, 524 DBCOOL_NO_REG, 525 DBCOOL_NO_REG }, 0, 9, 0 }, 526 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH, 527 DBCOOL_NO_REG, 528 DBCOOL_NO_REG }, 0, 6, 0 }, 529 { DBC_CTL, { DBCOOL_ADM1030_R_TMIN, 530 DBCOOL_NO_REG, 531 DBCOOL_NO_REG }, 1, 8, 0 }, 532 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH, 533 DBCOOL_NO_REG, 534 DBCOOL_NO_REG }, 1, 9, 0 }, 535 { DBC_CTL, { DBCOOL_ADM1030_R_TTHRESH, 536 DBCOOL_NO_REG, 537 DBCOOL_NO_REG }, 1, 6, 0 }, 538 { DBC_EOF, {0, 0, 0 }, 0, 0, 0 } 539 }; 540 541 struct dbcool_power_control ADM1030_power_table[] = { 542 { { DBCOOL_ADM1030_CFG1, DBCOOL_NO_REG, DBCOOL_NO_REG, 543 DBCOOL_ADM1030_FAN_SPEED_CFG }, 544 "fan_control_1" }, 545 { { 0, 0, 0, 0 }, NULL } 546 }; 547 548 struct chip_id chip_table[] = { 549 { DBCOOL_COMPANYID, ADT7490_DEVICEID, ADT7490_REV_ID, 550 ADT7490_sensor_table, ADT7475_power_table, 551 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_PECI, 552 90000 * 60, "ADT7490" }, 553 { DBCOOL_COMPANYID, ADT7476_DEVICEID, 0xff, 554 ADT7476_sensor_table, ADT7475_power_table, 555 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY, 556 90000 * 60, "ADT7476" }, 557 { DBCOOL_COMPANYID, ADT7475_DEVICEID, 0xff, 558 ADT7475_sensor_table, ADT7475_power_table, 559 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_SHDN, 560 90000 * 60, "ADT7475" }, 561 { DBCOOL_COMPANYID, ADT7473_DEVICEID, ADT7473_REV_ID1, 562 ADT7475_sensor_table, ADT7475_power_table, 563 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_SHDN, 564 90000 * 60, "ADT7460/ADT7463" }, 565 { DBCOOL_COMPANYID, ADT7473_DEVICEID, ADT7473_REV_ID2, 566 ADT7475_sensor_table, ADT7475_power_table, 567 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_SHDN, 568 90000 * 60, "ADT7463-1" }, 569 { DBCOOL_COMPANYID, ADT7468_DEVICEID, 0xff, 570 ADT7476_sensor_table, ADT7475_power_table, 571 DBCFLAG_TEMPOFFSET | DBCFLAG_MULTI_VCC | DBCFLAG_HAS_MAXDUTY | 572 DBCFLAG_4BIT_VER | DBCFLAG_HAS_SHDN, 573 90000 * 60, "ADT7467/ADT7468" }, 574 { DBCOOL_COMPANYID, ADT7466_DEVICEID, 0xff, 575 ADT7466_sensor_table, NULL, 576 DBCFLAG_ADT7466 | DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_SHDN, 577 82000 * 60, "ADT7466" }, 578 { DBCOOL_COMPANYID, ADT7463_DEVICEID, ADT7463_REV_ID1, 579 ADM1027_sensor_table, ADT7475_power_table, 580 DBCFLAG_MULTI_VCC | DBCFLAG_4BIT_VER | DBCFLAG_HAS_SHDN, 581 90000 * 60, "ADT7463" }, 582 { DBCOOL_COMPANYID, ADT7463_DEVICEID, ADT7463_REV_ID2, 583 ADM1027_sensor_table, ADT7475_power_table, 584 DBCFLAG_MULTI_VCC | DBCFLAG_4BIT_VER | DBCFLAG_HAS_SHDN | 585 DBCFLAG_HAS_VID_SEL, 586 90000 * 60, "ADT7463" }, 587 { DBCOOL_COMPANYID, ADM1027_DEVICEID, ADM1027_REV_ID, 588 ADM1027_sensor_table, ADT7475_power_table, 589 DBCFLAG_MULTI_VCC | DBCFLAG_4BIT_VER, 590 90000 * 60, "ADM1027" }, 591 { DBCOOL_COMPANYID, ADM1030_DEVICEID, 0xff, 592 ADM1030_sensor_table, ADM1030_power_table, 593 DBCFLAG_ADM1030 | DBCFLAG_NO_READBYTE, 594 11250 * 60, "ADM1030" }, 595 { DBCOOL_COMPANYID, ADM1031_DEVICEID, 0xff, 596 ADM1030_sensor_table, ADM1030_power_table, 597 DBCFLAG_ADM1030 | DBCFLAG_NO_READBYTE, 598 11250 * 60, "ADM1031" }, 599 { 0, 0, 0, NULL, NULL, 0, 0, NULL } 600 }; 601 602 static const char *behavior[] = { 603 "remote1", "local", "remote2", "full-speed", 604 "disabled", "local+remote2","all-temps", "manual" 605 }; 606 607 static char dbcool_cur_behav[16]; 608 609 CFATTACH_DECL_NEW(dbcool, sizeof(struct dbcool_softc), 610 dbcool_match, dbcool_attach, dbcool_detach, NULL); 611 612 int 613 dbcool_match(device_t parent, cfdata_t cf, void *aux) 614 { 615 struct i2c_attach_args *ia = aux; 616 struct dbcool_chipset dc; 617 dc.dc_tag = ia->ia_tag; 618 dc.dc_addr = ia->ia_addr; 619 dc.dc_chip = NULL; 620 dc.dc_readreg = dbcool_readreg; 621 dc.dc_writereg = dbcool_writereg; 622 623 /* no probing if we attach to iic, but verify chip id and address */ 624 if ((ia->ia_addr & DBCOOL_ADDRMASK) != DBCOOL_ADDR) 625 return 0; 626 if (dbcool_chip_ident(&dc) >= 0) 627 return 1; 628 629 return 0; 630 } 631 632 void 633 dbcool_attach(device_t parent, device_t self, void *aux) 634 { 635 struct dbcool_softc *sc = device_private(self); 636 struct i2c_attach_args *args = aux; 637 uint8_t ver; 638 639 sc->sc_dc.dc_addr = args->ia_addr; 640 sc->sc_dc.dc_tag = args->ia_tag; 641 sc->sc_dc.dc_chip = NULL; 642 sc->sc_dc.dc_readreg = dbcool_readreg; 643 sc->sc_dc.dc_writereg = dbcool_writereg; 644 (void)dbcool_chip_ident(&sc->sc_dc); 645 sc->sc_dev = self; 646 647 aprint_naive("\n"); 648 aprint_normal("\n"); 649 650 ver = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_REVISION_REG); 651 if (sc->sc_dc.dc_chip->flags & DBCFLAG_4BIT_VER) 652 aprint_normal_dev(self, "%s dBCool(tm) Controller " 653 "(rev 0x%02x, stepping 0x%02x)\n", sc->sc_dc.dc_chip->name, 654 ver >> 4, ver & 0x0f); 655 else 656 aprint_normal_dev(self, "%s dBCool(tm) Controller " 657 "(rev 0x%04x)\n", sc->sc_dc.dc_chip->name, ver); 658 659 dbcool_setup(self); 660 661 if (!pmf_device_register(self, dbcool_pmf_suspend, dbcool_pmf_resume)) 662 aprint_error_dev(self, "couldn't establish power handler\n"); 663 } 664 665 static int 666 dbcool_detach(device_t self, int flags) 667 { 668 struct dbcool_softc *sc = device_private(self); 669 670 sysmon_envsys_unregister(sc->sc_sme); 671 sc->sc_sme = NULL; 672 return 0; 673 } 674 675 /* On suspend, we save the state of the SHDN bit, then set it */ 676 bool dbcool_pmf_suspend(device_t dev, const pmf_qual_t *qual) 677 { 678 struct dbcool_softc *sc = device_private(dev); 679 uint8_t reg, bit, cfg; 680 681 if ((sc->sc_dc.dc_chip->flags && DBCFLAG_HAS_SHDN) == 0) 682 return true; 683 684 if (sc->sc_dc.dc_chip->flags && DBCFLAG_ADT7466) { 685 reg = DBCOOL_ADT7466_CONFIG2; 686 bit = DBCOOL_ADT7466_CFG2_SHDN; 687 } else { 688 reg = DBCOOL_CONFIG2_REG; 689 bit = DBCOOL_CFG2_SHDN; 690 } 691 cfg = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 692 sc->sc_suspend = cfg & bit; 693 cfg |= bit; 694 sc->sc_dc.dc_writereg(&sc->sc_dc, reg, cfg); 695 696 return true; 697 } 698 699 /* On resume, we restore the previous state of the SHDN bit */ 700 bool dbcool_pmf_resume(device_t dev, const pmf_qual_t *qual) 701 { 702 struct dbcool_softc *sc = device_private(dev); 703 uint8_t reg, bit, cfg; 704 705 if ((sc->sc_dc.dc_chip->flags && DBCFLAG_HAS_SHDN) == 0) 706 return true; 707 708 if (sc->sc_dc.dc_chip->flags && DBCFLAG_ADT7466) { 709 reg = DBCOOL_ADT7466_CONFIG2; 710 bit = DBCOOL_ADT7466_CFG2_SHDN; 711 } else { 712 reg = DBCOOL_CONFIG2_REG; 713 bit = DBCOOL_CFG2_SHDN; 714 } 715 cfg = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 716 cfg &= ~sc->sc_suspend; 717 sc->sc_dc.dc_writereg(&sc->sc_dc, reg, cfg); 718 719 return true; 720 721 } 722 723 uint8_t 724 dbcool_readreg(struct dbcool_chipset *dc, uint8_t reg) 725 { 726 uint8_t data = 0; 727 728 if (iic_acquire_bus(dc->dc_tag, 0) != 0) 729 return data; 730 731 if (dc->dc_chip == NULL || dc->dc_chip->flags & DBCFLAG_NO_READBYTE) { 732 /* ADM1027 doesn't support i2c read_byte protocol */ 733 if (iic_smbus_send_byte(dc->dc_tag, dc->dc_addr, reg, 0) != 0) 734 goto bad; 735 (void)iic_smbus_receive_byte(dc->dc_tag, dc->dc_addr, &data, 0); 736 } else 737 (void)iic_smbus_read_byte(dc->dc_tag, dc->dc_addr, reg, &data, 738 0); 739 740 bad: 741 iic_release_bus(dc->dc_tag, 0); 742 return data; 743 } 744 745 void 746 dbcool_writereg(struct dbcool_chipset *dc, uint8_t reg, uint8_t val) 747 { 748 if (iic_acquire_bus(dc->dc_tag, 0) != 0) 749 return; 750 751 (void)iic_smbus_write_byte(dc->dc_tag, dc->dc_addr, reg, val, 0); 752 753 iic_release_bus(dc->dc_tag, 0); 754 } 755 756 static bool 757 dbcool_islocked(struct dbcool_softc *sc) 758 { 759 uint8_t cfg_reg; 760 761 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 762 return 0; 763 764 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) 765 cfg_reg = DBCOOL_ADT7466_CONFIG1; 766 else 767 cfg_reg = DBCOOL_CONFIG1_REG; 768 769 if (sc->sc_dc.dc_readreg(&sc->sc_dc, cfg_reg) & DBCOOL_CFG1_LOCK) 770 return 1; 771 else 772 return 0; 773 } 774 775 static int 776 dbcool_read_temp(struct dbcool_softc *sc, uint8_t reg, bool extres) 777 { 778 uint8_t t1, t2, t3, val, ext = 0; 779 int temp; 780 781 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) { 782 /* 783 * ADT7466 temps are in strange location 784 */ 785 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADT7466_CONFIG1); 786 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 787 if (extres) 788 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, reg + 1); 789 } else if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) { 790 /* 791 * ADM1030 temps are in their own special place, too 792 */ 793 if (extres) { 794 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_TEMP_EXTRES); 795 if (reg == DBCOOL_ADM1030_L_TEMP) 796 ext >>= 6; 797 else 798 ext >>= 1; 799 ext &= 0x03; 800 } 801 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 802 } else if (extres) { 803 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES2_REG); 804 805 /* Read all msb regs to unlatch them */ 806 t1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_12VIN); 807 t1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_REMOTE1_TEMP); 808 t2 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_REMOTE2_TEMP); 809 t3 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_LOCAL_TEMP); 810 switch (reg) { 811 case DBCOOL_REMOTE1_TEMP: 812 val = t1; 813 ext >>= 2; 814 break; 815 case DBCOOL_LOCAL_TEMP: 816 val = t3; 817 ext >>= 4; 818 break; 819 case DBCOOL_REMOTE2_TEMP: 820 val = t2; 821 ext >>= 6; 822 break; 823 default: 824 val = 0; 825 break; 826 } 827 ext &= 0x03; 828 } 829 else 830 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 831 832 /* Check for invalid temp values */ 833 if ((sc->sc_temp_offset == 0 && val == 0x80) || 834 (sc->sc_temp_offset != 0 && val == 0)) 835 return 0; 836 837 /* If using offset mode, adjust, else treat as signed */ 838 if (sc->sc_temp_offset) { 839 temp = val; 840 temp -= sc->sc_temp_offset; 841 } else 842 temp = (int8_t)val; 843 844 /* Convert degC to uK and include extended precision bits */ 845 temp *= 1000000; 846 temp += 250000 * (int)ext; 847 temp += 273150000U; 848 849 return temp; 850 } 851 852 static int 853 dbcool_read_rpm(struct dbcool_softc *sc, uint8_t reg) 854 { 855 int rpm; 856 uint8_t rpm_lo, rpm_hi; 857 858 rpm_lo = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 859 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 860 rpm_hi = (rpm_lo == 0xff)?0xff:0x0; 861 else 862 rpm_hi = sc->sc_dc.dc_readreg(&sc->sc_dc, reg + 1); 863 864 rpm = (rpm_hi << 8) | rpm_lo; 865 if (rpm == 0xffff) 866 return 0; /* 0xffff indicates stalled/failed fan */ 867 868 return (sc->sc_dc.dc_chip->rpm_dividend / rpm); 869 } 870 871 /* Provide chip's supply voltage, in microvolts */ 872 static int 873 dbcool_supply_voltage(struct dbcool_softc *sc) 874 { 875 if (sc->sc_dc.dc_chip->flags & DBCFLAG_MULTI_VCC) { 876 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_CONFIG1_REG) & DBCOOL_CFG1_Vcc) 877 return 5002500; 878 else 879 return 3300000; 880 } else if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) { 881 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADT7466_CONFIG1) & 882 DBCOOL_ADT7466_CFG1_Vcc) 883 return 5000000; 884 else 885 return 3300000; 886 } else 887 return 3300000; 888 } 889 890 /* 891 * Nominal voltages are calculated in microvolts 892 */ 893 static int 894 dbcool_read_volt(struct dbcool_softc *sc, uint8_t reg, int nom_idx, bool extres) 895 { 896 uint8_t ext = 0, v1, v2, v3, v4, val; 897 int64_t ret; 898 int64_t nom; 899 900 nom = nominal_voltages[nom_idx]; 901 if (nom < 0) 902 nom = sc->sc_supply_voltage; 903 904 /* ADT7466 voltages are in strange locations with only 8-bits */ 905 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) 906 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 907 else 908 /* 909 * It's a "normal" dbCool chip - check for regs that 910 * share extended resolution bits since we have to 911 * read all the MSB registers to unlatch them. 912 */ 913 if (!extres) 914 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 915 else if (reg == DBCOOL_12VIN) { 916 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES2_REG) && 0x03; 917 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 918 (void)dbcool_read_temp(sc, DBCOOL_LOCAL_TEMP, true); 919 } else if (reg == DBCOOL_VTT || reg == DBCOOL_IMON) { 920 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES_VTT_IMON); 921 v1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_IMON); 922 v2 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VTT); 923 if (reg == DBCOOL_IMON) { 924 val = v1; 925 ext >>= 6; 926 } else 927 val = v2; 928 ext >>= 4; 929 ext &= 0x0f; 930 } else { 931 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES1_REG); 932 v1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_25VIN); 933 v2 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VCCP); 934 v3 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VCC); 935 v4 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_5VIN); 936 937 switch (reg) { 938 case DBCOOL_25VIN: 939 val = v1; 940 break; 941 case DBCOOL_VCCP: 942 val = v2; 943 ext >>= 2; 944 break; 945 case DBCOOL_VCC: 946 val = v3; 947 ext >>= 4; 948 break; 949 case DBCOOL_5VIN: 950 val = v4; 951 ext >>= 6; 952 break; 953 default: 954 val = nom = 0; 955 } 956 ext &= 0x03; 957 } 958 959 /* 960 * Scale the nominal value by the 10-bit fraction 961 * 962 * Returned value is in microvolts. 963 */ 964 ret = val; 965 ret <<= 2; 966 ret |= ext; 967 ret = (ret * nom) / 0x300; 968 969 return ret; 970 } 971 972 SYSCTL_SETUP(sysctl_dbcoolsetup, "sysctl dBCool subtree setup") 973 { 974 sysctl_createv(NULL, 0, NULL, NULL, 975 CTLFLAG_PERMANENT, 976 CTLTYPE_NODE, "hw", NULL, 977 NULL, 0, NULL, 0, 978 CTL_HW, CTL_EOL); 979 } 980 981 static int 982 sysctl_dbcool_temp(SYSCTLFN_ARGS) 983 { 984 struct sysctlnode node; 985 struct dbcool_softc *sc; 986 int reg, error; 987 uint8_t chipreg; 988 uint8_t newreg; 989 990 node = *rnode; 991 sc = (struct dbcool_softc *)node.sysctl_data; 992 chipreg = node.sysctl_num & 0xff; 993 994 if (sc->sc_temp_offset) { 995 reg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 996 reg -= sc->sc_temp_offset; 997 } else 998 reg = (int8_t)sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 999 1000 node.sysctl_data = ® 1001 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1002 1003 if (error || newp == NULL) 1004 return error; 1005 1006 /* We were asked to update the value - sanity check before writing */ 1007 if (*(int *)node.sysctl_data < -64 || 1008 *(int *)node.sysctl_data > 127 + sc->sc_temp_offset) 1009 return EINVAL; 1010 1011 newreg = *(int *)node.sysctl_data; 1012 newreg += sc->sc_temp_offset; 1013 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1014 return 0; 1015 } 1016 1017 static int 1018 sysctl_adm1030_temp(SYSCTLFN_ARGS) 1019 { 1020 struct sysctlnode node; 1021 struct dbcool_softc *sc; 1022 int reg, error; 1023 uint8_t chipreg, oldreg, newreg; 1024 1025 node = *rnode; 1026 sc = (struct dbcool_softc *)node.sysctl_data; 1027 chipreg = node.sysctl_num & 0xff; 1028 1029 oldreg = (int8_t)sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1030 reg = (oldreg >> 1) & ~0x03; 1031 1032 node.sysctl_data = ® 1033 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1034 1035 if (error || newp == NULL) 1036 return error; 1037 1038 /* We were asked to update the value - sanity check before writing */ 1039 if (*(int *)node.sysctl_data < 0 || *(int *)node.sysctl_data > 127) 1040 return EINVAL; 1041 1042 newreg = *(int *)node.sysctl_data; 1043 newreg &= ~0x03; 1044 newreg <<= 1; 1045 newreg |= (oldreg & 0x07); 1046 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1047 return 0; 1048 } 1049 1050 static int 1051 sysctl_adm1030_trange(SYSCTLFN_ARGS) 1052 { 1053 struct sysctlnode node; 1054 struct dbcool_softc *sc; 1055 int reg, error, newval; 1056 uint8_t chipreg, oldreg, newreg; 1057 1058 node = *rnode; 1059 sc = (struct dbcool_softc *)node.sysctl_data; 1060 chipreg = node.sysctl_num & 0xff; 1061 1062 oldreg = (int8_t)sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1063 reg = oldreg & 0x07; 1064 1065 node.sysctl_data = ® 1066 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1067 1068 if (error || newp == NULL) 1069 return error; 1070 1071 /* We were asked to update the value - sanity check before writing */ 1072 newval = *(int *)node.sysctl_data; 1073 1074 if (newval == 5) 1075 newreg = 0; 1076 else if (newval == 10) 1077 newreg = 1; 1078 else if (newval == 20) 1079 newreg = 2; 1080 else if (newval == 40) 1081 newreg = 3; 1082 else if (newval == 80) 1083 newreg = 4; 1084 else 1085 return EINVAL; 1086 1087 newreg |= (oldreg & ~0x07); 1088 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1089 return 0; 1090 } 1091 1092 static int 1093 sysctl_dbcool_duty(SYSCTLFN_ARGS) 1094 { 1095 struct sysctlnode node; 1096 struct dbcool_softc *sc; 1097 int reg, error; 1098 uint8_t chipreg, oldreg, newreg; 1099 1100 node = *rnode; 1101 sc = (struct dbcool_softc *)node.sysctl_data; 1102 chipreg = node.sysctl_num & 0xff; 1103 1104 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1105 reg = (uint32_t)oldreg; 1106 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 1107 reg = ((reg & 0x0f) * 100) / 15; 1108 else 1109 reg = (reg * 100) / 255; 1110 node.sysctl_data = ® 1111 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1112 1113 if (error || newp == NULL) 1114 return error; 1115 1116 /* We were asked to update the value - sanity check before writing */ 1117 if (*(int *)node.sysctl_data < 0 || *(int *)node.sysctl_data > 100) 1118 return EINVAL; 1119 1120 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) { 1121 newreg = *(uint8_t *)(node.sysctl_data) * 15 / 100; 1122 newreg |= oldreg & 0xf0; 1123 } else 1124 newreg = *(uint8_t *)(node.sysctl_data) * 255 / 100; 1125 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1126 return 0; 1127 } 1128 1129 static int 1130 sysctl_dbcool_behavior(SYSCTLFN_ARGS) 1131 { 1132 struct sysctlnode node; 1133 struct dbcool_softc *sc; 1134 int i, reg, error; 1135 uint8_t chipreg, oldreg, newreg; 1136 1137 node = *rnode; 1138 sc = (struct dbcool_softc *)node.sysctl_data; 1139 chipreg = node.sysctl_num & 0xff; 1140 1141 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1142 1143 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) { 1144 if ((sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_CFG2) & 1) == 0) 1145 reg = 4; 1146 else if ((oldreg & 0x80) == 0) 1147 reg = 7; 1148 else if ((oldreg & 0x60) == 0) 1149 reg = 4; 1150 else 1151 reg = 6; 1152 } else 1153 reg = (oldreg >> 5) & 0x07; 1154 1155 strlcpy(dbcool_cur_behav, behavior[reg], sizeof(dbcool_cur_behav)); 1156 node.sysctl_data = dbcool_cur_behav; 1157 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1158 1159 if (error || newp == NULL) 1160 return error; 1161 1162 /* We were asked to update the value - convert string to value */ 1163 newreg = __arraycount(behavior); 1164 for (i = 0; i < __arraycount(behavior); i++) 1165 if (strcmp(node.sysctl_data, behavior[i]) == 0) 1166 break; 1167 if (i >= __arraycount(behavior)) 1168 return EINVAL; 1169 1170 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) { 1171 /* 1172 * ADM1030 splits fan controller behavior across two 1173 * registers. We also do not support Auto-Filter mode 1174 * nor do we support Manual-RPM-feedback. 1175 */ 1176 if (newreg == 4) { 1177 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_CFG2); 1178 oldreg &= ~0x01; 1179 sc->sc_dc.dc_writereg(&sc->sc_dc, DBCOOL_ADM1030_CFG2, oldreg); 1180 } else { 1181 if (newreg == 0) 1182 newreg = 4; 1183 else if (newreg == 6) 1184 newreg = 7; 1185 else if (newreg == 7) 1186 newreg = 0; 1187 else 1188 return EINVAL; 1189 newreg <<= 5; 1190 newreg |= (oldreg & 0x1f); 1191 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1192 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_CFG2) | 1; 1193 sc->sc_dc.dc_writereg(&sc->sc_dc, DBCOOL_ADM1030_CFG2, oldreg); 1194 } 1195 } else { 1196 newreg = (sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg) & 0x1f) | (i << 5); 1197 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1198 } 1199 return 0; 1200 } 1201 1202 static int 1203 sysctl_dbcool_slope(SYSCTLFN_ARGS) 1204 { 1205 struct sysctlnode node; 1206 struct dbcool_softc *sc; 1207 int reg, error; 1208 uint8_t chipreg; 1209 uint8_t newreg; 1210 1211 node = *rnode; 1212 sc = (struct dbcool_softc *)node.sysctl_data; 1213 chipreg = node.sysctl_num & 0xff; 1214 1215 reg = (sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg) >> 4) & 0x0f; 1216 node.sysctl_data = ® 1217 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1218 1219 if (error || newp == NULL) 1220 return error; 1221 1222 /* We were asked to update the value - sanity check before writing */ 1223 if (*(int *)node.sysctl_data < 0 || *(int *)node.sysctl_data > 0x0f) 1224 return EINVAL; 1225 1226 newreg = (sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg) & 0x0f) | 1227 (*(int *)node.sysctl_data << 4); 1228 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1229 return 0; 1230 } 1231 1232 static int 1233 sysctl_dbcool_thyst(SYSCTLFN_ARGS) 1234 { 1235 struct sysctlnode node; 1236 struct dbcool_softc *sc; 1237 int reg, error; 1238 uint8_t chipreg; 1239 uint8_t newreg, newhyst; 1240 1241 node = *rnode; 1242 sc = (struct dbcool_softc *)node.sysctl_data; 1243 chipreg = node.sysctl_num & 0x7f; 1244 1245 /* retrieve 4-bit value */ 1246 newreg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1247 if ((node.sysctl_num & 0x80) == 0) 1248 reg = newreg >> 4; 1249 else 1250 reg = newreg; 1251 reg = reg & 0x0f; 1252 1253 node.sysctl_data = ® 1254 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1255 1256 if (error || newp == NULL) 1257 return error; 1258 1259 /* We were asked to update the value - sanity check before writing */ 1260 newhyst = *(int *)node.sysctl_data; 1261 if (newhyst > 0x0f) 1262 return EINVAL; 1263 1264 /* Insert new value into field and update register */ 1265 if ((node.sysctl_num & 0x80) == 0) { 1266 newreg &= 0x0f; 1267 newreg |= (newhyst << 4); 1268 } else { 1269 newreg &= 0xf0; 1270 newreg |= newhyst; 1271 } 1272 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1273 return 0; 1274 } 1275 1276 #ifdef DBCOOL_DEBUG 1277 1278 /* 1279 * These routines can be used for debugging. reg_select is used to 1280 * select any arbitrary register in the device. reg_access is used 1281 * to read (and optionally update) the selected register. 1282 * 1283 * No attempt is made to validate the data passed. If you use these 1284 * routines, you are assumed to know what you're doing! 1285 * 1286 * Caveat user 1287 */ 1288 static int 1289 sysctl_dbcool_reg_select(SYSCTLFN_ARGS) 1290 { 1291 struct sysctlnode node; 1292 struct dbcool_softc *sc; 1293 int reg, error; 1294 1295 node = *rnode; 1296 sc = (struct dbcool_softc *)node.sysctl_data; 1297 1298 reg = sc->sc_user_reg; 1299 node.sysctl_data = ® 1300 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1301 1302 if (error || newp == NULL) 1303 return error; 1304 1305 sc->sc_user_reg = *(int *)node.sysctl_data; 1306 return 0; 1307 } 1308 1309 static int 1310 sysctl_dbcool_reg_access(SYSCTLFN_ARGS) 1311 { 1312 struct sysctlnode node; 1313 struct dbcool_softc *sc; 1314 int reg, error; 1315 uint8_t chipreg; 1316 uint8_t newreg; 1317 1318 node = *rnode; 1319 sc = (struct dbcool_softc *)node.sysctl_data; 1320 chipreg = sc->sc_user_reg; 1321 1322 reg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1323 node.sysctl_data = ® 1324 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1325 1326 if (error || newp == NULL) 1327 return error; 1328 1329 newreg = *(int *)node.sysctl_data; 1330 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1331 return 0; 1332 } 1333 #endif /* DBCOOL_DEBUG */ 1334 1335 /* 1336 * Encode an index number and register number for use as a sysctl_num 1337 * so we can select the correct device register later. 1338 */ 1339 #define DBC_PWM_SYSCTL(seq, reg) ((seq << 8) | reg) 1340 1341 void 1342 dbcool_setup(device_t self) 1343 { 1344 struct dbcool_softc *sc = device_private(self); 1345 const struct sysctlnode *me = NULL; 1346 #ifdef DBCOOL_DEBUG 1347 struct sysctlnode *node = NULL; 1348 #endif 1349 uint8_t cfg_val, cfg_reg; 1350 int ret, error; 1351 1352 /* 1353 * Some chips are capable of reporting an extended temperature range 1354 * by default. On these models, config register 5 bit 0 can be set 1355 * to 1 for compatability with other chips that report 2s complement. 1356 */ 1357 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) { 1358 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADT7466_CONFIG1) & 0x80) 1359 sc->sc_temp_offset = 64; 1360 else 1361 sc->sc_temp_offset = 0; 1362 } else if (sc->sc_dc.dc_chip->flags & DBCFLAG_TEMPOFFSET) { 1363 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_CONFIG5_REG) & 1364 DBCOOL_CFG5_TWOSCOMP) 1365 sc->sc_temp_offset = 0; 1366 else 1367 sc->sc_temp_offset = 64; 1368 } else 1369 sc->sc_temp_offset = 0; 1370 1371 /* Determine Vcc for this chip */ 1372 sc->sc_supply_voltage = dbcool_supply_voltage(sc); 1373 1374 ret = sysctl_createv(NULL, 0, NULL, &me, 1375 CTLFLAG_READWRITE, 1376 CTLTYPE_NODE, device_xname(self), NULL, 1377 NULL, 0, NULL, 0, 1378 CTL_HW, CTL_CREATE, CTL_EOL); 1379 if (ret == 0) 1380 sc->sc_root_sysctl_num = me->sysctl_num; 1381 else 1382 sc->sc_root_sysctl_num = 0; 1383 1384 aprint_debug_dev(self, 1385 "Supply voltage %"PRId64".%06"PRId64"V, %s temp range\n", 1386 sc->sc_supply_voltage / 1000000, 1387 sc->sc_supply_voltage % 1000000, 1388 sc->sc_temp_offset ? "extended" : "normal"); 1389 1390 /* Create the sensors for this device */ 1391 sc->sc_sme = sysmon_envsys_create(); 1392 if (dbcool_setup_sensors(sc)) 1393 goto out; 1394 1395 if (sc->sc_root_sysctl_num != 0) { 1396 /* If supported, create sysctl tree for fan PWM controllers */ 1397 if (sc->sc_dc.dc_chip->power != NULL) 1398 dbcool_setup_controllers(sc); 1399 1400 #ifdef DBCOOL_DEBUG 1401 ret = sysctl_createv(NULL, 0, NULL, 1402 (const struct sysctlnode **)&node, 1403 CTLFLAG_READWRITE, CTLTYPE_INT, "reg_select", NULL, 1404 sysctl_dbcool_reg_select, 1405 0, sc, sizeof(int), 1406 CTL_HW, me->sysctl_num, CTL_CREATE, CTL_EOL); 1407 if (node != NULL) 1408 node->sysctl_data = sc; 1409 1410 ret = sysctl_createv(NULL, 0, NULL, 1411 (const struct sysctlnode **)&node, 1412 CTLFLAG_READWRITE, CTLTYPE_INT, "reg_access", NULL, 1413 sysctl_dbcool_reg_access, 1414 0, sc, sizeof(int), 1415 CTL_HW, me->sysctl_num, CTL_CREATE, CTL_EOL); 1416 if (node != NULL) 1417 node->sysctl_data = sc; 1418 #endif /* DBCOOL_DEBUG */ 1419 } 1420 1421 /* 1422 * Read and rewrite config register to activate device 1423 */ 1424 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 1425 cfg_reg = DBCOOL_ADM1030_CFG1; 1426 else if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) 1427 cfg_reg = DBCOOL_ADT7466_CONFIG1; 1428 else 1429 cfg_reg = DBCOOL_CONFIG1_REG; 1430 cfg_val = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_CONFIG1_REG); 1431 if ((cfg_val & DBCOOL_CFG1_START) == 0) { 1432 cfg_val |= DBCOOL_CFG1_START; 1433 sc->sc_dc.dc_writereg(&sc->sc_dc, cfg_reg, cfg_val); 1434 } 1435 if (dbcool_islocked(sc)) 1436 aprint_normal_dev(self, "configuration locked\n"); 1437 1438 sc->sc_sme->sme_name = device_xname(self); 1439 sc->sc_sme->sme_cookie = sc; 1440 sc->sc_sme->sme_refresh = dbcool_refresh; 1441 sc->sc_sme->sme_set_limits = dbcool_set_limits; 1442 sc->sc_sme->sme_get_limits = dbcool_get_limits; 1443 1444 if ((error = sysmon_envsys_register(sc->sc_sme)) != 0) { 1445 aprint_error_dev(self, 1446 "unable to register with sysmon (%d)\n", error); 1447 goto out; 1448 } 1449 1450 return; 1451 1452 out: 1453 sysmon_envsys_destroy(sc->sc_sme); 1454 } 1455 1456 static int 1457 dbcool_setup_sensors(struct dbcool_softc *sc) 1458 { 1459 int i; 1460 int error = 0; 1461 uint8_t vid_reg, vid_val; 1462 struct chip_id *chip = sc->sc_dc.dc_chip; 1463 1464 for (i=0; chip->table[i].type != DBC_EOF; i++) { 1465 if (i < DBCOOL_MAXSENSORS) 1466 sc->sc_sysctl_num[i] = -1; 1467 else if (chip->table[i].type != DBC_CTL) { 1468 aprint_normal_dev(sc->sc_dev, "chip table too big!\n"); 1469 break; 1470 } 1471 switch (chip->table[i].type) { 1472 case DBC_TEMP: 1473 sc->sc_sensor[i].units = ENVSYS_STEMP; 1474 sc->sc_sensor[i].flags |= ENVSYS_FMONLIMITS; 1475 error = dbcool_attach_sensor(sc, i); 1476 break; 1477 case DBC_VOLT: 1478 /* 1479 * If 12V-In pin has been reconfigured as 6th bit 1480 * of VID code, don't create a 12V-In sensor 1481 */ 1482 if ((chip->flags & DBCFLAG_HAS_VID_SEL) && 1483 (chip->table[i].reg.val_reg == DBCOOL_12VIN) && 1484 (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VID_REG) & 1485 0x80)) 1486 break; 1487 1488 sc->sc_sensor[i].units = ENVSYS_SVOLTS_DC; 1489 sc->sc_sensor[i].flags |= ENVSYS_FMONLIMITS; 1490 error = dbcool_attach_sensor(sc, i); 1491 break; 1492 case DBC_FAN: 1493 sc->sc_sensor[i].units = ENVSYS_SFANRPM; 1494 sc->sc_sensor[i].flags |= ENVSYS_FMONLIMITS; 1495 error = dbcool_attach_sensor(sc, i); 1496 break; 1497 case DBC_VID: 1498 sc->sc_sensor[i].units = ENVSYS_INTEGER; 1499 sc->sc_sensor[i].flags |= ENVSYS_FMONNOTSUPP; 1500 1501 /* retrieve 5- or 6-bit value */ 1502 vid_reg = chip->table[i].reg.val_reg; 1503 vid_val = sc->sc_dc.dc_readreg(&sc->sc_dc, vid_reg); 1504 if (chip->flags & DBCFLAG_HAS_VID_SEL) 1505 vid_val &= 0x3f; 1506 else 1507 vid_val &= 0x1f; 1508 sc->sc_sensor[i].value_cur = vid_val; 1509 1510 error = dbcool_attach_sensor(sc, i); 1511 break; 1512 case DBC_CTL: 1513 error = dbcool_attach_temp_control(sc, i, chip); 1514 if (error) { 1515 aprint_error_dev(sc->sc_dev, 1516 "attach index %d failed %d\n", 1517 i, error); 1518 error = 0; 1519 } 1520 break; 1521 default: 1522 aprint_error_dev(sc->sc_dev, 1523 "sensor_table index %d has bad type %d\n", 1524 i, chip->table[i].type); 1525 break; 1526 } 1527 if (error) 1528 break; 1529 } 1530 return error; 1531 } 1532 1533 static int 1534 dbcool_attach_sensor(struct dbcool_softc *sc, int idx) 1535 { 1536 int name_index; 1537 int error = 0; 1538 1539 name_index = sc->sc_dc.dc_chip->table[idx].name_index; 1540 strlcpy(sc->sc_sensor[idx].desc, dbc_sensor_names[name_index], 1541 sizeof(sc->sc_sensor[idx].desc)); 1542 sc->sc_regs[idx] = &sc->sc_dc.dc_chip->table[idx].reg; 1543 sc->sc_nom_volt[idx] = sc->sc_dc.dc_chip->table[idx].nom_volt_index; 1544 1545 error = sysmon_envsys_sensor_attach(sc->sc_sme, &sc->sc_sensor[idx]); 1546 return error; 1547 } 1548 1549 static int 1550 dbcool_attach_temp_control(struct dbcool_softc *sc, int idx, 1551 struct chip_id *chip) 1552 { 1553 const struct sysctlnode *me2 = NULL; 1554 struct sysctlnode *node = NULL; 1555 int j, ret, sysctl_index, rw_flag; 1556 uint8_t sysctl_reg; 1557 char name[SYSCTL_NAMELEN]; 1558 1559 /* Search for the corresponding temp sensor */ 1560 for (j = 0; j < idx; j++) { 1561 if (j >= DBCOOL_MAXSENSORS || chip->table[j].type != DBC_TEMP) 1562 continue; 1563 if (chip->table[j].name_index == chip->table[idx].name_index) 1564 break; 1565 } 1566 if (j >= idx) /* Temp sensor not found */ 1567 return ENOENT; 1568 1569 /* create sysctl node for the sensor if not one already there */ 1570 if (sc->sc_sysctl_num[j] == -1) { 1571 ret = sysctl_createv(NULL, 0, NULL, &me2, CTLFLAG_READWRITE, 1572 CTLTYPE_NODE, sc->sc_sensor[j].desc, NULL, 1573 NULL, 0, NULL, 0, 1574 CTL_HW, sc->sc_root_sysctl_num, CTL_CREATE, 1575 CTL_EOL); 1576 if (me2 != NULL) 1577 sc->sc_sysctl_num[j] = me2->sysctl_num; 1578 else 1579 return ret; 1580 } 1581 /* add sysctl leaf node for this control variable */ 1582 sysctl_index = chip->table[idx].sysctl_index; 1583 sysctl_reg = chip->table[idx].reg.val_reg; 1584 strlcpy(name, dbc_sysctl_table[sysctl_index].name, sizeof(name)); 1585 if (dbc_sysctl_table[sysctl_index].lockable && dbcool_islocked(sc)) 1586 rw_flag = CTLFLAG_READONLY | CTLFLAG_OWNDESC; 1587 else 1588 rw_flag = CTLFLAG_READWRITE | CTLFLAG_OWNDESC; 1589 ret = sysctl_createv(NULL, 0, NULL, 1590 (const struct sysctlnode **)&node, rw_flag, 1591 CTLTYPE_INT, name, 1592 dbc_sysctl_table[sysctl_index].desc, 1593 dbc_sysctl_table[sysctl_index].helper, 1594 0, sc, sizeof(int), 1595 CTL_HW, sc->sc_root_sysctl_num, 1596 sc->sc_sysctl_num[j], 1597 DBC_PWM_SYSCTL(idx, sysctl_reg), CTL_EOL); 1598 if (node != NULL) 1599 node->sysctl_data = sc; 1600 1601 return ret; 1602 } 1603 1604 static void 1605 dbcool_setup_controllers(struct dbcool_softc *sc) 1606 { 1607 int i, j, ret, rw_flag; 1608 uint8_t sysctl_reg; 1609 struct chip_id *chip = sc->sc_dc.dc_chip; 1610 const struct sysctlnode *me2 = NULL; 1611 struct sysctlnode *node = NULL; 1612 char name[SYSCTL_NAMELEN]; 1613 1614 for (i = 0; chip->power[i].desc != NULL; i++) { 1615 snprintf(name, sizeof(name), "fan_ctl_%d", i); 1616 ret = sysctl_createv(NULL, 0, NULL, &me2, 1617 CTLFLAG_READWRITE | CTLFLAG_OWNDESC, 1618 CTLTYPE_NODE, name, NULL, 1619 NULL, 0, NULL, 0, 1620 CTL_HW, sc->sc_root_sysctl_num, CTL_CREATE, CTL_EOL); 1621 1622 for (j = DBC_PWM_BEHAVIOR; j < DBC_PWM_LAST_PARAM; j++) { 1623 if (j == DBC_PWM_MAX_DUTY && 1624 (chip->flags & DBCFLAG_HAS_MAXDUTY) == 0) 1625 continue; 1626 sysctl_reg = chip->power[i].power_regs[j]; 1627 if (sysctl_reg == DBCOOL_NO_REG) 1628 continue; 1629 strlcpy(name, dbc_sysctl_table[j].name, sizeof(name)); 1630 if (dbc_sysctl_table[j].lockable && dbcool_islocked(sc)) 1631 rw_flag = CTLFLAG_READONLY | CTLFLAG_OWNDESC; 1632 else 1633 rw_flag = CTLFLAG_READWRITE | CTLFLAG_OWNDESC; 1634 ret = sysctl_createv(NULL, 0, NULL, 1635 (const struct sysctlnode **)&node, rw_flag, 1636 (j == DBC_PWM_BEHAVIOR)? 1637 CTLTYPE_STRING:CTLTYPE_INT, 1638 name, 1639 dbc_sysctl_table[j].desc, 1640 dbc_sysctl_table[j].helper, 1641 0, sc, 1642 ( j == DBC_PWM_BEHAVIOR)? 1643 sizeof(dbcool_cur_behav): sizeof(int), 1644 CTL_HW, sc->sc_root_sysctl_num, me2->sysctl_num, 1645 DBC_PWM_SYSCTL(j, sysctl_reg), CTL_EOL); 1646 if (node != NULL) 1647 node->sysctl_data = sc; 1648 } 1649 } 1650 } 1651 1652 static void 1653 dbcool_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 1654 { 1655 struct dbcool_softc *sc=sme->sme_cookie; 1656 int i, nom_volt_idx, cur; 1657 struct reg_list *reg; 1658 1659 i = edata->sensor; 1660 reg = sc->sc_regs[i]; 1661 1662 edata->state = ENVSYS_SVALID; 1663 switch (edata->units) 1664 { 1665 case ENVSYS_STEMP: 1666 cur = dbcool_read_temp(sc, reg->val_reg, true); 1667 break; 1668 case ENVSYS_SVOLTS_DC: 1669 nom_volt_idx = sc->sc_nom_volt[i]; 1670 cur = dbcool_read_volt(sc, reg->val_reg, nom_volt_idx, 1671 true); 1672 break; 1673 case ENVSYS_SFANRPM: 1674 cur = dbcool_read_rpm(sc, reg->val_reg); 1675 break; 1676 case ENVSYS_INTEGER: 1677 return; 1678 default: 1679 edata->state = ENVSYS_SINVALID; 1680 return; 1681 } 1682 1683 if (cur == 0 && (edata->units != ENVSYS_SFANRPM)) 1684 edata->state = ENVSYS_SINVALID; 1685 1686 /* 1687 * If fan is "stalled" but has no low limit, treat 1688 * it as though the fan is not installed. 1689 */ 1690 else if (edata->units == ENVSYS_SFANRPM && cur == 0 && 1691 !(edata->upropset & (PROP_CRITMIN | PROP_WARNMIN))) 1692 edata->state = ENVSYS_SINVALID; 1693 1694 edata->value_cur = cur; 1695 } 1696 1697 int 1698 dbcool_chip_ident(struct dbcool_chipset *dc) 1699 { 1700 /* verify this is a supported dbCool chip */ 1701 uint8_t c_id, d_id, r_id; 1702 int i; 1703 1704 c_id = dc->dc_readreg(dc, DBCOOL_COMPANYID_REG); 1705 d_id = dc->dc_readreg(dc, DBCOOL_DEVICEID_REG); 1706 r_id = dc->dc_readreg(dc, DBCOOL_REVISION_REG); 1707 1708 for (i = 0; chip_table[i].company != 0; i++) 1709 if ((c_id == chip_table[i].company) && 1710 (d_id == chip_table[i].device || 1711 chip_table[i].device == 0xff) && 1712 (r_id == chip_table[i].rev || 1713 chip_table[i].rev == 0xff)) { 1714 dc->dc_chip = &chip_table[i]; 1715 return i; 1716 } 1717 1718 aprint_verbose("dbcool_chip_ident: addr 0x%02x c_id 0x%02x d_id 0x%02x" 1719 " r_id 0x%02x: No match.\n", dc->dc_addr, c_id, d_id, 1720 r_id); 1721 1722 return -1; 1723 } 1724 1725 /* 1726 * Retrieve sensor limits from the chip registers 1727 */ 1728 static void 1729 dbcool_get_limits(struct sysmon_envsys *sme, envsys_data_t *edata, 1730 sysmon_envsys_lim_t *limits, uint32_t *props) 1731 { 1732 int index = edata->sensor; 1733 struct dbcool_softc *sc = sme->sme_cookie; 1734 1735 *props &= ~(PROP_CRITMIN | PROP_CRITMAX); 1736 switch (edata->units) { 1737 case ENVSYS_STEMP: 1738 dbcool_get_temp_limits(sc, index, limits, props); 1739 break; 1740 case ENVSYS_SVOLTS_DC: 1741 dbcool_get_volt_limits(sc, index, limits, props); 1742 break; 1743 case ENVSYS_SFANRPM: 1744 dbcool_get_fan_limits(sc, index, limits, props); 1745 1746 /* FALLTHROUGH */ 1747 default: 1748 break; 1749 } 1750 *props &= ~PROP_DRIVER_LIMITS; 1751 1752 /* If both limits provided, make sure they're sane */ 1753 if ((*props & PROP_CRITMIN) && 1754 (*props & PROP_CRITMAX) && 1755 (limits->sel_critmin >= limits->sel_critmax)) 1756 *props &= ~(PROP_CRITMIN | PROP_CRITMAX); 1757 } 1758 1759 static void 1760 dbcool_get_temp_limits(struct dbcool_softc *sc, int idx, 1761 sysmon_envsys_lim_t *lims, uint32_t *props) 1762 { 1763 struct reg_list *reg = sc->sc_regs[idx]; 1764 uint8_t lo_lim, hi_lim; 1765 1766 lo_lim = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->lo_lim_reg); 1767 hi_lim = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->hi_lim_reg); 1768 1769 if (sc->sc_temp_offset) { 1770 if (lo_lim > 0x01) { 1771 lims->sel_critmin = lo_lim - sc->sc_temp_offset; 1772 *props |= PROP_CRITMIN; 1773 } 1774 if (hi_lim != 0xff) { 1775 lims->sel_critmax = hi_lim - sc->sc_temp_offset; 1776 *props |= PROP_CRITMAX; 1777 } 1778 } else { 1779 if (lo_lim != 0x80 && lo_lim != 0x81) { 1780 lims->sel_critmin = (int8_t)lo_lim; 1781 *props |= PROP_CRITMIN; 1782 } 1783 1784 if (hi_lim != 0x7f) { 1785 lims->sel_critmax = (int8_t)hi_lim; 1786 *props |= PROP_CRITMAX; 1787 } 1788 } 1789 1790 /* Convert temp limits to microKelvin */ 1791 lims->sel_critmin *= 1000000; 1792 lims->sel_critmin += 273150000; 1793 lims->sel_critmax *= 1000000; 1794 lims->sel_critmax += 273150000; 1795 } 1796 1797 static void 1798 dbcool_get_volt_limits(struct dbcool_softc *sc, int idx, 1799 sysmon_envsys_lim_t *lims, uint32_t *props) 1800 { 1801 struct reg_list *reg = sc->sc_regs[idx]; 1802 int64_t limit; 1803 int nom; 1804 1805 nom = nominal_voltages[sc->sc_dc.dc_chip->table[idx].nom_volt_index]; 1806 if (nom < 0) 1807 nom = dbcool_supply_voltage(sc); 1808 nom *= 1000000; /* scale for microvolts */ 1809 1810 limit = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->lo_lim_reg); 1811 if (limit != 0x00 && limit != 0xff) { 1812 limit *= nom; 1813 limit /= 0xc0; 1814 lims->sel_critmin = limit; 1815 *props |= PROP_CRITMIN; 1816 } 1817 limit = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->hi_lim_reg); 1818 if (limit != 0x00 && limit != 0xff) { 1819 limit *= nom; 1820 limit /= 0xc0; 1821 lims->sel_critmax = limit; 1822 *props |= PROP_CRITMAX; 1823 } 1824 } 1825 1826 static void 1827 dbcool_get_fan_limits(struct dbcool_softc *sc, int idx, 1828 sysmon_envsys_lim_t *lims, uint32_t *props) 1829 { 1830 struct reg_list *reg = sc->sc_regs[idx]; 1831 int32_t limit; 1832 1833 limit = dbcool_read_rpm(sc, reg->lo_lim_reg); 1834 if (limit) { 1835 lims->sel_critmin = limit; 1836 *props |= PROP_CRITMIN; 1837 } 1838 } 1839 1840 /* 1841 * Update sensor limits in the chip registers 1842 */ 1843 static void 1844 dbcool_set_limits(struct sysmon_envsys *sme, envsys_data_t *edata, 1845 sysmon_envsys_lim_t *limits, uint32_t *props) 1846 { 1847 int index = edata->sensor; 1848 struct dbcool_softc *sc = sme->sme_cookie; 1849 1850 switch (edata->units) { 1851 case ENVSYS_STEMP: 1852 dbcool_set_temp_limits(sc, index, limits, props); 1853 break; 1854 case ENVSYS_SVOLTS_DC: 1855 dbcool_set_volt_limits(sc, index, limits, props); 1856 break; 1857 case ENVSYS_SFANRPM: 1858 dbcool_set_fan_limits(sc, index, limits, props); 1859 1860 /* FALLTHROUGH */ 1861 default: 1862 break; 1863 } 1864 *props &= ~PROP_DRIVER_LIMITS; 1865 } 1866 1867 static void 1868 dbcool_set_temp_limits(struct dbcool_softc *sc, int idx, 1869 sysmon_envsys_lim_t *lims, uint32_t *props) 1870 { 1871 struct reg_list *reg = sc->sc_regs[idx]; 1872 int32_t limit; 1873 1874 if (*props & PROP_CRITMIN) { 1875 limit = lims->sel_critmin - 273150000; 1876 limit /= 1000000; 1877 if (sc->sc_temp_offset) { 1878 limit += sc->sc_temp_offset; 1879 if (limit < 0) 1880 limit = 0; 1881 else if (limit > 255) 1882 limit = 255; 1883 } else { 1884 if (limit < -127) 1885 limit = -127; 1886 else if (limit > 127) 1887 limit = 127; 1888 } 1889 } else 1890 if (sc->sc_temp_offset) 1891 limit = 0x00; 1892 else 1893 limit = 0x80; 1894 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, (uint8_t)limit); 1895 1896 if (*props & PROP_CRITMAX) { 1897 limit = lims->sel_critmax - 273150000; 1898 limit /= 1000000; 1899 if (sc->sc_temp_offset) { 1900 limit += sc->sc_temp_offset; 1901 if (limit < 0) 1902 limit = 0; 1903 else if (limit > 255) 1904 limit = 255; 1905 } else { 1906 if (limit < -127) 1907 limit = -127; 1908 else if (limit > 127) 1909 limit = 127; 1910 } 1911 } else 1912 if (sc->sc_temp_offset) 1913 limit = 0xff; 1914 else 1915 limit = 0x7f; 1916 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg, (uint8_t)limit); 1917 } 1918 1919 static void 1920 dbcool_set_volt_limits(struct dbcool_softc *sc, int idx, 1921 sysmon_envsys_lim_t *lims, uint32_t *props) 1922 { 1923 struct reg_list *reg = sc->sc_regs[idx]; 1924 int64_t limit; 1925 int nom; 1926 1927 nom = nominal_voltages[sc->sc_dc.dc_chip->table[idx].nom_volt_index]; 1928 if (nom < 0) 1929 nom = dbcool_supply_voltage(sc); 1930 nom *= 1000000; /* scale for microvolts */ 1931 1932 if (*props & PROP_CRITMIN) { 1933 limit = lims->sel_critmin; 1934 limit *= 0xc0; 1935 limit /= nom; 1936 if (limit > 0xff) 1937 limit = 0xff; 1938 else if (limit < 0) 1939 limit = 0; 1940 } else 1941 limit = 0; 1942 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, limit); 1943 1944 if (*props & PROP_CRITMAX) { 1945 limit = lims->sel_critmax; 1946 limit *= 0xc0; 1947 limit /= nom; 1948 if (limit > 0xff) 1949 limit = 0xff; 1950 else if (limit < 0) 1951 limit = 0; 1952 } else 1953 limit = 0xff; 1954 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg, limit); 1955 } 1956 1957 static void 1958 dbcool_set_fan_limits(struct dbcool_softc *sc, int idx, 1959 sysmon_envsys_lim_t *lims, uint32_t *props) 1960 { 1961 struct reg_list *reg = sc->sc_regs[idx]; 1962 int32_t limit, dividend; 1963 1964 if (*props & PROP_CRITMIN) { 1965 limit = lims->sel_critmin; 1966 if (limit == 0) 1967 limit = 0xffff; 1968 else { 1969 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 1970 dividend = 11250 * 60; 1971 else 1972 dividend = 90000 * 60; 1973 limit = limit / dividend; 1974 if (limit > 0xffff) 1975 limit = 0xffff; 1976 } 1977 } else 1978 limit = 0xffff; 1979 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, limit & 0xff); 1980 limit >>= 8; 1981 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg + 1, limit & 0xff); 1982 } 1983
Indexes created Thu Sep 25 02:09:54 GMT 2025