dbcool.c revision 1.22
1 /* $NetBSD: dbcool.c,v 1.22 2010/04/01 04:29:35 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Goyette 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * a driver for the dbCool(tm) family of environmental controllers 34 * 35 * Data sheets for the various supported chips are available at 36 * 37 * http://www.onsemi.com/pub/Collateral/ADM1027-D.PDF 38 * http://www.onsemi.com/pub/Collateral/ADM1030-D.PDF 39 * http://www.onsemi.com/pub/Collateral/ADT7463-D.PDF 40 * http://www.onsemi.com/pub/Collateral/ADT7466.PDF 41 * http://www.onsemi.com/pub/Collateral/ADT7467-D.PDF 42 * http://www.onsemi.com/pub/Collateral/ADT7468-D.PDF 43 * http://www.onsemi.com/pub/Collateral/ADT7473-D.PDF 44 * http://www.onsemi.com/pub/Collateral/ADT7475-D.PDF 45 * http://www.onsemi.com/pub/Collateral/ADT7476-D.PDF 46 * http://www.onsemi.com/pub/Collateral/ADT7490-D.PDF 47 * 48 * (URLs are correct as of October 5, 2008) 49 */ 50 51 #include <sys/cdefs.h> 52 __KERNEL_RCSID(0, "$NetBSD: dbcool.c,v 1.22 2010/04/01 04:29:35 macallan Exp $"); 53 54 #include <sys/param.h> 55 #include <sys/systm.h> 56 #include <sys/kernel.h> 57 #include <sys/device.h> 58 #include <sys/malloc.h> 59 #include <sys/sysctl.h> 60 61 #include <uvm/uvm_extern.h> 62 63 #include <dev/i2c/dbcool_var.h> 64 #include <dev/i2c/dbcool_reg.h> 65 66 /* Config interface */ 67 static int dbcool_match(device_t, cfdata_t, void *); 68 static void dbcool_attach(device_t, device_t, void *); 69 static int dbcool_detach(device_t, int); 70 71 /* Device attributes */ 72 static int dbcool_supply_voltage(struct dbcool_softc *); 73 static bool dbcool_islocked(struct dbcool_softc *); 74 75 /* Sensor read functions */ 76 static void dbcool_refresh(struct sysmon_envsys *, envsys_data_t *); 77 static int dbcool_read_rpm(struct dbcool_softc *, uint8_t); 78 static int dbcool_read_temp(struct dbcool_softc *, uint8_t, bool); 79 static int dbcool_read_volt(struct dbcool_softc *, uint8_t, int, bool); 80 81 /* Sensor get/set limit functions */ 82 static void dbcool_get_limits(struct sysmon_envsys *, envsys_data_t *, 83 sysmon_envsys_lim_t *, uint32_t *); 84 static void dbcool_get_temp_limits(struct dbcool_softc *, int, 85 sysmon_envsys_lim_t *, uint32_t *); 86 static void dbcool_get_volt_limits(struct dbcool_softc *, int, 87 sysmon_envsys_lim_t *, uint32_t *); 88 static void dbcool_get_fan_limits(struct dbcool_softc *, int, 89 sysmon_envsys_lim_t *, uint32_t *); 90 91 static void dbcool_set_limits(struct sysmon_envsys *, envsys_data_t *, 92 sysmon_envsys_lim_t *, uint32_t *); 93 static void dbcool_set_temp_limits(struct dbcool_softc *, int, 94 sysmon_envsys_lim_t *, uint32_t *); 95 static void dbcool_set_volt_limits(struct dbcool_softc *, int, 96 sysmon_envsys_lim_t *, uint32_t *); 97 static void dbcool_set_fan_limits(struct dbcool_softc *, int, 98 sysmon_envsys_lim_t *, uint32_t *); 99 100 /* SYSCTL Helpers */ 101 static int sysctl_dbcool_temp(SYSCTLFN_PROTO); 102 static int sysctl_adm1030_temp(SYSCTLFN_PROTO); 103 static int sysctl_adm1030_trange(SYSCTLFN_PROTO); 104 static int sysctl_dbcool_duty(SYSCTLFN_PROTO); 105 static int sysctl_dbcool_behavior(SYSCTLFN_PROTO); 106 static int sysctl_dbcool_slope(SYSCTLFN_PROTO); 107 static int sysctl_dbcool_thyst(SYSCTLFN_PROTO); 108 109 /* Set-up subroutines */ 110 static void dbcool_setup_controllers(struct dbcool_softc *); 111 static int dbcool_setup_sensors(struct dbcool_softc *); 112 static int dbcool_attach_sensor(struct dbcool_softc *, int); 113 static int dbcool_attach_temp_control(struct dbcool_softc *, int, 114 struct chip_id *); 115 116 #ifdef DBCOOL_DEBUG 117 static int sysctl_dbcool_reg_select(SYSCTLFN_PROTO); 118 static int sysctl_dbcool_reg_access(SYSCTLFN_PROTO); 119 #endif /* DBCOOL_DEBUG */ 120 121 /* 122 * Descriptions for SYSCTL entries 123 */ 124 struct dbc_sysctl_info { 125 const char *name; 126 const char *desc; 127 bool lockable; 128 int (*helper)(SYSCTLFN_PROTO); 129 }; 130 131 static struct dbc_sysctl_info dbc_sysctl_table[] = { 132 /* 133 * The first several entries must remain in the same order as the 134 * corresponding entries in enum dbc_pwm_params 135 */ 136 { "behavior", "operating behavior and temp selector", 137 true, sysctl_dbcool_behavior }, 138 { "min_duty", "minimum fan controller PWM duty cycle", 139 true, sysctl_dbcool_duty }, 140 { "max_duty", "maximum fan controller PWM duty cycle", 141 true, sysctl_dbcool_duty }, 142 { "cur_duty", "current fan controller PWM duty cycle", 143 false, sysctl_dbcool_duty }, 144 145 /* 146 * The rest of these should be in the order in which they 147 * are to be stored in the sysctl tree; the table index is 148 * used as the high-order bits of the sysctl_num to maintain 149 * the sequence. 150 * 151 * If you rearrange the order of these items, be sure to 152 * update the sysctl_index in the XXX_sensor_table[] for 153 * the various chips! 154 */ 155 { "Trange", "temp slope/range to reach 100% duty cycle", 156 true, sysctl_dbcool_slope }, 157 { "Tmin", "temp at which to start fan controller", 158 true, sysctl_dbcool_temp }, 159 { "Ttherm", "temp at which THERM is asserted", 160 true, sysctl_dbcool_temp }, 161 { "Thyst", "temp hysteresis for stopping fan controller", 162 true, sysctl_dbcool_thyst }, 163 { "Tmin", "temp at which to start fan controller", 164 true, sysctl_adm1030_temp }, 165 { "Trange", "temp slope/range to reach 100% duty cycle", 166 true, sysctl_adm1030_trange }, 167 }; 168 169 static const char *dbc_sensor_names[] = { 170 "l_temp", "r1_temp", "r2_temp", "Vccp", "Vcc", "fan1", 171 "fan2", "fan3", "fan4", "AIN1", "AIN2", "V2dot5", 172 "V5", "V12", "Vtt", "Imon", "VID" 173 }; 174 175 /* 176 * Following table derived from product data-sheets 177 */ 178 static int64_t nominal_voltages[] = { 179 -1, /* Vcc can be either 3.3 or 5.0V 180 at 3/4 scale */ 181 2249939, /* Vccp 2.25V 3/4 scale */ 182 2497436, /* 2.5VIN 2.5V 3/4 scale */ 183 5002466, /* 5VIN 5V 3/4 scale */ 184 12000000, /* 12VIN 12V 3/4 scale */ 185 1690809, /* Vtt, Imon 2.25V full scale */ 186 1689600, /* AIN1, AIN2 2.25V full scale */ 187 0 188 }; 189 190 /* 191 * Sensor-type, { val-reg, hilim-reg, lolim-reg}, name-idx, sysctl-table-idx, 192 * nom-voltage-index 193 */ 194 struct dbcool_sensor ADT7490_sensor_table[] = { 195 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 196 DBCOOL_LOCAL_HIGHLIM, 197 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 198 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 199 DBCOOL_REMOTE1_HIGHLIM, 200 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 201 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 202 DBCOOL_REMOTE2_HIGHLIM, 203 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 204 { DBC_VOLT, { DBCOOL_VCCP, 205 DBCOOL_VCCP_HIGHLIM, 206 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 207 { DBC_VOLT, { DBCOOL_VCC, 208 DBCOOL_VCC_HIGHLIM, 209 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 210 { DBC_VOLT, { DBCOOL_25VIN, 211 DBCOOL_25VIN_HIGHLIM, 212 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 }, 213 { DBC_VOLT, { DBCOOL_5VIN, 214 DBCOOL_5VIN_HIGHLIM, 215 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 }, 216 { DBC_VOLT, { DBCOOL_12VIN, 217 DBCOOL_12VIN_HIGHLIM, 218 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 }, 219 { DBC_VOLT, { DBCOOL_VTT, 220 DBCOOL_VTT_HIGHLIM, 221 DBCOOL_VTT_LOWLIM }, 14, 0, 5 }, 222 { DBC_VOLT, { DBCOOL_IMON, 223 DBCOOL_IMON_HIGHLIM, 224 DBCOOL_IMON_LOWLIM }, 15, 0, 5 }, 225 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 226 DBCOOL_NO_REG, 227 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 228 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 229 DBCOOL_NO_REG, 230 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 231 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 232 DBCOOL_NO_REG, 233 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 234 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 235 DBCOOL_NO_REG, 236 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 237 { DBC_VID, { DBCOOL_VID_REG, 238 DBCOOL_NO_REG, 239 DBCOOL_NO_REG }, 16, 0, 0 }, 240 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 241 DBCOOL_NO_REG, 242 DBCOOL_NO_REG }, 0, 5, 0 }, 243 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 244 DBCOOL_NO_REG, 245 DBCOOL_NO_REG }, 0, 6, 0 }, 246 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 247 DBCOOL_NO_REG, 248 DBCOOL_NO_REG }, 0, 7, 0 }, 249 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 250 DBCOOL_NO_REG, 251 DBCOOL_NO_REG }, 1, 5, 0 }, 252 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 253 DBCOOL_NO_REG, 254 DBCOOL_NO_REG }, 1, 6, 0 }, 255 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 256 DBCOOL_NO_REG, 257 DBCOOL_NO_REG }, 1, 7, 0 }, 258 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 259 DBCOOL_NO_REG, 260 DBCOOL_NO_REG }, 2, 5, 0 }, 261 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 262 DBCOOL_NO_REG, 263 DBCOOL_NO_REG }, 2, 6, 0 }, 264 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 265 DBCOOL_NO_REG, 266 DBCOOL_NO_REG }, 2, 7, 0 }, 267 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 268 }; 269 270 struct dbcool_sensor ADT7476_sensor_table[] = { 271 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 272 DBCOOL_LOCAL_HIGHLIM, 273 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 274 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 275 DBCOOL_REMOTE1_HIGHLIM, 276 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 277 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 278 DBCOOL_REMOTE2_HIGHLIM, 279 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 280 { DBC_VOLT, { DBCOOL_VCCP, 281 DBCOOL_VCCP_HIGHLIM, 282 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 283 { DBC_VOLT, { DBCOOL_VCC, 284 DBCOOL_VCC_HIGHLIM, 285 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 286 { DBC_VOLT, { DBCOOL_25VIN, 287 DBCOOL_25VIN_HIGHLIM, 288 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 }, 289 { DBC_VOLT, { DBCOOL_5VIN, 290 DBCOOL_5VIN_HIGHLIM, 291 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 }, 292 { DBC_VOLT, { DBCOOL_12VIN, 293 DBCOOL_12VIN_HIGHLIM, 294 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 }, 295 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 296 DBCOOL_NO_REG, 297 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 298 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 299 DBCOOL_NO_REG, 300 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 301 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 302 DBCOOL_NO_REG, 303 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 304 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 305 DBCOOL_NO_REG, 306 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 307 { DBC_VID, { DBCOOL_VID_REG, 308 DBCOOL_NO_REG, 309 DBCOOL_NO_REG }, 16, 0, 0 }, 310 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 311 DBCOOL_NO_REG, 312 DBCOOL_NO_REG }, 0, 5, 0 }, 313 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 314 DBCOOL_NO_REG, 315 DBCOOL_NO_REG }, 0, 6, 0 }, 316 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 317 DBCOOL_NO_REG, 318 DBCOOL_NO_REG }, 0, 7, 0 }, 319 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 320 DBCOOL_NO_REG, 321 DBCOOL_NO_REG }, 1, 5, 0 }, 322 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 323 DBCOOL_NO_REG, 324 DBCOOL_NO_REG }, 1, 6, 0 }, 325 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 326 DBCOOL_NO_REG, 327 DBCOOL_NO_REG }, 1, 7, 0 }, 328 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 329 DBCOOL_NO_REG, 330 DBCOOL_NO_REG }, 2, 5, 0 }, 331 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 332 DBCOOL_NO_REG, 333 DBCOOL_NO_REG }, 2, 6, 0 }, 334 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 335 DBCOOL_NO_REG, 336 DBCOOL_NO_REG }, 2, 7, 0 }, 337 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 338 }; 339 340 struct dbcool_sensor ADT7475_sensor_table[] = { 341 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 342 DBCOOL_LOCAL_HIGHLIM, 343 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 344 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 345 DBCOOL_REMOTE1_HIGHLIM, 346 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 347 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 348 DBCOOL_REMOTE2_HIGHLIM, 349 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 350 { DBC_VOLT, { DBCOOL_VCCP, 351 DBCOOL_VCCP_HIGHLIM, 352 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 353 { DBC_VOLT, { DBCOOL_VCC, 354 DBCOOL_VCC_HIGHLIM, 355 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 356 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 357 DBCOOL_NO_REG, 358 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 359 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 360 DBCOOL_NO_REG, 361 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 362 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 363 DBCOOL_NO_REG, 364 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 365 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 366 DBCOOL_NO_REG, 367 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 368 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 369 DBCOOL_NO_REG, 370 DBCOOL_NO_REG }, 0, 5, 0 }, 371 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 372 DBCOOL_NO_REG, 373 DBCOOL_NO_REG }, 0, 6, 0 }, 374 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 375 DBCOOL_NO_REG, 376 DBCOOL_NO_REG }, 0, 7, 0 }, 377 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 378 DBCOOL_NO_REG, 379 DBCOOL_NO_REG }, 1, 5, 0 }, 380 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 381 DBCOOL_NO_REG, 382 DBCOOL_NO_REG }, 1, 6, 0 }, 383 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 384 DBCOOL_NO_REG, 385 DBCOOL_NO_REG }, 1, 7, 0 }, 386 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 387 DBCOOL_NO_REG, 388 DBCOOL_NO_REG }, 2, 5, 0 }, 389 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 390 DBCOOL_NO_REG, 391 DBCOOL_NO_REG }, 2, 6, 0 }, 392 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 393 DBCOOL_NO_REG, 394 DBCOOL_NO_REG }, 2, 7, 0 }, 395 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 396 }; 397 398 /* 399 * The registers of dbcool_power_control must be in the same order as 400 * in enum dbc_pwm_params 401 */ 402 struct dbcool_power_control ADT7475_power_table[] = { 403 { { DBCOOL_PWM1_CTL, DBCOOL_PWM1_MINDUTY, 404 DBCOOL_PWM1_MAXDUTY, DBCOOL_PWM1_CURDUTY }, 405 "fan_control_1" }, 406 { { DBCOOL_PWM2_CTL, DBCOOL_PWM2_MINDUTY, 407 DBCOOL_PWM2_MAXDUTY, DBCOOL_PWM2_CURDUTY }, 408 "fan_control_2" }, 409 { { DBCOOL_PWM3_CTL, DBCOOL_PWM3_MINDUTY, 410 DBCOOL_PWM3_MAXDUTY, DBCOOL_PWM3_CURDUTY }, 411 "fan_control_3" }, 412 { { 0, 0, 0, 0 }, NULL } 413 }; 414 415 struct dbcool_sensor ADT7466_sensor_table[] = { 416 { DBC_TEMP, { DBCOOL_ADT7466_LCL_TEMP_MSB, 417 DBCOOL_ADT7466_LCL_TEMP_HILIM, 418 DBCOOL_ADT7466_LCL_TEMP_LOLIM }, 0, 0, 0 }, 419 { DBC_TEMP, { DBCOOL_ADT7466_REM_TEMP_MSB, 420 DBCOOL_ADT7466_REM_TEMP_HILIM, 421 DBCOOL_ADT7466_REM_TEMP_LOLIM }, 1, 0, 0 }, 422 { DBC_VOLT, { DBCOOL_ADT7466_VCC, 423 DBCOOL_ADT7466_VCC_HILIM, 424 DBCOOL_ADT7466_VCC_LOLIM }, 4, 0, 0 }, 425 { DBC_VOLT, { DBCOOL_ADT7466_AIN1, 426 DBCOOL_ADT7466_AIN1_HILIM, 427 DBCOOL_ADT7466_AIN1_LOLIM }, 9, 0, 6 }, 428 { DBC_VOLT, { DBCOOL_ADT7466_AIN2, 429 DBCOOL_ADT7466_AIN2_HILIM, 430 DBCOOL_ADT7466_AIN2_LOLIM }, 10, 0, 6 }, 431 { DBC_FAN, { DBCOOL_ADT7466_FANA_LSB, 432 DBCOOL_NO_REG, 433 DBCOOL_ADT7466_FANA_LOLIM_LSB }, 5, 0, 0 }, 434 { DBC_FAN, { DBCOOL_ADT7466_FANB_LSB, 435 DBCOOL_NO_REG, 436 DBCOOL_ADT7466_FANB_LOLIM_LSB }, 6, 0, 0 }, 437 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 438 }; 439 440 struct dbcool_sensor ADM1027_sensor_table[] = { 441 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 442 DBCOOL_LOCAL_HIGHLIM, 443 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 444 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 445 DBCOOL_REMOTE1_HIGHLIM, 446 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 447 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 448 DBCOOL_REMOTE2_HIGHLIM, 449 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 450 { DBC_VOLT, { DBCOOL_VCCP, 451 DBCOOL_VCCP_HIGHLIM, 452 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 453 { DBC_VOLT, { DBCOOL_VCC, 454 DBCOOL_VCC_HIGHLIM, 455 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 456 { DBC_VOLT, { DBCOOL_25VIN, 457 DBCOOL_25VIN_HIGHLIM, 458 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 }, 459 { DBC_VOLT, { DBCOOL_5VIN, 460 DBCOOL_5VIN_HIGHLIM, 461 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 }, 462 { DBC_VOLT, { DBCOOL_12VIN, 463 DBCOOL_12VIN_HIGHLIM, 464 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 }, 465 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 466 DBCOOL_NO_REG, 467 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 468 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 469 DBCOOL_NO_REG, 470 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 471 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 472 DBCOOL_NO_REG, 473 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 474 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 475 DBCOOL_NO_REG, 476 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 477 { DBC_VID, { DBCOOL_VID_REG, 478 DBCOOL_NO_REG, 479 DBCOOL_NO_REG }, 16, 0, 0 }, 480 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 481 DBCOOL_NO_REG, 482 DBCOOL_NO_REG }, 0, 5, 0 }, 483 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 484 DBCOOL_NO_REG, 485 DBCOOL_NO_REG }, 0, 6, 0 }, 486 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 487 DBCOOL_NO_REG, 488 DBCOOL_NO_REG }, 0, 7, 0 }, 489 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 490 DBCOOL_NO_REG, 491 DBCOOL_NO_REG }, 1, 5, 0 }, 492 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 493 DBCOOL_NO_REG, 494 DBCOOL_NO_REG }, 1, 6, 0 }, 495 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 496 DBCOOL_NO_REG, 497 DBCOOL_NO_REG }, 1, 7, 0 }, 498 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 499 DBCOOL_NO_REG, 500 DBCOOL_NO_REG }, 2, 5, 0 }, 501 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 502 DBCOOL_NO_REG, 503 DBCOOL_NO_REG }, 2, 6, 0 }, 504 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 505 DBCOOL_NO_REG, 506 DBCOOL_NO_REG }, 2, 7, 0 }, 507 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 508 }; 509 510 struct dbcool_sensor ADM1030_sensor_table[] = { 511 { DBC_TEMP, { DBCOOL_ADM1030_L_TEMP, 512 DBCOOL_ADM1030_L_HI_LIM, 513 DBCOOL_ADM1030_L_LO_LIM }, 0, 0, 0 }, 514 { DBC_TEMP, { DBCOOL_ADM1030_R_TEMP, 515 DBCOOL_ADM1030_R_HI_LIM, 516 DBCOOL_ADM1030_R_LO_LIM }, 1, 0, 0 }, 517 { DBC_FAN, { DBCOOL_ADM1030_FAN_TACH, 518 DBCOOL_NO_REG, 519 DBCOOL_ADM1030_FAN_LO_LIM }, 5, 0, 0 }, 520 { DBC_CTL, { DBCOOL_ADM1030_L_TMIN, 521 DBCOOL_NO_REG, 522 DBCOOL_NO_REG }, 0, 8, 0 }, 523 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH, 524 DBCOOL_NO_REG, 525 DBCOOL_NO_REG }, 0, 9, 0 }, 526 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH, 527 DBCOOL_NO_REG, 528 DBCOOL_NO_REG }, 0, 6, 0 }, 529 { DBC_CTL, { DBCOOL_ADM1030_R_TMIN, 530 DBCOOL_NO_REG, 531 DBCOOL_NO_REG }, 1, 8, 0 }, 532 { DBC_CTL, { DBCOOL_ADM1030_R_TTHRESH, 533 DBCOOL_NO_REG, 534 DBCOOL_NO_REG }, 1, 9, 0 }, 535 { DBC_CTL, { DBCOOL_ADM1030_R_TTHRESH, 536 DBCOOL_NO_REG, 537 DBCOOL_NO_REG }, 1, 6, 0 }, 538 { DBC_EOF, {0, 0, 0 }, 0, 0, 0 } 539 }; 540 541 struct dbcool_power_control ADM1030_power_table[] = { 542 { { DBCOOL_ADM1030_CFG1, DBCOOL_NO_REG, DBCOOL_NO_REG, 543 DBCOOL_ADM1030_FAN_SPEED_CFG }, 544 "fan_control_1" }, 545 { { 0, 0, 0, 0 }, NULL } 546 }; 547 548 struct dbcool_sensor ADM1031_sensor_table[] = { 549 { DBC_TEMP, { DBCOOL_ADM1030_L_TEMP, 550 DBCOOL_ADM1030_L_HI_LIM, 551 DBCOOL_ADM1030_L_LO_LIM }, 0, 0, 0 }, 552 { DBC_TEMP, { DBCOOL_ADM1030_R_TEMP, 553 DBCOOL_ADM1030_R_HI_LIM, 554 DBCOOL_ADM1030_R_LO_LIM }, 1, 0, 0 }, 555 { DBC_TEMP, { DBCOOL_ADM1031_R2_TEMP, 556 DBCOOL_ADM1031_R2_HI_LIM, 557 DBCOOL_ADM1031_R2_LO_LIM }, 2, 0, 0 }, 558 { DBC_FAN, { DBCOOL_ADM1030_FAN_TACH, 559 DBCOOL_NO_REG, 560 DBCOOL_ADM1030_FAN_LO_LIM }, 5, 0, 0 }, 561 { DBC_FAN, { DBCOOL_ADM1031_FAN2_TACH, 562 DBCOOL_NO_REG, 563 DBCOOL_ADM1031_FAN2_LO_LIM }, 6, 0, 0 }, 564 { DBC_CTL, { DBCOOL_ADM1030_L_TMIN, 565 DBCOOL_NO_REG, 566 DBCOOL_NO_REG }, 0, 8, 0 }, 567 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH, 568 DBCOOL_NO_REG, 569 DBCOOL_NO_REG }, 0, 9, 0 }, 570 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH, 571 DBCOOL_NO_REG, 572 DBCOOL_NO_REG }, 0, 6, 0 }, 573 { DBC_CTL, { DBCOOL_ADM1030_R_TMIN, 574 DBCOOL_NO_REG, 575 DBCOOL_NO_REG }, 1, 8, 0 }, 576 { DBC_CTL, { DBCOOL_ADM1030_R_TTHRESH, 577 DBCOOL_NO_REG, 578 DBCOOL_NO_REG }, 1, 9, 0 }, 579 { DBC_CTL, { DBCOOL_ADM1030_R_TTHRESH, 580 DBCOOL_NO_REG, 581 DBCOOL_NO_REG }, 1, 6, 0 }, 582 { DBC_CTL, { DBCOOL_ADM1031_R2_TMIN, 583 DBCOOL_NO_REG, 584 DBCOOL_NO_REG }, 2, 8, 0 }, 585 { DBC_CTL, { DBCOOL_ADM1031_R2_TTHRESH, 586 DBCOOL_NO_REG, 587 DBCOOL_NO_REG }, 2, 9, 0 }, 588 { DBC_CTL, { DBCOOL_ADM1031_R2_TTHRESH, 589 DBCOOL_NO_REG, 590 DBCOOL_NO_REG }, 2, 6, 0 }, 591 { DBC_EOF, {0, 0, 0 }, 0, 0, 0 } 592 }; 593 594 struct dbcool_power_control ADM1031_power_table[] = { 595 { { DBCOOL_ADM1030_CFG1, DBCOOL_NO_REG, DBCOOL_NO_REG, 596 DBCOOL_ADM1030_FAN_SPEED_CFG }, 597 "fan_control_1" }, 598 { { DBCOOL_ADM1030_CFG1, DBCOOL_NO_REG, DBCOOL_NO_REG, 599 DBCOOL_ADM1030_FAN_SPEED_CFG }, 600 "fan_control_2" }, 601 { { 0, 0, 0, 0 }, NULL } 602 }; 603 struct chip_id chip_table[] = { 604 { DBCOOL_COMPANYID, ADT7490_DEVICEID, ADT7490_REV_ID, 605 ADT7490_sensor_table, ADT7475_power_table, 606 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_PECI, 607 90000 * 60, "ADT7490" }, 608 { DBCOOL_COMPANYID, ADT7476_DEVICEID, 0xff, 609 ADT7476_sensor_table, ADT7475_power_table, 610 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY, 611 90000 * 60, "ADT7476" }, 612 { DBCOOL_COMPANYID, ADT7475_DEVICEID, 0xff, 613 ADT7475_sensor_table, ADT7475_power_table, 614 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_SHDN, 615 90000 * 60, "ADT7475" }, 616 { DBCOOL_COMPANYID, ADT7473_DEVICEID, ADT7473_REV_ID1, 617 ADT7475_sensor_table, ADT7475_power_table, 618 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_SHDN, 619 90000 * 60, "ADT7460/ADT7463" }, 620 { DBCOOL_COMPANYID, ADT7473_DEVICEID, ADT7473_REV_ID2, 621 ADT7475_sensor_table, ADT7475_power_table, 622 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_SHDN, 623 90000 * 60, "ADT7463-1" }, 624 { DBCOOL_COMPANYID, ADT7468_DEVICEID, 0xff, 625 ADT7476_sensor_table, ADT7475_power_table, 626 DBCFLAG_TEMPOFFSET | DBCFLAG_MULTI_VCC | DBCFLAG_HAS_MAXDUTY | 627 DBCFLAG_4BIT_VER | DBCFLAG_HAS_SHDN, 628 90000 * 60, "ADT7467/ADT7468" }, 629 { DBCOOL_COMPANYID, ADT7466_DEVICEID, 0xff, 630 ADT7466_sensor_table, NULL, 631 DBCFLAG_ADT7466 | DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_SHDN, 632 82000 * 60, "ADT7466" }, 633 { DBCOOL_COMPANYID, ADT7463_DEVICEID, ADT7463_REV_ID1, 634 ADM1027_sensor_table, ADT7475_power_table, 635 DBCFLAG_MULTI_VCC | DBCFLAG_4BIT_VER | DBCFLAG_HAS_SHDN, 636 90000 * 60, "ADT7463" }, 637 { DBCOOL_COMPANYID, ADT7463_DEVICEID, ADT7463_REV_ID2, 638 ADM1027_sensor_table, ADT7475_power_table, 639 DBCFLAG_MULTI_VCC | DBCFLAG_4BIT_VER | DBCFLAG_HAS_SHDN | 640 DBCFLAG_HAS_VID_SEL, 641 90000 * 60, "ADT7463" }, 642 { DBCOOL_COMPANYID, ADM1027_DEVICEID, ADM1027_REV_ID, 643 ADM1027_sensor_table, ADT7475_power_table, 644 DBCFLAG_MULTI_VCC | DBCFLAG_4BIT_VER, 645 90000 * 60, "ADM1027" }, 646 { DBCOOL_COMPANYID, ADM1030_DEVICEID, 0xff, 647 ADM1030_sensor_table, ADM1030_power_table, 648 DBCFLAG_ADM1030 | DBCFLAG_NO_READBYTE, 649 11250 * 60, "ADM1030" }, 650 { DBCOOL_COMPANYID, ADM1031_DEVICEID, 0xff, 651 ADM1031_sensor_table, ADM1030_power_table, 652 DBCFLAG_ADM1030 | DBCFLAG_NO_READBYTE, 653 11250 * 60, "ADM1031" }, 654 { 0, 0, 0, NULL, NULL, 0, 0, NULL } 655 }; 656 657 static const char *behavior[] = { 658 "remote1", "local", "remote2", "full-speed", 659 "disabled", "local+remote2","all-temps", "manual" 660 }; 661 662 static char dbcool_cur_behav[16]; 663 664 CFATTACH_DECL_NEW(dbcool, sizeof(struct dbcool_softc), 665 dbcool_match, dbcool_attach, dbcool_detach, NULL); 666 667 int 668 dbcool_match(device_t parent, cfdata_t cf, void *aux) 669 { 670 struct i2c_attach_args *ia = aux; 671 struct dbcool_chipset dc; 672 dc.dc_tag = ia->ia_tag; 673 dc.dc_addr = ia->ia_addr; 674 dc.dc_chip = NULL; 675 dc.dc_readreg = dbcool_readreg; 676 dc.dc_writereg = dbcool_writereg; 677 678 /* no probing if we attach to iic, but verify chip id and address */ 679 if ((ia->ia_addr & DBCOOL_ADDRMASK) != DBCOOL_ADDR) 680 return 0; 681 if (dbcool_chip_ident(&dc) >= 0) 682 return 1; 683 684 return 0; 685 } 686 687 void 688 dbcool_attach(device_t parent, device_t self, void *aux) 689 { 690 struct dbcool_softc *sc = device_private(self); 691 struct i2c_attach_args *args = aux; 692 uint8_t ver; 693 694 sc->sc_dc.dc_addr = args->ia_addr; 695 sc->sc_dc.dc_tag = args->ia_tag; 696 sc->sc_dc.dc_chip = NULL; 697 sc->sc_dc.dc_readreg = dbcool_readreg; 698 sc->sc_dc.dc_writereg = dbcool_writereg; 699 (void)dbcool_chip_ident(&sc->sc_dc); 700 sc->sc_dev = self; 701 702 aprint_naive("\n"); 703 aprint_normal("\n"); 704 705 ver = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_REVISION_REG); 706 if (sc->sc_dc.dc_chip->flags & DBCFLAG_4BIT_VER) 707 aprint_normal_dev(self, "%s dBCool(tm) Controller " 708 "(rev 0x%02x, stepping 0x%02x)\n", sc->sc_dc.dc_chip->name, 709 ver >> 4, ver & 0x0f); 710 else 711 aprint_normal_dev(self, "%s dBCool(tm) Controller " 712 "(rev 0x%04x)\n", sc->sc_dc.dc_chip->name, ver); 713 714 dbcool_setup(self); 715 716 if (!pmf_device_register(self, dbcool_pmf_suspend, dbcool_pmf_resume)) 717 aprint_error_dev(self, "couldn't establish power handler\n"); 718 } 719 720 static int 721 dbcool_detach(device_t self, int flags) 722 { 723 struct dbcool_softc *sc = device_private(self); 724 725 sysmon_envsys_unregister(sc->sc_sme); 726 sc->sc_sme = NULL; 727 return 0; 728 } 729 730 /* On suspend, we save the state of the SHDN bit, then set it */ 731 bool dbcool_pmf_suspend(device_t dev, const pmf_qual_t *qual) 732 { 733 struct dbcool_softc *sc = device_private(dev); 734 uint8_t reg, bit, cfg; 735 736 if ((sc->sc_dc.dc_chip->flags && DBCFLAG_HAS_SHDN) == 0) 737 return true; 738 739 if (sc->sc_dc.dc_chip->flags && DBCFLAG_ADT7466) { 740 reg = DBCOOL_ADT7466_CONFIG2; 741 bit = DBCOOL_ADT7466_CFG2_SHDN; 742 } else { 743 reg = DBCOOL_CONFIG2_REG; 744 bit = DBCOOL_CFG2_SHDN; 745 } 746 cfg = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 747 sc->sc_suspend = cfg & bit; 748 cfg |= bit; 749 sc->sc_dc.dc_writereg(&sc->sc_dc, reg, cfg); 750 751 return true; 752 } 753 754 /* On resume, we restore the previous state of the SHDN bit */ 755 bool dbcool_pmf_resume(device_t dev, const pmf_qual_t *qual) 756 { 757 struct dbcool_softc *sc = device_private(dev); 758 uint8_t reg, bit, cfg; 759 760 if ((sc->sc_dc.dc_chip->flags && DBCFLAG_HAS_SHDN) == 0) 761 return true; 762 763 if (sc->sc_dc.dc_chip->flags && DBCFLAG_ADT7466) { 764 reg = DBCOOL_ADT7466_CONFIG2; 765 bit = DBCOOL_ADT7466_CFG2_SHDN; 766 } else { 767 reg = DBCOOL_CONFIG2_REG; 768 bit = DBCOOL_CFG2_SHDN; 769 } 770 cfg = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 771 cfg &= ~sc->sc_suspend; 772 sc->sc_dc.dc_writereg(&sc->sc_dc, reg, cfg); 773 774 return true; 775 776 } 777 778 uint8_t 779 dbcool_readreg(struct dbcool_chipset *dc, uint8_t reg) 780 { 781 uint8_t data = 0; 782 783 if (iic_acquire_bus(dc->dc_tag, 0) != 0) 784 return data; 785 786 if (dc->dc_chip == NULL || dc->dc_chip->flags & DBCFLAG_NO_READBYTE) { 787 /* ADM1027 doesn't support i2c read_byte protocol */ 788 if (iic_smbus_send_byte(dc->dc_tag, dc->dc_addr, reg, 0) != 0) 789 goto bad; 790 (void)iic_smbus_receive_byte(dc->dc_tag, dc->dc_addr, &data, 0); 791 } else 792 (void)iic_smbus_read_byte(dc->dc_tag, dc->dc_addr, reg, &data, 793 0); 794 795 bad: 796 iic_release_bus(dc->dc_tag, 0); 797 return data; 798 } 799 800 void 801 dbcool_writereg(struct dbcool_chipset *dc, uint8_t reg, uint8_t val) 802 { 803 if (iic_acquire_bus(dc->dc_tag, 0) != 0) 804 return; 805 806 (void)iic_smbus_write_byte(dc->dc_tag, dc->dc_addr, reg, val, 0); 807 808 iic_release_bus(dc->dc_tag, 0); 809 } 810 811 static bool 812 dbcool_islocked(struct dbcool_softc *sc) 813 { 814 uint8_t cfg_reg; 815 816 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 817 return 0; 818 819 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) 820 cfg_reg = DBCOOL_ADT7466_CONFIG1; 821 else 822 cfg_reg = DBCOOL_CONFIG1_REG; 823 824 if (sc->sc_dc.dc_readreg(&sc->sc_dc, cfg_reg) & DBCOOL_CFG1_LOCK) 825 return 1; 826 else 827 return 0; 828 } 829 830 static int 831 dbcool_read_temp(struct dbcool_softc *sc, uint8_t reg, bool extres) 832 { 833 uint8_t t1, t2, t3, val, ext = 0; 834 int temp; 835 836 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) { 837 /* 838 * ADT7466 temps are in strange location 839 */ 840 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADT7466_CONFIG1); 841 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 842 if (extres) 843 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, reg + 1); 844 } else if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) { 845 /* 846 * ADM1030 temps are in their own special place, too 847 */ 848 if (extres) { 849 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_TEMP_EXTRES); 850 if (reg == DBCOOL_ADM1030_L_TEMP) 851 ext >>= 6; 852 else if (reg == DBCOOL_ADM1031_R2_TEMP) 853 ext >>= 4; 854 else 855 ext >>= 1; 856 ext &= 0x03; 857 } 858 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 859 } else if (extres) { 860 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES2_REG); 861 862 /* Read all msb regs to unlatch them */ 863 t1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_12VIN); 864 t1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_REMOTE1_TEMP); 865 t2 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_REMOTE2_TEMP); 866 t3 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_LOCAL_TEMP); 867 switch (reg) { 868 case DBCOOL_REMOTE1_TEMP: 869 val = t1; 870 ext >>= 2; 871 break; 872 case DBCOOL_LOCAL_TEMP: 873 val = t3; 874 ext >>= 4; 875 break; 876 case DBCOOL_REMOTE2_TEMP: 877 val = t2; 878 ext >>= 6; 879 break; 880 default: 881 val = 0; 882 break; 883 } 884 ext &= 0x03; 885 } 886 else 887 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 888 889 /* Check for invalid temp values */ 890 if ((sc->sc_temp_offset == 0 && val == 0x80) || 891 (sc->sc_temp_offset != 0 && val == 0)) 892 return 0; 893 894 /* If using offset mode, adjust, else treat as signed */ 895 if (sc->sc_temp_offset) { 896 temp = val; 897 temp -= sc->sc_temp_offset; 898 } else 899 temp = (int8_t)val; 900 901 /* Convert degC to uK and include extended precision bits */ 902 temp *= 1000000; 903 temp += 250000 * (int)ext; 904 temp += 273150000U; 905 906 return temp; 907 } 908 909 static int 910 dbcool_read_rpm(struct dbcool_softc *sc, uint8_t reg) 911 { 912 int rpm; 913 uint8_t rpm_lo, rpm_hi; 914 915 rpm_lo = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 916 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 917 rpm_hi = (rpm_lo == 0xff)?0xff:0x0; 918 else 919 rpm_hi = sc->sc_dc.dc_readreg(&sc->sc_dc, reg + 1); 920 921 rpm = (rpm_hi << 8) | rpm_lo; 922 if (rpm == 0xffff) 923 return 0; /* 0xffff indicates stalled/failed fan */ 924 925 return (sc->sc_dc.dc_chip->rpm_dividend / rpm); 926 } 927 928 /* Provide chip's supply voltage, in microvolts */ 929 static int 930 dbcool_supply_voltage(struct dbcool_softc *sc) 931 { 932 if (sc->sc_dc.dc_chip->flags & DBCFLAG_MULTI_VCC) { 933 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_CONFIG1_REG) & DBCOOL_CFG1_Vcc) 934 return 5002500; 935 else 936 return 3300000; 937 } else if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) { 938 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADT7466_CONFIG1) & 939 DBCOOL_ADT7466_CFG1_Vcc) 940 return 5000000; 941 else 942 return 3300000; 943 } else 944 return 3300000; 945 } 946 947 /* 948 * Nominal voltages are calculated in microvolts 949 */ 950 static int 951 dbcool_read_volt(struct dbcool_softc *sc, uint8_t reg, int nom_idx, bool extres) 952 { 953 uint8_t ext = 0, v1, v2, v3, v4, val; 954 int64_t ret; 955 int64_t nom; 956 957 nom = nominal_voltages[nom_idx]; 958 if (nom < 0) 959 nom = sc->sc_supply_voltage; 960 961 /* ADT7466 voltages are in strange locations with only 8-bits */ 962 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) 963 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 964 else 965 /* 966 * It's a "normal" dbCool chip - check for regs that 967 * share extended resolution bits since we have to 968 * read all the MSB registers to unlatch them. 969 */ 970 if (!extres) 971 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 972 else if (reg == DBCOOL_12VIN) { 973 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES2_REG) && 0x03; 974 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 975 (void)dbcool_read_temp(sc, DBCOOL_LOCAL_TEMP, true); 976 } else if (reg == DBCOOL_VTT || reg == DBCOOL_IMON) { 977 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES_VTT_IMON); 978 v1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_IMON); 979 v2 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VTT); 980 if (reg == DBCOOL_IMON) { 981 val = v1; 982 ext >>= 6; 983 } else 984 val = v2; 985 ext >>= 4; 986 ext &= 0x0f; 987 } else { 988 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES1_REG); 989 v1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_25VIN); 990 v2 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VCCP); 991 v3 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VCC); 992 v4 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_5VIN); 993 994 switch (reg) { 995 case DBCOOL_25VIN: 996 val = v1; 997 break; 998 case DBCOOL_VCCP: 999 val = v2; 1000 ext >>= 2; 1001 break; 1002 case DBCOOL_VCC: 1003 val = v3; 1004 ext >>= 4; 1005 break; 1006 case DBCOOL_5VIN: 1007 val = v4; 1008 ext >>= 6; 1009 break; 1010 default: 1011 val = nom = 0; 1012 } 1013 ext &= 0x03; 1014 } 1015 1016 /* 1017 * Scale the nominal value by the 10-bit fraction 1018 * 1019 * Returned value is in microvolts. 1020 */ 1021 ret = val; 1022 ret <<= 2; 1023 ret |= ext; 1024 ret = (ret * nom) / 0x300; 1025 1026 return ret; 1027 } 1028 1029 SYSCTL_SETUP(sysctl_dbcoolsetup, "sysctl dBCool subtree setup") 1030 { 1031 sysctl_createv(NULL, 0, NULL, NULL, 1032 CTLFLAG_PERMANENT, 1033 CTLTYPE_NODE, "hw", NULL, 1034 NULL, 0, NULL, 0, 1035 CTL_HW, CTL_EOL); 1036 } 1037 1038 static int 1039 sysctl_dbcool_temp(SYSCTLFN_ARGS) 1040 { 1041 struct sysctlnode node; 1042 struct dbcool_softc *sc; 1043 int reg, error; 1044 uint8_t chipreg; 1045 uint8_t newreg; 1046 1047 node = *rnode; 1048 sc = (struct dbcool_softc *)node.sysctl_data; 1049 chipreg = node.sysctl_num & 0xff; 1050 1051 if (sc->sc_temp_offset) { 1052 reg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1053 reg -= sc->sc_temp_offset; 1054 } else 1055 reg = (int8_t)sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1056 1057 node.sysctl_data = ® 1058 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1059 1060 if (error || newp == NULL) 1061 return error; 1062 1063 /* We were asked to update the value - sanity check before writing */ 1064 if (*(int *)node.sysctl_data < -64 || 1065 *(int *)node.sysctl_data > 127 + sc->sc_temp_offset) 1066 return EINVAL; 1067 1068 newreg = *(int *)node.sysctl_data; 1069 newreg += sc->sc_temp_offset; 1070 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1071 return 0; 1072 } 1073 1074 static int 1075 sysctl_adm1030_temp(SYSCTLFN_ARGS) 1076 { 1077 struct sysctlnode node; 1078 struct dbcool_softc *sc; 1079 int reg, error; 1080 uint8_t chipreg, oldreg, newreg; 1081 1082 node = *rnode; 1083 sc = (struct dbcool_softc *)node.sysctl_data; 1084 chipreg = node.sysctl_num & 0xff; 1085 1086 oldreg = (int8_t)sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1087 reg = (oldreg >> 1) & ~0x03; 1088 1089 node.sysctl_data = ® 1090 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1091 1092 if (error || newp == NULL) 1093 return error; 1094 1095 /* We were asked to update the value - sanity check before writing */ 1096 if (*(int *)node.sysctl_data < 0 || *(int *)node.sysctl_data > 127) 1097 return EINVAL; 1098 1099 newreg = *(int *)node.sysctl_data; 1100 newreg &= ~0x03; 1101 newreg <<= 1; 1102 newreg |= (oldreg & 0x07); 1103 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1104 return 0; 1105 } 1106 1107 static int 1108 sysctl_adm1030_trange(SYSCTLFN_ARGS) 1109 { 1110 struct sysctlnode node; 1111 struct dbcool_softc *sc; 1112 int reg, error, newval; 1113 uint8_t chipreg, oldreg, newreg; 1114 1115 node = *rnode; 1116 sc = (struct dbcool_softc *)node.sysctl_data; 1117 chipreg = node.sysctl_num & 0xff; 1118 1119 oldreg = (int8_t)sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1120 reg = oldreg & 0x07; 1121 1122 node.sysctl_data = ® 1123 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1124 1125 if (error || newp == NULL) 1126 return error; 1127 1128 /* We were asked to update the value - sanity check before writing */ 1129 newval = *(int *)node.sysctl_data; 1130 1131 if (newval == 5) 1132 newreg = 0; 1133 else if (newval == 10) 1134 newreg = 1; 1135 else if (newval == 20) 1136 newreg = 2; 1137 else if (newval == 40) 1138 newreg = 3; 1139 else if (newval == 80) 1140 newreg = 4; 1141 else 1142 return EINVAL; 1143 1144 newreg |= (oldreg & ~0x07); 1145 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1146 return 0; 1147 } 1148 1149 static int 1150 sysctl_dbcool_duty(SYSCTLFN_ARGS) 1151 { 1152 struct sysctlnode node; 1153 struct dbcool_softc *sc; 1154 int reg, error; 1155 uint8_t chipreg, oldreg, newreg; 1156 1157 node = *rnode; 1158 sc = (struct dbcool_softc *)node.sysctl_data; 1159 chipreg = node.sysctl_num & 0xff; 1160 1161 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1162 reg = (uint32_t)oldreg; 1163 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 1164 reg = ((reg & 0x0f) * 100) / 15; 1165 else 1166 reg = (reg * 100) / 255; 1167 node.sysctl_data = ® 1168 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1169 1170 if (error || newp == NULL) 1171 return error; 1172 1173 /* We were asked to update the value - sanity check before writing */ 1174 if (*(int *)node.sysctl_data < 0 || *(int *)node.sysctl_data > 100) 1175 return EINVAL; 1176 1177 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) { 1178 newreg = *(uint8_t *)(node.sysctl_data) * 15 / 100; 1179 newreg |= oldreg & 0xf0; 1180 } else 1181 newreg = *(uint8_t *)(node.sysctl_data) * 255 / 100; 1182 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1183 return 0; 1184 } 1185 1186 static int 1187 sysctl_dbcool_behavior(SYSCTLFN_ARGS) 1188 { 1189 struct sysctlnode node; 1190 struct dbcool_softc *sc; 1191 int i, reg, error; 1192 uint8_t chipreg, oldreg, newreg; 1193 1194 node = *rnode; 1195 sc = (struct dbcool_softc *)node.sysctl_data; 1196 chipreg = node.sysctl_num & 0xff; 1197 1198 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1199 1200 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) { 1201 if ((sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_CFG2) & 1) == 0) 1202 reg = 4; 1203 else if ((oldreg & 0x80) == 0) 1204 reg = 7; 1205 else if ((oldreg & 0x60) == 0) 1206 reg = 4; 1207 else 1208 reg = 6; 1209 } else 1210 reg = (oldreg >> 5) & 0x07; 1211 1212 strlcpy(dbcool_cur_behav, behavior[reg], sizeof(dbcool_cur_behav)); 1213 node.sysctl_data = dbcool_cur_behav; 1214 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1215 1216 if (error || newp == NULL) 1217 return error; 1218 1219 /* We were asked to update the value - convert string to value */ 1220 newreg = __arraycount(behavior); 1221 for (i = 0; i < __arraycount(behavior); i++) 1222 if (strcmp(node.sysctl_data, behavior[i]) == 0) 1223 break; 1224 if (i >= __arraycount(behavior)) 1225 return EINVAL; 1226 1227 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) { 1228 /* 1229 * ADM1030 splits fan controller behavior across two 1230 * registers. We also do not support Auto-Filter mode 1231 * nor do we support Manual-RPM-feedback. 1232 */ 1233 if (newreg == 4) { 1234 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_CFG2); 1235 oldreg &= ~0x01; 1236 sc->sc_dc.dc_writereg(&sc->sc_dc, DBCOOL_ADM1030_CFG2, oldreg); 1237 } else { 1238 if (newreg == 0) 1239 newreg = 4; 1240 else if (newreg == 6) 1241 newreg = 7; 1242 else if (newreg == 7) 1243 newreg = 0; 1244 else 1245 return EINVAL; 1246 newreg <<= 5; 1247 newreg |= (oldreg & 0x1f); 1248 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1249 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_CFG2) | 1; 1250 sc->sc_dc.dc_writereg(&sc->sc_dc, DBCOOL_ADM1030_CFG2, oldreg); 1251 } 1252 } else { 1253 newreg = (sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg) & 0x1f) | (i << 5); 1254 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1255 } 1256 return 0; 1257 } 1258 1259 static int 1260 sysctl_dbcool_slope(SYSCTLFN_ARGS) 1261 { 1262 struct sysctlnode node; 1263 struct dbcool_softc *sc; 1264 int reg, error; 1265 uint8_t chipreg; 1266 uint8_t newreg; 1267 1268 node = *rnode; 1269 sc = (struct dbcool_softc *)node.sysctl_data; 1270 chipreg = node.sysctl_num & 0xff; 1271 1272 reg = (sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg) >> 4) & 0x0f; 1273 node.sysctl_data = ® 1274 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1275 1276 if (error || newp == NULL) 1277 return error; 1278 1279 /* We were asked to update the value - sanity check before writing */ 1280 if (*(int *)node.sysctl_data < 0 || *(int *)node.sysctl_data > 0x0f) 1281 return EINVAL; 1282 1283 newreg = (sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg) & 0x0f) | 1284 (*(int *)node.sysctl_data << 4); 1285 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1286 return 0; 1287 } 1288 1289 static int 1290 sysctl_dbcool_thyst(SYSCTLFN_ARGS) 1291 { 1292 struct sysctlnode node; 1293 struct dbcool_softc *sc; 1294 int reg, error; 1295 uint8_t chipreg; 1296 uint8_t newreg, newhyst; 1297 1298 node = *rnode; 1299 sc = (struct dbcool_softc *)node.sysctl_data; 1300 chipreg = node.sysctl_num & 0x7f; 1301 1302 /* retrieve 4-bit value */ 1303 newreg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1304 if ((node.sysctl_num & 0x80) == 0) 1305 reg = newreg >> 4; 1306 else 1307 reg = newreg; 1308 reg = reg & 0x0f; 1309 1310 node.sysctl_data = ® 1311 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1312 1313 if (error || newp == NULL) 1314 return error; 1315 1316 /* We were asked to update the value - sanity check before writing */ 1317 newhyst = *(int *)node.sysctl_data; 1318 if (newhyst > 0x0f) 1319 return EINVAL; 1320 1321 /* Insert new value into field and update register */ 1322 if ((node.sysctl_num & 0x80) == 0) { 1323 newreg &= 0x0f; 1324 newreg |= (newhyst << 4); 1325 } else { 1326 newreg &= 0xf0; 1327 newreg |= newhyst; 1328 } 1329 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1330 return 0; 1331 } 1332 1333 #ifdef DBCOOL_DEBUG 1334 1335 /* 1336 * These routines can be used for debugging. reg_select is used to 1337 * select any arbitrary register in the device. reg_access is used 1338 * to read (and optionally update) the selected register. 1339 * 1340 * No attempt is made to validate the data passed. If you use these 1341 * routines, you are assumed to know what you're doing! 1342 * 1343 * Caveat user 1344 */ 1345 static int 1346 sysctl_dbcool_reg_select(SYSCTLFN_ARGS) 1347 { 1348 struct sysctlnode node; 1349 struct dbcool_softc *sc; 1350 int reg, error; 1351 1352 node = *rnode; 1353 sc = (struct dbcool_softc *)node.sysctl_data; 1354 1355 reg = sc->sc_user_reg; 1356 node.sysctl_data = ® 1357 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1358 1359 if (error || newp == NULL) 1360 return error; 1361 1362 sc->sc_user_reg = *(int *)node.sysctl_data; 1363 return 0; 1364 } 1365 1366 static int 1367 sysctl_dbcool_reg_access(SYSCTLFN_ARGS) 1368 { 1369 struct sysctlnode node; 1370 struct dbcool_softc *sc; 1371 int reg, error; 1372 uint8_t chipreg; 1373 uint8_t newreg; 1374 1375 node = *rnode; 1376 sc = (struct dbcool_softc *)node.sysctl_data; 1377 chipreg = sc->sc_user_reg; 1378 1379 reg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1380 node.sysctl_data = ® 1381 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1382 1383 if (error || newp == NULL) 1384 return error; 1385 1386 newreg = *(int *)node.sysctl_data; 1387 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1388 return 0; 1389 } 1390 #endif /* DBCOOL_DEBUG */ 1391 1392 /* 1393 * Encode an index number and register number for use as a sysctl_num 1394 * so we can select the correct device register later. 1395 */ 1396 #define DBC_PWM_SYSCTL(seq, reg) ((seq << 8) | reg) 1397 1398 void 1399 dbcool_setup(device_t self) 1400 { 1401 struct dbcool_softc *sc = device_private(self); 1402 const struct sysctlnode *me = NULL; 1403 #ifdef DBCOOL_DEBUG 1404 struct sysctlnode *node = NULL; 1405 #endif 1406 uint8_t cfg_val, cfg_reg; 1407 int ret, error; 1408 1409 /* 1410 * Some chips are capable of reporting an extended temperature range 1411 * by default. On these models, config register 5 bit 0 can be set 1412 * to 1 for compatability with other chips that report 2s complement. 1413 */ 1414 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) { 1415 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADT7466_CONFIG1) & 0x80) 1416 sc->sc_temp_offset = 64; 1417 else 1418 sc->sc_temp_offset = 0; 1419 } else if (sc->sc_dc.dc_chip->flags & DBCFLAG_TEMPOFFSET) { 1420 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_CONFIG5_REG) & 1421 DBCOOL_CFG5_TWOSCOMP) 1422 sc->sc_temp_offset = 0; 1423 else 1424 sc->sc_temp_offset = 64; 1425 } else 1426 sc->sc_temp_offset = 0; 1427 1428 /* Determine Vcc for this chip */ 1429 sc->sc_supply_voltage = dbcool_supply_voltage(sc); 1430 1431 ret = sysctl_createv(NULL, 0, NULL, &me, 1432 CTLFLAG_READWRITE, 1433 CTLTYPE_NODE, device_xname(self), NULL, 1434 NULL, 0, NULL, 0, 1435 CTL_HW, CTL_CREATE, CTL_EOL); 1436 if (ret == 0) 1437 sc->sc_root_sysctl_num = me->sysctl_num; 1438 else 1439 sc->sc_root_sysctl_num = 0; 1440 1441 aprint_debug_dev(self, 1442 "Supply voltage %"PRId64".%06"PRId64"V, %s temp range\n", 1443 sc->sc_supply_voltage / 1000000, 1444 sc->sc_supply_voltage % 1000000, 1445 sc->sc_temp_offset ? "extended" : "normal"); 1446 1447 /* Create the sensors for this device */ 1448 sc->sc_sme = sysmon_envsys_create(); 1449 if (dbcool_setup_sensors(sc)) 1450 goto out; 1451 1452 if (sc->sc_root_sysctl_num != 0) { 1453 /* If supported, create sysctl tree for fan PWM controllers */ 1454 if (sc->sc_dc.dc_chip->power != NULL) 1455 dbcool_setup_controllers(sc); 1456 1457 #ifdef DBCOOL_DEBUG 1458 ret = sysctl_createv(NULL, 0, NULL, 1459 (const struct sysctlnode **)&node, 1460 CTLFLAG_READWRITE, CTLTYPE_INT, "reg_select", NULL, 1461 sysctl_dbcool_reg_select, 1462 0, sc, sizeof(int), 1463 CTL_HW, me->sysctl_num, CTL_CREATE, CTL_EOL); 1464 if (node != NULL) 1465 node->sysctl_data = sc; 1466 1467 ret = sysctl_createv(NULL, 0, NULL, 1468 (const struct sysctlnode **)&node, 1469 CTLFLAG_READWRITE, CTLTYPE_INT, "reg_access", NULL, 1470 sysctl_dbcool_reg_access, 1471 0, sc, sizeof(int), 1472 CTL_HW, me->sysctl_num, CTL_CREATE, CTL_EOL); 1473 if (node != NULL) 1474 node->sysctl_data = sc; 1475 #endif /* DBCOOL_DEBUG */ 1476 } 1477 1478 /* 1479 * Read and rewrite config register to activate device 1480 */ 1481 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 1482 cfg_reg = DBCOOL_ADM1030_CFG1; 1483 else if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) 1484 cfg_reg = DBCOOL_ADT7466_CONFIG1; 1485 else 1486 cfg_reg = DBCOOL_CONFIG1_REG; 1487 cfg_val = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_CONFIG1_REG); 1488 if ((cfg_val & DBCOOL_CFG1_START) == 0) { 1489 cfg_val |= DBCOOL_CFG1_START; 1490 sc->sc_dc.dc_writereg(&sc->sc_dc, cfg_reg, cfg_val); 1491 } 1492 if (dbcool_islocked(sc)) 1493 aprint_normal_dev(self, "configuration locked\n"); 1494 1495 sc->sc_sme->sme_name = device_xname(self); 1496 sc->sc_sme->sme_cookie = sc; 1497 sc->sc_sme->sme_refresh = dbcool_refresh; 1498 sc->sc_sme->sme_set_limits = dbcool_set_limits; 1499 sc->sc_sme->sme_get_limits = dbcool_get_limits; 1500 1501 if ((error = sysmon_envsys_register(sc->sc_sme)) != 0) { 1502 aprint_error_dev(self, 1503 "unable to register with sysmon (%d)\n", error); 1504 goto out; 1505 } 1506 1507 return; 1508 1509 out: 1510 sysmon_envsys_destroy(sc->sc_sme); 1511 } 1512 1513 static int 1514 dbcool_setup_sensors(struct dbcool_softc *sc) 1515 { 1516 int i; 1517 int error = 0; 1518 uint8_t vid_reg, vid_val; 1519 struct chip_id *chip = sc->sc_dc.dc_chip; 1520 1521 for (i=0; chip->table[i].type != DBC_EOF; i++) { 1522 if (i < DBCOOL_MAXSENSORS) 1523 sc->sc_sysctl_num[i] = -1; 1524 else if (chip->table[i].type != DBC_CTL) { 1525 aprint_normal_dev(sc->sc_dev, "chip table too big!\n"); 1526 break; 1527 } 1528 switch (chip->table[i].type) { 1529 case DBC_TEMP: 1530 sc->sc_sensor[i].units = ENVSYS_STEMP; 1531 sc->sc_sensor[i].flags |= ENVSYS_FMONLIMITS; 1532 error = dbcool_attach_sensor(sc, i); 1533 break; 1534 case DBC_VOLT: 1535 /* 1536 * If 12V-In pin has been reconfigured as 6th bit 1537 * of VID code, don't create a 12V-In sensor 1538 */ 1539 if ((chip->flags & DBCFLAG_HAS_VID_SEL) && 1540 (chip->table[i].reg.val_reg == DBCOOL_12VIN) && 1541 (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VID_REG) & 1542 0x80)) 1543 break; 1544 1545 sc->sc_sensor[i].units = ENVSYS_SVOLTS_DC; 1546 sc->sc_sensor[i].flags |= ENVSYS_FMONLIMITS; 1547 error = dbcool_attach_sensor(sc, i); 1548 break; 1549 case DBC_FAN: 1550 sc->sc_sensor[i].units = ENVSYS_SFANRPM; 1551 sc->sc_sensor[i].flags |= ENVSYS_FMONLIMITS; 1552 error = dbcool_attach_sensor(sc, i); 1553 break; 1554 case DBC_VID: 1555 sc->sc_sensor[i].units = ENVSYS_INTEGER; 1556 sc->sc_sensor[i].flags |= ENVSYS_FMONNOTSUPP; 1557 1558 /* retrieve 5- or 6-bit value */ 1559 vid_reg = chip->table[i].reg.val_reg; 1560 vid_val = sc->sc_dc.dc_readreg(&sc->sc_dc, vid_reg); 1561 if (chip->flags & DBCFLAG_HAS_VID_SEL) 1562 vid_val &= 0x3f; 1563 else 1564 vid_val &= 0x1f; 1565 sc->sc_sensor[i].value_cur = vid_val; 1566 1567 error = dbcool_attach_sensor(sc, i); 1568 break; 1569 case DBC_CTL: 1570 error = dbcool_attach_temp_control(sc, i, chip); 1571 if (error) { 1572 aprint_error_dev(sc->sc_dev, 1573 "attach index %d failed %d\n", 1574 i, error); 1575 error = 0; 1576 } 1577 break; 1578 default: 1579 aprint_error_dev(sc->sc_dev, 1580 "sensor_table index %d has bad type %d\n", 1581 i, chip->table[i].type); 1582 break; 1583 } 1584 if (error) 1585 break; 1586 } 1587 return error; 1588 } 1589 1590 static int 1591 dbcool_attach_sensor(struct dbcool_softc *sc, int idx) 1592 { 1593 int name_index; 1594 int error = 0; 1595 1596 name_index = sc->sc_dc.dc_chip->table[idx].name_index; 1597 strlcpy(sc->sc_sensor[idx].desc, dbc_sensor_names[name_index], 1598 sizeof(sc->sc_sensor[idx].desc)); 1599 sc->sc_regs[idx] = &sc->sc_dc.dc_chip->table[idx].reg; 1600 sc->sc_nom_volt[idx] = sc->sc_dc.dc_chip->table[idx].nom_volt_index; 1601 1602 error = sysmon_envsys_sensor_attach(sc->sc_sme, &sc->sc_sensor[idx]); 1603 return error; 1604 } 1605 1606 static int 1607 dbcool_attach_temp_control(struct dbcool_softc *sc, int idx, 1608 struct chip_id *chip) 1609 { 1610 const struct sysctlnode *me2 = NULL; 1611 struct sysctlnode *node = NULL; 1612 int j, ret, sysctl_index, rw_flag; 1613 uint8_t sysctl_reg; 1614 char name[SYSCTL_NAMELEN]; 1615 1616 /* Search for the corresponding temp sensor */ 1617 for (j = 0; j < idx; j++) { 1618 if (j >= DBCOOL_MAXSENSORS || chip->table[j].type != DBC_TEMP) 1619 continue; 1620 if (chip->table[j].name_index == chip->table[idx].name_index) 1621 break; 1622 } 1623 if (j >= idx) /* Temp sensor not found */ 1624 return ENOENT; 1625 1626 /* create sysctl node for the sensor if not one already there */ 1627 if (sc->sc_sysctl_num[j] == -1) { 1628 ret = sysctl_createv(NULL, 0, NULL, &me2, CTLFLAG_READWRITE, 1629 CTLTYPE_NODE, sc->sc_sensor[j].desc, NULL, 1630 NULL, 0, NULL, 0, 1631 CTL_HW, sc->sc_root_sysctl_num, CTL_CREATE, 1632 CTL_EOL); 1633 if (me2 != NULL) 1634 sc->sc_sysctl_num[j] = me2->sysctl_num; 1635 else 1636 return ret; 1637 } 1638 /* add sysctl leaf node for this control variable */ 1639 sysctl_index = chip->table[idx].sysctl_index; 1640 sysctl_reg = chip->table[idx].reg.val_reg; 1641 strlcpy(name, dbc_sysctl_table[sysctl_index].name, sizeof(name)); 1642 if (dbc_sysctl_table[sysctl_index].lockable && dbcool_islocked(sc)) 1643 rw_flag = CTLFLAG_READONLY | CTLFLAG_OWNDESC; 1644 else 1645 rw_flag = CTLFLAG_READWRITE | CTLFLAG_OWNDESC; 1646 ret = sysctl_createv(NULL, 0, NULL, 1647 (const struct sysctlnode **)&node, rw_flag, 1648 CTLTYPE_INT, name, 1649 dbc_sysctl_table[sysctl_index].desc, 1650 dbc_sysctl_table[sysctl_index].helper, 1651 0, sc, sizeof(int), 1652 CTL_HW, sc->sc_root_sysctl_num, 1653 sc->sc_sysctl_num[j], 1654 DBC_PWM_SYSCTL(idx, sysctl_reg), CTL_EOL); 1655 if (node != NULL) 1656 node->sysctl_data = sc; 1657 1658 return ret; 1659 } 1660 1661 static void 1662 dbcool_setup_controllers(struct dbcool_softc *sc) 1663 { 1664 int i, j, ret, rw_flag; 1665 uint8_t sysctl_reg; 1666 struct chip_id *chip = sc->sc_dc.dc_chip; 1667 const struct sysctlnode *me2 = NULL; 1668 struct sysctlnode *node = NULL; 1669 char name[SYSCTL_NAMELEN]; 1670 1671 for (i = 0; chip->power[i].desc != NULL; i++) { 1672 snprintf(name, sizeof(name), "fan_ctl_%d", i); 1673 ret = sysctl_createv(NULL, 0, NULL, &me2, 1674 CTLFLAG_READWRITE | CTLFLAG_OWNDESC, 1675 CTLTYPE_NODE, name, NULL, 1676 NULL, 0, NULL, 0, 1677 CTL_HW, sc->sc_root_sysctl_num, CTL_CREATE, CTL_EOL); 1678 1679 for (j = DBC_PWM_BEHAVIOR; j < DBC_PWM_LAST_PARAM; j++) { 1680 if (j == DBC_PWM_MAX_DUTY && 1681 (chip->flags & DBCFLAG_HAS_MAXDUTY) == 0) 1682 continue; 1683 sysctl_reg = chip->power[i].power_regs[j]; 1684 if (sysctl_reg == DBCOOL_NO_REG) 1685 continue; 1686 strlcpy(name, dbc_sysctl_table[j].name, sizeof(name)); 1687 if (dbc_sysctl_table[j].lockable && dbcool_islocked(sc)) 1688 rw_flag = CTLFLAG_READONLY | CTLFLAG_OWNDESC; 1689 else 1690 rw_flag = CTLFLAG_READWRITE | CTLFLAG_OWNDESC; 1691 ret = sysctl_createv(NULL, 0, NULL, 1692 (const struct sysctlnode **)&node, rw_flag, 1693 (j == DBC_PWM_BEHAVIOR)? 1694 CTLTYPE_STRING:CTLTYPE_INT, 1695 name, 1696 dbc_sysctl_table[j].desc, 1697 dbc_sysctl_table[j].helper, 1698 0, sc, 1699 ( j == DBC_PWM_BEHAVIOR)? 1700 sizeof(dbcool_cur_behav): sizeof(int), 1701 CTL_HW, sc->sc_root_sysctl_num, me2->sysctl_num, 1702 DBC_PWM_SYSCTL(j, sysctl_reg), CTL_EOL); 1703 if (node != NULL) 1704 node->sysctl_data = sc; 1705 } 1706 } 1707 } 1708 1709 static void 1710 dbcool_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 1711 { 1712 struct dbcool_softc *sc=sme->sme_cookie; 1713 int i, nom_volt_idx, cur; 1714 struct reg_list *reg; 1715 1716 i = edata->sensor; 1717 reg = sc->sc_regs[i]; 1718 1719 edata->state = ENVSYS_SVALID; 1720 switch (edata->units) 1721 { 1722 case ENVSYS_STEMP: 1723 cur = dbcool_read_temp(sc, reg->val_reg, true); 1724 break; 1725 case ENVSYS_SVOLTS_DC: 1726 nom_volt_idx = sc->sc_nom_volt[i]; 1727 cur = dbcool_read_volt(sc, reg->val_reg, nom_volt_idx, 1728 true); 1729 break; 1730 case ENVSYS_SFANRPM: 1731 cur = dbcool_read_rpm(sc, reg->val_reg); 1732 break; 1733 case ENVSYS_INTEGER: 1734 return; 1735 default: 1736 edata->state = ENVSYS_SINVALID; 1737 return; 1738 } 1739 1740 if (cur == 0 && (edata->units != ENVSYS_SFANRPM)) 1741 edata->state = ENVSYS_SINVALID; 1742 1743 /* 1744 * If fan is "stalled" but has no low limit, treat 1745 * it as though the fan is not installed. 1746 */ 1747 else if (edata->units == ENVSYS_SFANRPM && cur == 0 && 1748 !(edata->upropset & (PROP_CRITMIN | PROP_WARNMIN))) 1749 edata->state = ENVSYS_SINVALID; 1750 1751 edata->value_cur = cur; 1752 } 1753 1754 int 1755 dbcool_chip_ident(struct dbcool_chipset *dc) 1756 { 1757 /* verify this is a supported dbCool chip */ 1758 uint8_t c_id, d_id, r_id; 1759 int i; 1760 1761 c_id = dc->dc_readreg(dc, DBCOOL_COMPANYID_REG); 1762 d_id = dc->dc_readreg(dc, DBCOOL_DEVICEID_REG); 1763 r_id = dc->dc_readreg(dc, DBCOOL_REVISION_REG); 1764 1765 for (i = 0; chip_table[i].company != 0; i++) 1766 if ((c_id == chip_table[i].company) && 1767 (d_id == chip_table[i].device || 1768 chip_table[i].device == 0xff) && 1769 (r_id == chip_table[i].rev || 1770 chip_table[i].rev == 0xff)) { 1771 dc->dc_chip = &chip_table[i]; 1772 return i; 1773 } 1774 1775 aprint_verbose("dbcool_chip_ident: addr 0x%02x c_id 0x%02x d_id 0x%02x" 1776 " r_id 0x%02x: No match.\n", dc->dc_addr, c_id, d_id, 1777 r_id); 1778 1779 return -1; 1780 } 1781 1782 /* 1783 * Retrieve sensor limits from the chip registers 1784 */ 1785 static void 1786 dbcool_get_limits(struct sysmon_envsys *sme, envsys_data_t *edata, 1787 sysmon_envsys_lim_t *limits, uint32_t *props) 1788 { 1789 int index = edata->sensor; 1790 struct dbcool_softc *sc = sme->sme_cookie; 1791 1792 *props &= ~(PROP_CRITMIN | PROP_CRITMAX); 1793 switch (edata->units) { 1794 case ENVSYS_STEMP: 1795 dbcool_get_temp_limits(sc, index, limits, props); 1796 break; 1797 case ENVSYS_SVOLTS_DC: 1798 dbcool_get_volt_limits(sc, index, limits, props); 1799 break; 1800 case ENVSYS_SFANRPM: 1801 dbcool_get_fan_limits(sc, index, limits, props); 1802 1803 /* FALLTHROUGH */ 1804 default: 1805 break; 1806 } 1807 *props &= ~PROP_DRIVER_LIMITS; 1808 1809 /* If both limits provided, make sure they're sane */ 1810 if ((*props & PROP_CRITMIN) && 1811 (*props & PROP_CRITMAX) && 1812 (limits->sel_critmin >= limits->sel_critmax)) 1813 *props &= ~(PROP_CRITMIN | PROP_CRITMAX); 1814 } 1815 1816 static void 1817 dbcool_get_temp_limits(struct dbcool_softc *sc, int idx, 1818 sysmon_envsys_lim_t *lims, uint32_t *props) 1819 { 1820 struct reg_list *reg = sc->sc_regs[idx]; 1821 uint8_t lo_lim, hi_lim; 1822 1823 lo_lim = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->lo_lim_reg); 1824 hi_lim = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->hi_lim_reg); 1825 1826 if (sc->sc_temp_offset) { 1827 if (lo_lim > 0x01) { 1828 lims->sel_critmin = lo_lim - sc->sc_temp_offset; 1829 *props |= PROP_CRITMIN; 1830 } 1831 if (hi_lim != 0xff) { 1832 lims->sel_critmax = hi_lim - sc->sc_temp_offset; 1833 *props |= PROP_CRITMAX; 1834 } 1835 } else { 1836 if (lo_lim != 0x80 && lo_lim != 0x81) { 1837 lims->sel_critmin = (int8_t)lo_lim; 1838 *props |= PROP_CRITMIN; 1839 } 1840 1841 if (hi_lim != 0x7f) { 1842 lims->sel_critmax = (int8_t)hi_lim; 1843 *props |= PROP_CRITMAX; 1844 } 1845 } 1846 1847 /* Convert temp limits to microKelvin */ 1848 lims->sel_critmin *= 1000000; 1849 lims->sel_critmin += 273150000; 1850 lims->sel_critmax *= 1000000; 1851 lims->sel_critmax += 273150000; 1852 } 1853 1854 static void 1855 dbcool_get_volt_limits(struct dbcool_softc *sc, int idx, 1856 sysmon_envsys_lim_t *lims, uint32_t *props) 1857 { 1858 struct reg_list *reg = sc->sc_regs[idx]; 1859 int64_t limit; 1860 int nom; 1861 1862 nom = nominal_voltages[sc->sc_dc.dc_chip->table[idx].nom_volt_index]; 1863 if (nom < 0) 1864 nom = dbcool_supply_voltage(sc); 1865 nom *= 1000000; /* scale for microvolts */ 1866 1867 limit = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->lo_lim_reg); 1868 if (limit != 0x00 && limit != 0xff) { 1869 limit *= nom; 1870 limit /= 0xc0; 1871 lims->sel_critmin = limit; 1872 *props |= PROP_CRITMIN; 1873 } 1874 limit = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->hi_lim_reg); 1875 if (limit != 0x00 && limit != 0xff) { 1876 limit *= nom; 1877 limit /= 0xc0; 1878 lims->sel_critmax = limit; 1879 *props |= PROP_CRITMAX; 1880 } 1881 } 1882 1883 static void 1884 dbcool_get_fan_limits(struct dbcool_softc *sc, int idx, 1885 sysmon_envsys_lim_t *lims, uint32_t *props) 1886 { 1887 struct reg_list *reg = sc->sc_regs[idx]; 1888 int32_t limit; 1889 1890 limit = dbcool_read_rpm(sc, reg->lo_lim_reg); 1891 if (limit) { 1892 lims->sel_critmin = limit; 1893 *props |= PROP_CRITMIN; 1894 } 1895 } 1896 1897 /* 1898 * Update sensor limits in the chip registers 1899 */ 1900 static void 1901 dbcool_set_limits(struct sysmon_envsys *sme, envsys_data_t *edata, 1902 sysmon_envsys_lim_t *limits, uint32_t *props) 1903 { 1904 int index = edata->sensor; 1905 struct dbcool_softc *sc = sme->sme_cookie; 1906 1907 switch (edata->units) { 1908 case ENVSYS_STEMP: 1909 dbcool_set_temp_limits(sc, index, limits, props); 1910 break; 1911 case ENVSYS_SVOLTS_DC: 1912 dbcool_set_volt_limits(sc, index, limits, props); 1913 break; 1914 case ENVSYS_SFANRPM: 1915 dbcool_set_fan_limits(sc, index, limits, props); 1916 1917 /* FALLTHROUGH */ 1918 default: 1919 break; 1920 } 1921 *props &= ~PROP_DRIVER_LIMITS; 1922 } 1923 1924 static void 1925 dbcool_set_temp_limits(struct dbcool_softc *sc, int idx, 1926 sysmon_envsys_lim_t *lims, uint32_t *props) 1927 { 1928 struct reg_list *reg = sc->sc_regs[idx]; 1929 int32_t limit; 1930 1931 if (*props & PROP_CRITMIN) { 1932 limit = lims->sel_critmin - 273150000; 1933 limit /= 1000000; 1934 if (sc->sc_temp_offset) { 1935 limit += sc->sc_temp_offset; 1936 if (limit < 0) 1937 limit = 0; 1938 else if (limit > 255) 1939 limit = 255; 1940 } else { 1941 if (limit < -127) 1942 limit = -127; 1943 else if (limit > 127) 1944 limit = 127; 1945 } 1946 } else 1947 if (sc->sc_temp_offset) 1948 limit = 0x00; 1949 else 1950 limit = 0x80; 1951 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, (uint8_t)limit); 1952 1953 if (*props & PROP_CRITMAX) { 1954 limit = lims->sel_critmax - 273150000; 1955 limit /= 1000000; 1956 if (sc->sc_temp_offset) { 1957 limit += sc->sc_temp_offset; 1958 if (limit < 0) 1959 limit = 0; 1960 else if (limit > 255) 1961 limit = 255; 1962 } else { 1963 if (limit < -127) 1964 limit = -127; 1965 else if (limit > 127) 1966 limit = 127; 1967 } 1968 } else 1969 if (sc->sc_temp_offset) 1970 limit = 0xff; 1971 else 1972 limit = 0x7f; 1973 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg, (uint8_t)limit); 1974 } 1975 1976 static void 1977 dbcool_set_volt_limits(struct dbcool_softc *sc, int idx, 1978 sysmon_envsys_lim_t *lims, uint32_t *props) 1979 { 1980 struct reg_list *reg = sc->sc_regs[idx]; 1981 int64_t limit; 1982 int nom; 1983 1984 nom = nominal_voltages[sc->sc_dc.dc_chip->table[idx].nom_volt_index]; 1985 if (nom < 0) 1986 nom = dbcool_supply_voltage(sc); 1987 nom *= 1000000; /* scale for microvolts */ 1988 1989 if (*props & PROP_CRITMIN) { 1990 limit = lims->sel_critmin; 1991 limit *= 0xc0; 1992 limit /= nom; 1993 if (limit > 0xff) 1994 limit = 0xff; 1995 else if (limit < 0) 1996 limit = 0; 1997 } else 1998 limit = 0; 1999 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, limit); 2000 2001 if (*props & PROP_CRITMAX) { 2002 limit = lims->sel_critmax; 2003 limit *= 0xc0; 2004 limit /= nom; 2005 if (limit > 0xff) 2006 limit = 0xff; 2007 else if (limit < 0) 2008 limit = 0; 2009 } else 2010 limit = 0xff; 2011 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg, limit); 2012 } 2013 2014 static void 2015 dbcool_set_fan_limits(struct dbcool_softc *sc, int idx, 2016 sysmon_envsys_lim_t *lims, uint32_t *props) 2017 { 2018 struct reg_list *reg = sc->sc_regs[idx]; 2019 int32_t limit, dividend; 2020 2021 if (*props & PROP_CRITMIN) { 2022 limit = lims->sel_critmin; 2023 if (limit == 0) 2024 limit = 0xffff; 2025 else { 2026 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 2027 dividend = 11250 * 60; 2028 else 2029 dividend = 90000 * 60; 2030 limit = limit / dividend; 2031 if (limit > 0xffff) 2032 limit = 0xffff; 2033 } 2034 } else 2035 limit = 0xffff; 2036 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, limit & 0xff); 2037 limit >>= 8; 2038 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg + 1, limit & 0xff); 2039 } 2040
Indexes created Thu Sep 25 16:09:42 GMT 2025