dbcool.c revision 1.25
1 /* $NetBSD: dbcool.c,v 1.25 2010/08/17 23:36:51 pgoyette Exp $ */ 2 3 /*- 4 * Copyright (c) 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Goyette 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * a driver for the dbCool(tm) family of environmental controllers 34 * 35 * Data sheets for the various supported chips are available at 36 * 37 * http://www.onsemi.com/pub/Collateral/ADM1027-D.PDF 38 * http://www.onsemi.com/pub/Collateral/ADM1030-D.PDF 39 * http://www.onsemi.com/pub/Collateral/ADT7463-D.PDF 40 * http://www.onsemi.com/pub/Collateral/ADT7466.PDF 41 * http://www.onsemi.com/pub/Collateral/ADT7467-D.PDF 42 * http://www.onsemi.com/pub/Collateral/ADT7468-D.PDF 43 * http://www.onsemi.com/pub/Collateral/ADT7473-D.PDF 44 * http://www.onsemi.com/pub/Collateral/ADT7475-D.PDF 45 * http://www.onsemi.com/pub/Collateral/ADT7476-D.PDF 46 * http://www.onsemi.com/pub/Collateral/ADT7490-D.PDF 47 * 48 * (URLs are correct as of October 5, 2008) 49 */ 50 51 #include <sys/cdefs.h> 52 __KERNEL_RCSID(0, "$NetBSD: dbcool.c,v 1.25 2010/08/17 23:36:51 pgoyette Exp $"); 53 54 #include <sys/param.h> 55 #include <sys/systm.h> 56 #include <sys/kernel.h> 57 #include <sys/device.h> 58 #include <sys/malloc.h> 59 #include <sys/sysctl.h> 60 61 #include <uvm/uvm_extern.h> 62 63 #include <dev/i2c/dbcool_var.h> 64 #include <dev/i2c/dbcool_reg.h> 65 66 /* Config interface */ 67 static int dbcool_match(device_t, cfdata_t, void *); 68 static void dbcool_attach(device_t, device_t, void *); 69 static int dbcool_detach(device_t, int); 70 71 /* Device attributes */ 72 static int dbcool_supply_voltage(struct dbcool_softc *); 73 static bool dbcool_islocked(struct dbcool_softc *); 74 75 /* Sensor read functions */ 76 static void dbcool_refresh(struct sysmon_envsys *, envsys_data_t *); 77 static int dbcool_read_rpm(struct dbcool_softc *, uint8_t); 78 static int dbcool_read_temp(struct dbcool_softc *, uint8_t, bool); 79 static int dbcool_read_volt(struct dbcool_softc *, uint8_t, int, bool); 80 81 /* Sensor get/set limit functions */ 82 static void dbcool_get_limits(struct sysmon_envsys *, envsys_data_t *, 83 sysmon_envsys_lim_t *, uint32_t *); 84 static void dbcool_get_temp_limits(struct dbcool_softc *, int, 85 sysmon_envsys_lim_t *, uint32_t *); 86 static void dbcool_get_volt_limits(struct dbcool_softc *, int, 87 sysmon_envsys_lim_t *, uint32_t *); 88 static void dbcool_get_fan_limits(struct dbcool_softc *, int, 89 sysmon_envsys_lim_t *, uint32_t *); 90 91 static void dbcool_set_limits(struct sysmon_envsys *, envsys_data_t *, 92 sysmon_envsys_lim_t *, uint32_t *); 93 static void dbcool_set_temp_limits(struct dbcool_softc *, int, 94 sysmon_envsys_lim_t *, uint32_t *); 95 static void dbcool_set_volt_limits(struct dbcool_softc *, int, 96 sysmon_envsys_lim_t *, uint32_t *); 97 static void dbcool_set_fan_limits(struct dbcool_softc *, int, 98 sysmon_envsys_lim_t *, uint32_t *); 99 100 /* SYSCTL Helpers */ 101 static int sysctl_dbcool_temp(SYSCTLFN_PROTO); 102 static int sysctl_adm1030_temp(SYSCTLFN_PROTO); 103 static int sysctl_adm1030_trange(SYSCTLFN_PROTO); 104 static int sysctl_dbcool_duty(SYSCTLFN_PROTO); 105 static int sysctl_dbcool_behavior(SYSCTLFN_PROTO); 106 static int sysctl_dbcool_slope(SYSCTLFN_PROTO); 107 static int sysctl_dbcool_thyst(SYSCTLFN_PROTO); 108 109 /* Set-up subroutines */ 110 static void dbcool_setup_controllers(struct dbcool_softc *); 111 static int dbcool_setup_sensors(struct dbcool_softc *); 112 static int dbcool_attach_sensor(struct dbcool_softc *, int); 113 static int dbcool_attach_temp_control(struct dbcool_softc *, int, 114 struct chip_id *); 115 116 #ifdef DBCOOL_DEBUG 117 static int sysctl_dbcool_reg_select(SYSCTLFN_PROTO); 118 static int sysctl_dbcool_reg_access(SYSCTLFN_PROTO); 119 #endif /* DBCOOL_DEBUG */ 120 121 /* 122 * Descriptions for SYSCTL entries 123 */ 124 struct dbc_sysctl_info { 125 const char *name; 126 const char *desc; 127 bool lockable; 128 int (*helper)(SYSCTLFN_PROTO); 129 }; 130 131 static struct dbc_sysctl_info dbc_sysctl_table[] = { 132 /* 133 * The first several entries must remain in the same order as the 134 * corresponding entries in enum dbc_pwm_params 135 */ 136 { "behavior", "operating behavior and temp selector", 137 true, sysctl_dbcool_behavior }, 138 { "min_duty", "minimum fan controller PWM duty cycle", 139 true, sysctl_dbcool_duty }, 140 { "max_duty", "maximum fan controller PWM duty cycle", 141 true, sysctl_dbcool_duty }, 142 { "cur_duty", "current fan controller PWM duty cycle", 143 false, sysctl_dbcool_duty }, 144 145 /* 146 * The rest of these should be in the order in which they 147 * are to be stored in the sysctl tree; the table index is 148 * used as the high-order bits of the sysctl_num to maintain 149 * the sequence. 150 * 151 * If you rearrange the order of these items, be sure to 152 * update the sysctl_index in the XXX_sensor_table[] for 153 * the various chips! 154 */ 155 { "Trange", "temp slope/range to reach 100% duty cycle", 156 true, sysctl_dbcool_slope }, 157 { "Tmin", "temp at which to start fan controller", 158 true, sysctl_dbcool_temp }, 159 { "Ttherm", "temp at which THERM is asserted", 160 true, sysctl_dbcool_temp }, 161 { "Thyst", "temp hysteresis for stopping fan controller", 162 true, sysctl_dbcool_thyst }, 163 { "Tmin", "temp at which to start fan controller", 164 true, sysctl_adm1030_temp }, 165 { "Trange", "temp slope/range to reach 100% duty cycle", 166 true, sysctl_adm1030_trange }, 167 }; 168 169 static const char *dbc_sensor_names[] = { 170 "l_temp", "r1_temp", "r2_temp", "Vccp", "Vcc", "fan1", 171 "fan2", "fan3", "fan4", "AIN1", "AIN2", "V2dot5", 172 "V5", "V12", "Vtt", "Imon", "VID" 173 }; 174 175 /* 176 * Following table derived from product data-sheets 177 */ 178 static int64_t nominal_voltages[] = { 179 -1, /* Vcc can be either 3.3 or 5.0V 180 at 3/4 scale */ 181 2249939, /* Vccp 2.25V 3/4 scale */ 182 2497436, /* 2.5VIN 2.5V 3/4 scale */ 183 5002466, /* 5VIN 5V 3/4 scale */ 184 12000000, /* 12VIN 12V 3/4 scale */ 185 1690809, /* Vtt, Imon 2.25V full scale */ 186 1689600, /* AIN1, AIN2 2.25V full scale */ 187 0 188 }; 189 190 /* 191 * Sensor-type, { val-reg, hilim-reg, lolim-reg}, name-idx, sysctl-table-idx, 192 * nom-voltage-index 193 */ 194 struct dbcool_sensor ADT7490_sensor_table[] = { 195 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 196 DBCOOL_LOCAL_HIGHLIM, 197 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 198 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 199 DBCOOL_REMOTE1_HIGHLIM, 200 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 201 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 202 DBCOOL_REMOTE2_HIGHLIM, 203 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 204 { DBC_VOLT, { DBCOOL_VCCP, 205 DBCOOL_VCCP_HIGHLIM, 206 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 207 { DBC_VOLT, { DBCOOL_VCC, 208 DBCOOL_VCC_HIGHLIM, 209 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 210 { DBC_VOLT, { DBCOOL_25VIN, 211 DBCOOL_25VIN_HIGHLIM, 212 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 }, 213 { DBC_VOLT, { DBCOOL_5VIN, 214 DBCOOL_5VIN_HIGHLIM, 215 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 }, 216 { DBC_VOLT, { DBCOOL_12VIN, 217 DBCOOL_12VIN_HIGHLIM, 218 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 }, 219 { DBC_VOLT, { DBCOOL_VTT, 220 DBCOOL_VTT_HIGHLIM, 221 DBCOOL_VTT_LOWLIM }, 14, 0, 5 }, 222 { DBC_VOLT, { DBCOOL_IMON, 223 DBCOOL_IMON_HIGHLIM, 224 DBCOOL_IMON_LOWLIM }, 15, 0, 5 }, 225 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 226 DBCOOL_NO_REG, 227 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 228 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 229 DBCOOL_NO_REG, 230 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 231 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 232 DBCOOL_NO_REG, 233 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 234 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 235 DBCOOL_NO_REG, 236 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 237 { DBC_VID, { DBCOOL_VID_REG, 238 DBCOOL_NO_REG, 239 DBCOOL_NO_REG }, 16, 0, 0 }, 240 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 241 DBCOOL_NO_REG, 242 DBCOOL_NO_REG }, 0, 5, 0 }, 243 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 244 DBCOOL_NO_REG, 245 DBCOOL_NO_REG }, 0, 6, 0 }, 246 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 247 DBCOOL_NO_REG, 248 DBCOOL_NO_REG }, 0, 7, 0 }, 249 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 250 DBCOOL_NO_REG, 251 DBCOOL_NO_REG }, 1, 5, 0 }, 252 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 253 DBCOOL_NO_REG, 254 DBCOOL_NO_REG }, 1, 6, 0 }, 255 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 256 DBCOOL_NO_REG, 257 DBCOOL_NO_REG }, 1, 7, 0 }, 258 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 259 DBCOOL_NO_REG, 260 DBCOOL_NO_REG }, 2, 5, 0 }, 261 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 262 DBCOOL_NO_REG, 263 DBCOOL_NO_REG }, 2, 6, 0 }, 264 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 265 DBCOOL_NO_REG, 266 DBCOOL_NO_REG }, 2, 7, 0 }, 267 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 268 }; 269 270 struct dbcool_sensor ADT7476_sensor_table[] = { 271 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 272 DBCOOL_LOCAL_HIGHLIM, 273 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 274 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 275 DBCOOL_REMOTE1_HIGHLIM, 276 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 277 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 278 DBCOOL_REMOTE2_HIGHLIM, 279 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 280 { DBC_VOLT, { DBCOOL_VCCP, 281 DBCOOL_VCCP_HIGHLIM, 282 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 283 { DBC_VOLT, { DBCOOL_VCC, 284 DBCOOL_VCC_HIGHLIM, 285 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 286 { DBC_VOLT, { DBCOOL_25VIN, 287 DBCOOL_25VIN_HIGHLIM, 288 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 }, 289 { DBC_VOLT, { DBCOOL_5VIN, 290 DBCOOL_5VIN_HIGHLIM, 291 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 }, 292 { DBC_VOLT, { DBCOOL_12VIN, 293 DBCOOL_12VIN_HIGHLIM, 294 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 }, 295 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 296 DBCOOL_NO_REG, 297 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 298 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 299 DBCOOL_NO_REG, 300 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 301 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 302 DBCOOL_NO_REG, 303 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 304 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 305 DBCOOL_NO_REG, 306 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 307 { DBC_VID, { DBCOOL_VID_REG, 308 DBCOOL_NO_REG, 309 DBCOOL_NO_REG }, 16, 0, 0 }, 310 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 311 DBCOOL_NO_REG, 312 DBCOOL_NO_REG }, 0, 5, 0 }, 313 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 314 DBCOOL_NO_REG, 315 DBCOOL_NO_REG }, 0, 6, 0 }, 316 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 317 DBCOOL_NO_REG, 318 DBCOOL_NO_REG }, 0, 7, 0 }, 319 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 320 DBCOOL_NO_REG, 321 DBCOOL_NO_REG }, 1, 5, 0 }, 322 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 323 DBCOOL_NO_REG, 324 DBCOOL_NO_REG }, 1, 6, 0 }, 325 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 326 DBCOOL_NO_REG, 327 DBCOOL_NO_REG }, 1, 7, 0 }, 328 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 329 DBCOOL_NO_REG, 330 DBCOOL_NO_REG }, 2, 5, 0 }, 331 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 332 DBCOOL_NO_REG, 333 DBCOOL_NO_REG }, 2, 6, 0 }, 334 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 335 DBCOOL_NO_REG, 336 DBCOOL_NO_REG }, 2, 7, 0 }, 337 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 338 }; 339 340 struct dbcool_sensor ADT7475_sensor_table[] = { 341 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 342 DBCOOL_LOCAL_HIGHLIM, 343 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 344 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 345 DBCOOL_REMOTE1_HIGHLIM, 346 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 347 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 348 DBCOOL_REMOTE2_HIGHLIM, 349 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 350 { DBC_VOLT, { DBCOOL_VCCP, 351 DBCOOL_VCCP_HIGHLIM, 352 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 353 { DBC_VOLT, { DBCOOL_VCC, 354 DBCOOL_VCC_HIGHLIM, 355 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 356 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 357 DBCOOL_NO_REG, 358 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 359 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 360 DBCOOL_NO_REG, 361 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 362 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 363 DBCOOL_NO_REG, 364 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 365 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 366 DBCOOL_NO_REG, 367 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 368 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 369 DBCOOL_NO_REG, 370 DBCOOL_NO_REG }, 0, 5, 0 }, 371 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 372 DBCOOL_NO_REG, 373 DBCOOL_NO_REG }, 0, 6, 0 }, 374 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 375 DBCOOL_NO_REG, 376 DBCOOL_NO_REG }, 0, 7, 0 }, 377 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 378 DBCOOL_NO_REG, 379 DBCOOL_NO_REG }, 1, 5, 0 }, 380 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 381 DBCOOL_NO_REG, 382 DBCOOL_NO_REG }, 1, 6, 0 }, 383 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 384 DBCOOL_NO_REG, 385 DBCOOL_NO_REG }, 1, 7, 0 }, 386 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 387 DBCOOL_NO_REG, 388 DBCOOL_NO_REG }, 2, 5, 0 }, 389 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 390 DBCOOL_NO_REG, 391 DBCOOL_NO_REG }, 2, 6, 0 }, 392 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 393 DBCOOL_NO_REG, 394 DBCOOL_NO_REG }, 2, 7, 0 }, 395 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 396 }; 397 398 /* 399 * The registers of dbcool_power_control must be in the same order as 400 * in enum dbc_pwm_params 401 */ 402 struct dbcool_power_control ADT7475_power_table[] = { 403 { { DBCOOL_PWM1_CTL, DBCOOL_PWM1_MINDUTY, 404 DBCOOL_PWM1_MAXDUTY, DBCOOL_PWM1_CURDUTY }, 405 "fan_control_1" }, 406 { { DBCOOL_PWM2_CTL, DBCOOL_PWM2_MINDUTY, 407 DBCOOL_PWM2_MAXDUTY, DBCOOL_PWM2_CURDUTY }, 408 "fan_control_2" }, 409 { { DBCOOL_PWM3_CTL, DBCOOL_PWM3_MINDUTY, 410 DBCOOL_PWM3_MAXDUTY, DBCOOL_PWM3_CURDUTY }, 411 "fan_control_3" }, 412 { { 0, 0, 0, 0 }, NULL } 413 }; 414 415 struct dbcool_sensor ADT7466_sensor_table[] = { 416 { DBC_TEMP, { DBCOOL_ADT7466_LCL_TEMP_MSB, 417 DBCOOL_ADT7466_LCL_TEMP_HILIM, 418 DBCOOL_ADT7466_LCL_TEMP_LOLIM }, 0, 0, 0 }, 419 { DBC_TEMP, { DBCOOL_ADT7466_REM_TEMP_MSB, 420 DBCOOL_ADT7466_REM_TEMP_HILIM, 421 DBCOOL_ADT7466_REM_TEMP_LOLIM }, 1, 0, 0 }, 422 { DBC_VOLT, { DBCOOL_ADT7466_VCC, 423 DBCOOL_ADT7466_VCC_HILIM, 424 DBCOOL_ADT7466_VCC_LOLIM }, 4, 0, 0 }, 425 { DBC_VOLT, { DBCOOL_ADT7466_AIN1, 426 DBCOOL_ADT7466_AIN1_HILIM, 427 DBCOOL_ADT7466_AIN1_LOLIM }, 9, 0, 6 }, 428 { DBC_VOLT, { DBCOOL_ADT7466_AIN2, 429 DBCOOL_ADT7466_AIN2_HILIM, 430 DBCOOL_ADT7466_AIN2_LOLIM }, 10, 0, 6 }, 431 { DBC_FAN, { DBCOOL_ADT7466_FANA_LSB, 432 DBCOOL_NO_REG, 433 DBCOOL_ADT7466_FANA_LOLIM_LSB }, 5, 0, 0 }, 434 { DBC_FAN, { DBCOOL_ADT7466_FANB_LSB, 435 DBCOOL_NO_REG, 436 DBCOOL_ADT7466_FANB_LOLIM_LSB }, 6, 0, 0 }, 437 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 438 }; 439 440 struct dbcool_sensor ADM1027_sensor_table[] = { 441 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 442 DBCOOL_LOCAL_HIGHLIM, 443 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 444 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 445 DBCOOL_REMOTE1_HIGHLIM, 446 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 447 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 448 DBCOOL_REMOTE2_HIGHLIM, 449 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 450 { DBC_VOLT, { DBCOOL_VCCP, 451 DBCOOL_VCCP_HIGHLIM, 452 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 453 { DBC_VOLT, { DBCOOL_VCC, 454 DBCOOL_VCC_HIGHLIM, 455 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 456 { DBC_VOLT, { DBCOOL_25VIN, 457 DBCOOL_25VIN_HIGHLIM, 458 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 }, 459 { DBC_VOLT, { DBCOOL_5VIN, 460 DBCOOL_5VIN_HIGHLIM, 461 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 }, 462 { DBC_VOLT, { DBCOOL_12VIN, 463 DBCOOL_12VIN_HIGHLIM, 464 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 }, 465 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 466 DBCOOL_NO_REG, 467 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 468 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 469 DBCOOL_NO_REG, 470 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 471 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 472 DBCOOL_NO_REG, 473 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 474 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 475 DBCOOL_NO_REG, 476 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 477 { DBC_VID, { DBCOOL_VID_REG, 478 DBCOOL_NO_REG, 479 DBCOOL_NO_REG }, 16, 0, 0 }, 480 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 481 DBCOOL_NO_REG, 482 DBCOOL_NO_REG }, 0, 5, 0 }, 483 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 484 DBCOOL_NO_REG, 485 DBCOOL_NO_REG }, 0, 6, 0 }, 486 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 487 DBCOOL_NO_REG, 488 DBCOOL_NO_REG }, 0, 7, 0 }, 489 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 490 DBCOOL_NO_REG, 491 DBCOOL_NO_REG }, 1, 5, 0 }, 492 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 493 DBCOOL_NO_REG, 494 DBCOOL_NO_REG }, 1, 6, 0 }, 495 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 496 DBCOOL_NO_REG, 497 DBCOOL_NO_REG }, 1, 7, 0 }, 498 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 499 DBCOOL_NO_REG, 500 DBCOOL_NO_REG }, 2, 5, 0 }, 501 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 502 DBCOOL_NO_REG, 503 DBCOOL_NO_REG }, 2, 6, 0 }, 504 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 505 DBCOOL_NO_REG, 506 DBCOOL_NO_REG }, 2, 7, 0 }, 507 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 508 }; 509 510 struct dbcool_sensor ADM1030_sensor_table[] = { 511 { DBC_TEMP, { DBCOOL_ADM1030_L_TEMP, 512 DBCOOL_ADM1030_L_HI_LIM, 513 DBCOOL_ADM1030_L_LO_LIM }, 0, 0, 0 }, 514 { DBC_TEMP, { DBCOOL_ADM1030_R_TEMP, 515 DBCOOL_ADM1030_R_HI_LIM, 516 DBCOOL_ADM1030_R_LO_LIM }, 1, 0, 0 }, 517 { DBC_FAN, { DBCOOL_ADM1030_FAN_TACH, 518 DBCOOL_NO_REG, 519 DBCOOL_ADM1030_FAN_LO_LIM }, 5, 0, 0 }, 520 { DBC_CTL, { DBCOOL_ADM1030_L_TMIN, 521 DBCOOL_NO_REG, 522 DBCOOL_NO_REG }, 0, 8, 0 }, 523 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH, 524 DBCOOL_NO_REG, 525 DBCOOL_NO_REG }, 0, 9, 0 }, 526 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH, 527 DBCOOL_NO_REG, 528 DBCOOL_NO_REG }, 0, 6, 0 }, 529 { DBC_CTL, { DBCOOL_ADM1030_R_TMIN, 530 DBCOOL_NO_REG, 531 DBCOOL_NO_REG }, 1, 8, 0 }, 532 { DBC_CTL, { DBCOOL_ADM1030_R_TTHRESH, 533 DBCOOL_NO_REG, 534 DBCOOL_NO_REG }, 1, 9, 0 }, 535 { DBC_CTL, { DBCOOL_ADM1030_R_TTHRESH, 536 DBCOOL_NO_REG, 537 DBCOOL_NO_REG }, 1, 6, 0 }, 538 { DBC_EOF, {0, 0, 0 }, 0, 0, 0 } 539 }; 540 541 struct dbcool_power_control ADM1030_power_table[] = { 542 { { DBCOOL_ADM1030_CFG1, DBCOOL_NO_REG, DBCOOL_NO_REG, 543 DBCOOL_ADM1030_FAN_SPEED_CFG }, 544 "fan_control_1" }, 545 { { 0, 0, 0, 0 }, NULL } 546 }; 547 548 struct dbcool_sensor ADM1031_sensor_table[] = { 549 { DBC_TEMP, { DBCOOL_ADM1030_L_TEMP, 550 DBCOOL_ADM1030_L_HI_LIM, 551 DBCOOL_ADM1030_L_LO_LIM }, 0, 0, 0 }, 552 { DBC_TEMP, { DBCOOL_ADM1030_R_TEMP, 553 DBCOOL_ADM1030_R_HI_LIM, 554 DBCOOL_ADM1030_R_LO_LIM }, 1, 0, 0 }, 555 { DBC_TEMP, { DBCOOL_ADM1031_R2_TEMP, 556 DBCOOL_ADM1031_R2_HI_LIM, 557 DBCOOL_ADM1031_R2_LO_LIM }, 2, 0, 0 }, 558 { DBC_FAN, { DBCOOL_ADM1030_FAN_TACH, 559 DBCOOL_NO_REG, 560 DBCOOL_ADM1030_FAN_LO_LIM }, 5, 0, 0 }, 561 { DBC_FAN, { DBCOOL_ADM1031_FAN2_TACH, 562 DBCOOL_NO_REG, 563 DBCOOL_ADM1031_FAN2_LO_LIM }, 6, 0, 0 }, 564 { DBC_CTL, { DBCOOL_ADM1030_L_TMIN, 565 DBCOOL_NO_REG, 566 DBCOOL_NO_REG }, 0, 8, 0 }, 567 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH, 568 DBCOOL_NO_REG, 569 DBCOOL_NO_REG }, 0, 9, 0 }, 570 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH, 571 DBCOOL_NO_REG, 572 DBCOOL_NO_REG }, 0, 6, 0 }, 573 { DBC_CTL, { DBCOOL_ADM1030_R_TMIN, 574 DBCOOL_NO_REG, 575 DBCOOL_NO_REG }, 1, 8, 0 }, 576 { DBC_CTL, { DBCOOL_ADM1030_R_TTHRESH, 577 DBCOOL_NO_REG, 578 DBCOOL_NO_REG }, 1, 9, 0 }, 579 { DBC_CTL, { DBCOOL_ADM1030_R_TTHRESH, 580 DBCOOL_NO_REG, 581 DBCOOL_NO_REG }, 1, 6, 0 }, 582 { DBC_CTL, { DBCOOL_ADM1031_R2_TMIN, 583 DBCOOL_NO_REG, 584 DBCOOL_NO_REG }, 2, 8, 0 }, 585 { DBC_CTL, { DBCOOL_ADM1031_R2_TTHRESH, 586 DBCOOL_NO_REG, 587 DBCOOL_NO_REG }, 2, 9, 0 }, 588 { DBC_CTL, { DBCOOL_ADM1031_R2_TTHRESH, 589 DBCOOL_NO_REG, 590 DBCOOL_NO_REG }, 2, 6, 0 }, 591 { DBC_EOF, {0, 0, 0 }, 0, 0, 0 } 592 }; 593 594 struct dbcool_power_control ADM1031_power_table[] = { 595 { { DBCOOL_ADM1030_CFG1, DBCOOL_NO_REG, DBCOOL_NO_REG, 596 DBCOOL_ADM1030_FAN_SPEED_CFG }, 597 "fan_control_1" }, 598 { { DBCOOL_ADM1030_CFG1, DBCOOL_NO_REG, DBCOOL_NO_REG, 599 DBCOOL_ADM1030_FAN_SPEED_CFG }, 600 "fan_control_2" }, 601 { { 0, 0, 0, 0 }, NULL } 602 }; 603 struct chip_id chip_table[] = { 604 { DBCOOL_COMPANYID, ADT7490_DEVICEID, ADT7490_REV_ID, 605 ADT7490_sensor_table, ADT7475_power_table, 606 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_PECI, 607 90000 * 60, "ADT7490" }, 608 { DBCOOL_COMPANYID, ADT7476_DEVICEID, 0xff, 609 ADT7476_sensor_table, ADT7475_power_table, 610 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY, 611 90000 * 60, "ADT7476" }, 612 { DBCOOL_COMPANYID, ADT7475_DEVICEID, 0xff, 613 ADT7475_sensor_table, ADT7475_power_table, 614 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_SHDN, 615 90000 * 60, "ADT7475" }, 616 { DBCOOL_COMPANYID, ADT7473_DEVICEID, ADT7473_REV_ID1, 617 ADT7475_sensor_table, ADT7475_power_table, 618 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_SHDN, 619 90000 * 60, "ADT7460/ADT7463" }, 620 { DBCOOL_COMPANYID, ADT7473_DEVICEID, ADT7473_REV_ID2, 621 ADT7475_sensor_table, ADT7475_power_table, 622 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_SHDN, 623 90000 * 60, "ADT7463-1" }, 624 { DBCOOL_COMPANYID, ADT7468_DEVICEID, 0xff, 625 ADT7476_sensor_table, ADT7475_power_table, 626 DBCFLAG_TEMPOFFSET | DBCFLAG_MULTI_VCC | DBCFLAG_HAS_MAXDUTY | 627 DBCFLAG_4BIT_VER | DBCFLAG_HAS_SHDN, 628 90000 * 60, "ADT7467/ADT7468" }, 629 { DBCOOL_COMPANYID, ADT7466_DEVICEID, 0xff, 630 ADT7466_sensor_table, NULL, 631 DBCFLAG_ADT7466 | DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_SHDN, 632 82000 * 60, "ADT7466" }, 633 { DBCOOL_COMPANYID, ADT7463_DEVICEID, ADT7463_REV_ID1, 634 ADM1027_sensor_table, ADT7475_power_table, 635 DBCFLAG_MULTI_VCC | DBCFLAG_4BIT_VER | DBCFLAG_HAS_SHDN, 636 90000 * 60, "ADT7463" }, 637 { DBCOOL_COMPANYID, ADT7463_DEVICEID, ADT7463_REV_ID2, 638 ADM1027_sensor_table, ADT7475_power_table, 639 DBCFLAG_MULTI_VCC | DBCFLAG_4BIT_VER | DBCFLAG_HAS_SHDN | 640 DBCFLAG_HAS_VID_SEL, 641 90000 * 60, "ADT7463" }, 642 { DBCOOL_COMPANYID, ADM1027_DEVICEID, ADM1027_REV_ID, 643 ADM1027_sensor_table, ADT7475_power_table, 644 DBCFLAG_MULTI_VCC | DBCFLAG_4BIT_VER, 645 90000 * 60, "ADM1027" }, 646 { DBCOOL_COMPANYID, ADM1030_DEVICEID, 0xff, 647 ADM1030_sensor_table, ADM1030_power_table, 648 DBCFLAG_ADM1030 | DBCFLAG_NO_READBYTE, 649 11250 * 60, "ADM1030" }, 650 { DBCOOL_COMPANYID, ADM1031_DEVICEID, 0xff, 651 ADM1031_sensor_table, ADM1030_power_table, 652 DBCFLAG_ADM1030 | DBCFLAG_NO_READBYTE, 653 11250 * 60, "ADM1031" }, 654 { 0, 0, 0, NULL, NULL, 0, 0, NULL } 655 }; 656 657 static const char *behavior[] = { 658 "remote1", "local", "remote2", "full-speed", 659 "disabled", "local+remote2","all-temps", "manual" 660 }; 661 662 static char dbcool_cur_behav[16]; 663 664 CFATTACH_DECL_NEW(dbcool, sizeof(struct dbcool_softc), 665 dbcool_match, dbcool_attach, dbcool_detach, NULL); 666 667 int 668 dbcool_match(device_t parent, cfdata_t cf, void *aux) 669 { 670 struct i2c_attach_args *ia = aux; 671 struct dbcool_chipset dc; 672 dc.dc_tag = ia->ia_tag; 673 dc.dc_addr = ia->ia_addr; 674 dc.dc_chip = NULL; 675 dc.dc_readreg = dbcool_readreg; 676 dc.dc_writereg = dbcool_writereg; 677 678 /* no probing if we attach to iic, but verify chip id and address */ 679 if ((ia->ia_addr & DBCOOL_ADDRMASK) != DBCOOL_ADDR) 680 return 0; 681 if (dbcool_chip_ident(&dc) >= 0) 682 return 1; 683 684 return 0; 685 } 686 687 void 688 dbcool_attach(device_t parent, device_t self, void *aux) 689 { 690 struct dbcool_softc *sc = device_private(self); 691 struct i2c_attach_args *args = aux; 692 uint8_t ver; 693 694 sc->sc_dc.dc_addr = args->ia_addr; 695 sc->sc_dc.dc_tag = args->ia_tag; 696 sc->sc_dc.dc_chip = NULL; 697 sc->sc_dc.dc_readreg = dbcool_readreg; 698 sc->sc_dc.dc_writereg = dbcool_writereg; 699 (void)dbcool_chip_ident(&sc->sc_dc); 700 sc->sc_dev = self; 701 702 aprint_naive("\n"); 703 aprint_normal("\n"); 704 705 ver = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_REVISION_REG); 706 if (sc->sc_dc.dc_chip->flags & DBCFLAG_4BIT_VER) 707 aprint_normal_dev(self, "%s dBCool(tm) Controller " 708 "(rev 0x%02x, stepping 0x%02x)\n", sc->sc_dc.dc_chip->name, 709 ver >> 4, ver & 0x0f); 710 else 711 aprint_normal_dev(self, "%s dBCool(tm) Controller " 712 "(rev 0x%04x)\n", sc->sc_dc.dc_chip->name, ver); 713 714 dbcool_setup(self); 715 716 if (!pmf_device_register(self, dbcool_pmf_suspend, dbcool_pmf_resume)) 717 aprint_error_dev(self, "couldn't establish power handler\n"); 718 } 719 720 static int 721 dbcool_detach(device_t self, int flags) 722 { 723 struct dbcool_softc *sc = device_private(self); 724 725 sysmon_envsys_unregister(sc->sc_sme); 726 sc->sc_sme = NULL; 727 return 0; 728 } 729 730 /* On suspend, we save the state of the SHDN bit, then set it */ 731 bool dbcool_pmf_suspend(device_t dev, const pmf_qual_t *qual) 732 { 733 struct dbcool_softc *sc = device_private(dev); 734 uint8_t reg, bit, cfg; 735 736 if ((sc->sc_dc.dc_chip->flags && DBCFLAG_HAS_SHDN) == 0) 737 return true; 738 739 if (sc->sc_dc.dc_chip->flags && DBCFLAG_ADT7466) { 740 reg = DBCOOL_ADT7466_CONFIG2; 741 bit = DBCOOL_ADT7466_CFG2_SHDN; 742 } else { 743 reg = DBCOOL_CONFIG2_REG; 744 bit = DBCOOL_CFG2_SHDN; 745 } 746 cfg = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 747 sc->sc_suspend = cfg & bit; 748 cfg |= bit; 749 sc->sc_dc.dc_writereg(&sc->sc_dc, reg, cfg); 750 751 return true; 752 } 753 754 /* On resume, we restore the previous state of the SHDN bit */ 755 bool dbcool_pmf_resume(device_t dev, const pmf_qual_t *qual) 756 { 757 struct dbcool_softc *sc = device_private(dev); 758 uint8_t reg, bit, cfg; 759 760 if ((sc->sc_dc.dc_chip->flags && DBCFLAG_HAS_SHDN) == 0) 761 return true; 762 763 if (sc->sc_dc.dc_chip->flags && DBCFLAG_ADT7466) { 764 reg = DBCOOL_ADT7466_CONFIG2; 765 bit = DBCOOL_ADT7466_CFG2_SHDN; 766 } else { 767 reg = DBCOOL_CONFIG2_REG; 768 bit = DBCOOL_CFG2_SHDN; 769 } 770 cfg = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 771 cfg &= ~sc->sc_suspend; 772 sc->sc_dc.dc_writereg(&sc->sc_dc, reg, cfg); 773 774 return true; 775 776 } 777 778 uint8_t 779 dbcool_readreg(struct dbcool_chipset *dc, uint8_t reg) 780 { 781 uint8_t data = 0; 782 783 if (iic_acquire_bus(dc->dc_tag, 0) != 0) 784 return data; 785 786 if (dc->dc_chip == NULL || dc->dc_chip->flags & DBCFLAG_NO_READBYTE) { 787 /* ADM1027 doesn't support i2c read_byte protocol */ 788 if (iic_smbus_send_byte(dc->dc_tag, dc->dc_addr, reg, 0) != 0) 789 goto bad; 790 (void)iic_smbus_receive_byte(dc->dc_tag, dc->dc_addr, &data, 0); 791 } else 792 (void)iic_smbus_read_byte(dc->dc_tag, dc->dc_addr, reg, &data, 793 0); 794 795 bad: 796 iic_release_bus(dc->dc_tag, 0); 797 return data; 798 } 799 800 void 801 dbcool_writereg(struct dbcool_chipset *dc, uint8_t reg, uint8_t val) 802 { 803 if (iic_acquire_bus(dc->dc_tag, 0) != 0) 804 return; 805 806 (void)iic_smbus_write_byte(dc->dc_tag, dc->dc_addr, reg, val, 0); 807 808 iic_release_bus(dc->dc_tag, 0); 809 } 810 811 static bool 812 dbcool_islocked(struct dbcool_softc *sc) 813 { 814 uint8_t cfg_reg; 815 816 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 817 return 0; 818 819 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) 820 cfg_reg = DBCOOL_ADT7466_CONFIG1; 821 else 822 cfg_reg = DBCOOL_CONFIG1_REG; 823 824 if (sc->sc_dc.dc_readreg(&sc->sc_dc, cfg_reg) & DBCOOL_CFG1_LOCK) 825 return 1; 826 else 827 return 0; 828 } 829 830 static int 831 dbcool_read_temp(struct dbcool_softc *sc, uint8_t reg, bool extres) 832 { 833 uint8_t t1, t2, t3, val, ext = 0; 834 int temp; 835 836 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) { 837 /* 838 * ADT7466 temps are in strange location 839 */ 840 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADT7466_CONFIG1); 841 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 842 if (extres) 843 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, reg + 1); 844 } else if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) { 845 /* 846 * ADM1030 temps are in their own special place, too 847 */ 848 if (extres) { 849 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_TEMP_EXTRES); 850 if (reg == DBCOOL_ADM1030_L_TEMP) 851 ext >>= 6; 852 else if (reg == DBCOOL_ADM1031_R2_TEMP) 853 ext >>= 4; 854 else 855 ext >>= 1; 856 ext &= 0x03; 857 } 858 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 859 } else if (extres) { 860 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES2_REG); 861 862 /* Read all msb regs to unlatch them */ 863 t1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_12VIN); 864 t1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_REMOTE1_TEMP); 865 t2 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_REMOTE2_TEMP); 866 t3 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_LOCAL_TEMP); 867 switch (reg) { 868 case DBCOOL_REMOTE1_TEMP: 869 val = t1; 870 ext >>= 2; 871 break; 872 case DBCOOL_LOCAL_TEMP: 873 val = t3; 874 ext >>= 4; 875 break; 876 case DBCOOL_REMOTE2_TEMP: 877 val = t2; 878 ext >>= 6; 879 break; 880 default: 881 val = 0; 882 break; 883 } 884 ext &= 0x03; 885 } 886 else 887 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 888 889 /* Check for invalid temp values */ 890 if ((sc->sc_temp_offset == 0 && val == 0x80) || 891 (sc->sc_temp_offset != 0 && val == 0)) 892 return 0; 893 894 /* If using offset mode, adjust, else treat as signed */ 895 if (sc->sc_temp_offset) { 896 temp = val; 897 temp -= sc->sc_temp_offset; 898 } else 899 temp = (int8_t)val; 900 901 /* Convert degC to uK and include extended precision bits */ 902 temp *= 1000000; 903 temp += 250000 * (int)ext; 904 temp += 273150000U; 905 906 return temp; 907 } 908 909 static int 910 dbcool_read_rpm(struct dbcool_softc *sc, uint8_t reg) 911 { 912 int rpm; 913 uint8_t rpm_lo, rpm_hi; 914 915 rpm_lo = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 916 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 917 rpm_hi = (rpm_lo == 0xff)?0xff:0x0; 918 else 919 rpm_hi = sc->sc_dc.dc_readreg(&sc->sc_dc, reg + 1); 920 921 rpm = (rpm_hi << 8) | rpm_lo; 922 if (rpm == 0xffff) 923 return 0; /* 0xffff indicates stalled/failed fan */ 924 925 /* don't divide by zero */ 926 return (rpm == 0)? 0 : (sc->sc_dc.dc_chip->rpm_dividend / rpm); 927 } 928 929 /* Provide chip's supply voltage, in microvolts */ 930 static int 931 dbcool_supply_voltage(struct dbcool_softc *sc) 932 { 933 if (sc->sc_dc.dc_chip->flags & DBCFLAG_MULTI_VCC) { 934 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_CONFIG1_REG) & DBCOOL_CFG1_Vcc) 935 return 5002500; 936 else 937 return 3300000; 938 } else if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) { 939 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADT7466_CONFIG1) & 940 DBCOOL_ADT7466_CFG1_Vcc) 941 return 5000000; 942 else 943 return 3300000; 944 } else 945 return 3300000; 946 } 947 948 /* 949 * Nominal voltages are calculated in microvolts 950 */ 951 static int 952 dbcool_read_volt(struct dbcool_softc *sc, uint8_t reg, int nom_idx, bool extres) 953 { 954 uint8_t ext = 0, v1, v2, v3, v4, val; 955 int64_t ret; 956 int64_t nom; 957 958 nom = nominal_voltages[nom_idx]; 959 if (nom < 0) 960 nom = sc->sc_supply_voltage; 961 962 /* ADT7466 voltages are in strange locations with only 8-bits */ 963 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) 964 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 965 else 966 /* 967 * It's a "normal" dbCool chip - check for regs that 968 * share extended resolution bits since we have to 969 * read all the MSB registers to unlatch them. 970 */ 971 if (!extres) 972 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 973 else if (reg == DBCOOL_12VIN) { 974 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES2_REG) && 0x03; 975 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 976 (void)dbcool_read_temp(sc, DBCOOL_LOCAL_TEMP, true); 977 } else if (reg == DBCOOL_VTT || reg == DBCOOL_IMON) { 978 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES_VTT_IMON); 979 v1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_IMON); 980 v2 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VTT); 981 if (reg == DBCOOL_IMON) { 982 val = v1; 983 ext >>= 6; 984 } else 985 val = v2; 986 ext >>= 4; 987 ext &= 0x0f; 988 } else { 989 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES1_REG); 990 v1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_25VIN); 991 v2 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VCCP); 992 v3 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VCC); 993 v4 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_5VIN); 994 995 switch (reg) { 996 case DBCOOL_25VIN: 997 val = v1; 998 break; 999 case DBCOOL_VCCP: 1000 val = v2; 1001 ext >>= 2; 1002 break; 1003 case DBCOOL_VCC: 1004 val = v3; 1005 ext >>= 4; 1006 break; 1007 case DBCOOL_5VIN: 1008 val = v4; 1009 ext >>= 6; 1010 break; 1011 default: 1012 val = nom = 0; 1013 } 1014 ext &= 0x03; 1015 } 1016 1017 /* 1018 * Scale the nominal value by the 10-bit fraction 1019 * 1020 * Returned value is in microvolts. 1021 */ 1022 ret = val; 1023 ret <<= 2; 1024 ret |= ext; 1025 ret = (ret * nom) / 0x300; 1026 1027 return ret; 1028 } 1029 1030 SYSCTL_SETUP(sysctl_dbcoolsetup, "sysctl dBCool subtree setup") 1031 { 1032 sysctl_createv(NULL, 0, NULL, NULL, 1033 CTLFLAG_PERMANENT, 1034 CTLTYPE_NODE, "hw", NULL, 1035 NULL, 0, NULL, 0, 1036 CTL_HW, CTL_EOL); 1037 } 1038 1039 static int 1040 sysctl_dbcool_temp(SYSCTLFN_ARGS) 1041 { 1042 struct sysctlnode node; 1043 struct dbcool_softc *sc; 1044 int reg, error; 1045 uint8_t chipreg; 1046 uint8_t newreg; 1047 1048 node = *rnode; 1049 sc = (struct dbcool_softc *)node.sysctl_data; 1050 chipreg = node.sysctl_num & 0xff; 1051 1052 if (sc->sc_temp_offset) { 1053 reg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1054 reg -= sc->sc_temp_offset; 1055 } else 1056 reg = (int8_t)sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1057 1058 node.sysctl_data = ® 1059 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1060 1061 if (error || newp == NULL) 1062 return error; 1063 1064 /* We were asked to update the value - sanity check before writing */ 1065 if (*(int *)node.sysctl_data < -64 || 1066 *(int *)node.sysctl_data > 127 + sc->sc_temp_offset) 1067 return EINVAL; 1068 1069 newreg = *(int *)node.sysctl_data; 1070 newreg += sc->sc_temp_offset; 1071 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1072 return 0; 1073 } 1074 1075 static int 1076 sysctl_adm1030_temp(SYSCTLFN_ARGS) 1077 { 1078 struct sysctlnode node; 1079 struct dbcool_softc *sc; 1080 int reg, error; 1081 uint8_t chipreg, oldreg, newreg; 1082 1083 node = *rnode; 1084 sc = (struct dbcool_softc *)node.sysctl_data; 1085 chipreg = node.sysctl_num & 0xff; 1086 1087 oldreg = (int8_t)sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1088 reg = (oldreg >> 1) & ~0x03; 1089 1090 node.sysctl_data = ® 1091 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1092 1093 if (error || newp == NULL) 1094 return error; 1095 1096 /* We were asked to update the value - sanity check before writing */ 1097 if (*(int *)node.sysctl_data < 0 || *(int *)node.sysctl_data > 127) 1098 return EINVAL; 1099 1100 newreg = *(int *)node.sysctl_data; 1101 newreg &= ~0x03; 1102 newreg <<= 1; 1103 newreg |= (oldreg & 0x07); 1104 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1105 return 0; 1106 } 1107 1108 static int 1109 sysctl_adm1030_trange(SYSCTLFN_ARGS) 1110 { 1111 struct sysctlnode node; 1112 struct dbcool_softc *sc; 1113 int reg, error, newval; 1114 uint8_t chipreg, oldreg, newreg; 1115 1116 node = *rnode; 1117 sc = (struct dbcool_softc *)node.sysctl_data; 1118 chipreg = node.sysctl_num & 0xff; 1119 1120 oldreg = (int8_t)sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1121 reg = oldreg & 0x07; 1122 1123 node.sysctl_data = ® 1124 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1125 1126 if (error || newp == NULL) 1127 return error; 1128 1129 /* We were asked to update the value - sanity check before writing */ 1130 newval = *(int *)node.sysctl_data; 1131 1132 if (newval == 5) 1133 newreg = 0; 1134 else if (newval == 10) 1135 newreg = 1; 1136 else if (newval == 20) 1137 newreg = 2; 1138 else if (newval == 40) 1139 newreg = 3; 1140 else if (newval == 80) 1141 newreg = 4; 1142 else 1143 return EINVAL; 1144 1145 newreg |= (oldreg & ~0x07); 1146 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1147 return 0; 1148 } 1149 1150 static int 1151 sysctl_dbcool_duty(SYSCTLFN_ARGS) 1152 { 1153 struct sysctlnode node; 1154 struct dbcool_softc *sc; 1155 int reg, error; 1156 uint8_t chipreg, oldreg, newreg; 1157 1158 node = *rnode; 1159 sc = (struct dbcool_softc *)node.sysctl_data; 1160 chipreg = node.sysctl_num & 0xff; 1161 1162 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1163 reg = (uint32_t)oldreg; 1164 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 1165 reg = ((reg & 0x0f) * 100) / 15; 1166 else 1167 reg = (reg * 100) / 255; 1168 node.sysctl_data = ® 1169 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1170 1171 if (error || newp == NULL) 1172 return error; 1173 1174 /* We were asked to update the value - sanity check before writing */ 1175 if (*(int *)node.sysctl_data < 0 || *(int *)node.sysctl_data > 100) 1176 return EINVAL; 1177 1178 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) { 1179 newreg = *(uint8_t *)(node.sysctl_data) * 15 / 100; 1180 newreg |= oldreg & 0xf0; 1181 } else 1182 newreg = *(uint8_t *)(node.sysctl_data) * 255 / 100; 1183 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1184 return 0; 1185 } 1186 1187 static int 1188 sysctl_dbcool_behavior(SYSCTLFN_ARGS) 1189 { 1190 struct sysctlnode node; 1191 struct dbcool_softc *sc; 1192 int i, reg, error; 1193 uint8_t chipreg, oldreg, newreg; 1194 1195 node = *rnode; 1196 sc = (struct dbcool_softc *)node.sysctl_data; 1197 chipreg = node.sysctl_num & 0xff; 1198 1199 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1200 1201 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) { 1202 if ((sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_CFG2) & 1) == 0) 1203 reg = 4; 1204 else if ((oldreg & 0x80) == 0) 1205 reg = 7; 1206 else if ((oldreg & 0x60) == 0) 1207 reg = 4; 1208 else 1209 reg = 6; 1210 } else 1211 reg = (oldreg >> 5) & 0x07; 1212 1213 strlcpy(dbcool_cur_behav, behavior[reg], sizeof(dbcool_cur_behav)); 1214 node.sysctl_data = dbcool_cur_behav; 1215 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1216 1217 if (error || newp == NULL) 1218 return error; 1219 1220 /* We were asked to update the value - convert string to value */ 1221 newreg = __arraycount(behavior); 1222 for (i = 0; i < __arraycount(behavior); i++) 1223 if (strcmp(node.sysctl_data, behavior[i]) == 0) 1224 break; 1225 if (i >= __arraycount(behavior)) 1226 return EINVAL; 1227 1228 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) { 1229 /* 1230 * ADM1030 splits fan controller behavior across two 1231 * registers. We also do not support Auto-Filter mode 1232 * nor do we support Manual-RPM-feedback. 1233 */ 1234 if (newreg == 4) { 1235 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_CFG2); 1236 oldreg &= ~0x01; 1237 sc->sc_dc.dc_writereg(&sc->sc_dc, DBCOOL_ADM1030_CFG2, oldreg); 1238 } else { 1239 if (newreg == 0) 1240 newreg = 4; 1241 else if (newreg == 6) 1242 newreg = 7; 1243 else if (newreg == 7) 1244 newreg = 0; 1245 else 1246 return EINVAL; 1247 newreg <<= 5; 1248 newreg |= (oldreg & 0x1f); 1249 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1250 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_CFG2) | 1; 1251 sc->sc_dc.dc_writereg(&sc->sc_dc, DBCOOL_ADM1030_CFG2, oldreg); 1252 } 1253 } else { 1254 newreg = (sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg) & 0x1f) | (i << 5); 1255 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1256 } 1257 return 0; 1258 } 1259 1260 static int 1261 sysctl_dbcool_slope(SYSCTLFN_ARGS) 1262 { 1263 struct sysctlnode node; 1264 struct dbcool_softc *sc; 1265 int reg, error; 1266 uint8_t chipreg; 1267 uint8_t newreg; 1268 1269 node = *rnode; 1270 sc = (struct dbcool_softc *)node.sysctl_data; 1271 chipreg = node.sysctl_num & 0xff; 1272 1273 reg = (sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg) >> 4) & 0x0f; 1274 node.sysctl_data = ® 1275 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1276 1277 if (error || newp == NULL) 1278 return error; 1279 1280 /* We were asked to update the value - sanity check before writing */ 1281 if (*(int *)node.sysctl_data < 0 || *(int *)node.sysctl_data > 0x0f) 1282 return EINVAL; 1283 1284 newreg = (sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg) & 0x0f) | 1285 (*(int *)node.sysctl_data << 4); 1286 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1287 return 0; 1288 } 1289 1290 static int 1291 sysctl_dbcool_thyst(SYSCTLFN_ARGS) 1292 { 1293 struct sysctlnode node; 1294 struct dbcool_softc *sc; 1295 int reg, error; 1296 uint8_t chipreg; 1297 uint8_t newreg, newhyst; 1298 1299 node = *rnode; 1300 sc = (struct dbcool_softc *)node.sysctl_data; 1301 chipreg = node.sysctl_num & 0x7f; 1302 1303 /* retrieve 4-bit value */ 1304 newreg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1305 if ((node.sysctl_num & 0x80) == 0) 1306 reg = newreg >> 4; 1307 else 1308 reg = newreg; 1309 reg = reg & 0x0f; 1310 1311 node.sysctl_data = ® 1312 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1313 1314 if (error || newp == NULL) 1315 return error; 1316 1317 /* We were asked to update the value - sanity check before writing */ 1318 newhyst = *(int *)node.sysctl_data; 1319 if (newhyst > 0x0f) 1320 return EINVAL; 1321 1322 /* Insert new value into field and update register */ 1323 if ((node.sysctl_num & 0x80) == 0) { 1324 newreg &= 0x0f; 1325 newreg |= (newhyst << 4); 1326 } else { 1327 newreg &= 0xf0; 1328 newreg |= newhyst; 1329 } 1330 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1331 return 0; 1332 } 1333 1334 #ifdef DBCOOL_DEBUG 1335 1336 /* 1337 * These routines can be used for debugging. reg_select is used to 1338 * select any arbitrary register in the device. reg_access is used 1339 * to read (and optionally update) the selected register. 1340 * 1341 * No attempt is made to validate the data passed. If you use these 1342 * routines, you are assumed to know what you're doing! 1343 * 1344 * Caveat user 1345 */ 1346 static int 1347 sysctl_dbcool_reg_select(SYSCTLFN_ARGS) 1348 { 1349 struct sysctlnode node; 1350 struct dbcool_softc *sc; 1351 int reg, error; 1352 1353 node = *rnode; 1354 sc = (struct dbcool_softc *)node.sysctl_data; 1355 1356 reg = sc->sc_user_reg; 1357 node.sysctl_data = ® 1358 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1359 1360 if (error || newp == NULL) 1361 return error; 1362 1363 sc->sc_user_reg = *(int *)node.sysctl_data; 1364 return 0; 1365 } 1366 1367 static int 1368 sysctl_dbcool_reg_access(SYSCTLFN_ARGS) 1369 { 1370 struct sysctlnode node; 1371 struct dbcool_softc *sc; 1372 int reg, error; 1373 uint8_t chipreg; 1374 uint8_t newreg; 1375 1376 node = *rnode; 1377 sc = (struct dbcool_softc *)node.sysctl_data; 1378 chipreg = sc->sc_user_reg; 1379 1380 reg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1381 node.sysctl_data = ® 1382 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1383 1384 if (error || newp == NULL) 1385 return error; 1386 1387 newreg = *(int *)node.sysctl_data; 1388 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1389 return 0; 1390 } 1391 #endif /* DBCOOL_DEBUG */ 1392 1393 /* 1394 * Encode an index number and register number for use as a sysctl_num 1395 * so we can select the correct device register later. 1396 */ 1397 #define DBC_PWM_SYSCTL(seq, reg) ((seq << 8) | reg) 1398 1399 void 1400 dbcool_setup(device_t self) 1401 { 1402 struct dbcool_softc *sc = device_private(self); 1403 const struct sysctlnode *me = NULL; 1404 #ifdef DBCOOL_DEBUG 1405 struct sysctlnode *node = NULL; 1406 #endif 1407 uint8_t cfg_val, cfg_reg; 1408 int ret, error; 1409 1410 /* 1411 * Some chips are capable of reporting an extended temperature range 1412 * by default. On these models, config register 5 bit 0 can be set 1413 * to 1 for compatability with other chips that report 2s complement. 1414 */ 1415 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) { 1416 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADT7466_CONFIG1) & 0x80) 1417 sc->sc_temp_offset = 64; 1418 else 1419 sc->sc_temp_offset = 0; 1420 } else if (sc->sc_dc.dc_chip->flags & DBCFLAG_TEMPOFFSET) { 1421 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_CONFIG5_REG) & 1422 DBCOOL_CFG5_TWOSCOMP) 1423 sc->sc_temp_offset = 0; 1424 else 1425 sc->sc_temp_offset = 64; 1426 } else 1427 sc->sc_temp_offset = 0; 1428 1429 /* Determine Vcc for this chip */ 1430 sc->sc_supply_voltage = dbcool_supply_voltage(sc); 1431 1432 ret = sysctl_createv(NULL, 0, NULL, &me, 1433 CTLFLAG_READWRITE, 1434 CTLTYPE_NODE, device_xname(self), NULL, 1435 NULL, 0, NULL, 0, 1436 CTL_HW, CTL_CREATE, CTL_EOL); 1437 if (ret == 0) 1438 sc->sc_root_sysctl_num = me->sysctl_num; 1439 else 1440 sc->sc_root_sysctl_num = 0; 1441 1442 aprint_debug_dev(self, 1443 "Supply voltage %"PRId64".%06"PRId64"V, %s temp range\n", 1444 sc->sc_supply_voltage / 1000000, 1445 sc->sc_supply_voltage % 1000000, 1446 sc->sc_temp_offset ? "extended" : "normal"); 1447 1448 /* Create the sensors for this device */ 1449 sc->sc_sme = sysmon_envsys_create(); 1450 if (dbcool_setup_sensors(sc)) 1451 goto out; 1452 1453 if (sc->sc_root_sysctl_num != 0) { 1454 /* If supported, create sysctl tree for fan PWM controllers */ 1455 if (sc->sc_dc.dc_chip->power != NULL) 1456 dbcool_setup_controllers(sc); 1457 1458 #ifdef DBCOOL_DEBUG 1459 ret = sysctl_createv(NULL, 0, NULL, 1460 (const struct sysctlnode **)&node, 1461 CTLFLAG_READWRITE, CTLTYPE_INT, "reg_select", NULL, 1462 sysctl_dbcool_reg_select, 1463 0, sc, sizeof(int), 1464 CTL_HW, me->sysctl_num, CTL_CREATE, CTL_EOL); 1465 if (node != NULL) 1466 node->sysctl_data = sc; 1467 1468 ret = sysctl_createv(NULL, 0, NULL, 1469 (const struct sysctlnode **)&node, 1470 CTLFLAG_READWRITE, CTLTYPE_INT, "reg_access", NULL, 1471 sysctl_dbcool_reg_access, 1472 0, sc, sizeof(int), 1473 CTL_HW, me->sysctl_num, CTL_CREATE, CTL_EOL); 1474 if (node != NULL) 1475 node->sysctl_data = sc; 1476 #endif /* DBCOOL_DEBUG */ 1477 } 1478 1479 /* 1480 * Read and rewrite config register to activate device 1481 */ 1482 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 1483 cfg_reg = DBCOOL_ADM1030_CFG1; 1484 else if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) 1485 cfg_reg = DBCOOL_ADT7466_CONFIG1; 1486 else 1487 cfg_reg = DBCOOL_CONFIG1_REG; 1488 cfg_val = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_CONFIG1_REG); 1489 if ((cfg_val & DBCOOL_CFG1_START) == 0) { 1490 cfg_val |= DBCOOL_CFG1_START; 1491 sc->sc_dc.dc_writereg(&sc->sc_dc, cfg_reg, cfg_val); 1492 } 1493 if (dbcool_islocked(sc)) 1494 aprint_normal_dev(self, "configuration locked\n"); 1495 1496 sc->sc_sme->sme_name = device_xname(self); 1497 sc->sc_sme->sme_cookie = sc; 1498 sc->sc_sme->sme_refresh = dbcool_refresh; 1499 sc->sc_sme->sme_set_limits = dbcool_set_limits; 1500 sc->sc_sme->sme_get_limits = dbcool_get_limits; 1501 1502 if ((error = sysmon_envsys_register(sc->sc_sme)) != 0) { 1503 aprint_error_dev(self, 1504 "unable to register with sysmon (%d)\n", error); 1505 goto out; 1506 } 1507 1508 return; 1509 1510 out: 1511 sysmon_envsys_destroy(sc->sc_sme); 1512 } 1513 1514 static int 1515 dbcool_setup_sensors(struct dbcool_softc *sc) 1516 { 1517 int i; 1518 int error = 0; 1519 uint8_t vid_reg, vid_val; 1520 struct chip_id *chip = sc->sc_dc.dc_chip; 1521 1522 for (i=0; chip->table[i].type != DBC_EOF; i++) { 1523 if (i < DBCOOL_MAXSENSORS) 1524 sc->sc_sysctl_num[i] = -1; 1525 else if (chip->table[i].type != DBC_CTL) { 1526 aprint_normal_dev(sc->sc_dev, "chip table too big!\n"); 1527 break; 1528 } 1529 switch (chip->table[i].type) { 1530 case DBC_TEMP: 1531 sc->sc_sensor[i].units = ENVSYS_STEMP; 1532 sc->sc_sensor[i].flags |= ENVSYS_FMONLIMITS; 1533 error = dbcool_attach_sensor(sc, i); 1534 break; 1535 case DBC_VOLT: 1536 /* 1537 * If 12V-In pin has been reconfigured as 6th bit 1538 * of VID code, don't create a 12V-In sensor 1539 */ 1540 if ((chip->flags & DBCFLAG_HAS_VID_SEL) && 1541 (chip->table[i].reg.val_reg == DBCOOL_12VIN) && 1542 (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VID_REG) & 1543 0x80)) 1544 break; 1545 1546 sc->sc_sensor[i].units = ENVSYS_SVOLTS_DC; 1547 sc->sc_sensor[i].flags |= ENVSYS_FMONLIMITS; 1548 error = dbcool_attach_sensor(sc, i); 1549 break; 1550 case DBC_FAN: 1551 sc->sc_sensor[i].units = ENVSYS_SFANRPM; 1552 sc->sc_sensor[i].flags |= ENVSYS_FMONLIMITS; 1553 error = dbcool_attach_sensor(sc, i); 1554 break; 1555 case DBC_VID: 1556 sc->sc_sensor[i].units = ENVSYS_INTEGER; 1557 sc->sc_sensor[i].flags |= ENVSYS_FMONNOTSUPP; 1558 1559 /* retrieve 5- or 6-bit value */ 1560 vid_reg = chip->table[i].reg.val_reg; 1561 vid_val = sc->sc_dc.dc_readreg(&sc->sc_dc, vid_reg); 1562 if (chip->flags & DBCFLAG_HAS_VID_SEL) 1563 vid_val &= 0x3f; 1564 else 1565 vid_val &= 0x1f; 1566 sc->sc_sensor[i].value_cur = vid_val; 1567 1568 error = dbcool_attach_sensor(sc, i); 1569 break; 1570 case DBC_CTL: 1571 error = dbcool_attach_temp_control(sc, i, chip); 1572 if (error) { 1573 aprint_error_dev(sc->sc_dev, 1574 "attach index %d failed %d\n", 1575 i, error); 1576 error = 0; 1577 } 1578 break; 1579 default: 1580 aprint_error_dev(sc->sc_dev, 1581 "sensor_table index %d has bad type %d\n", 1582 i, chip->table[i].type); 1583 break; 1584 } 1585 if (error) 1586 break; 1587 } 1588 return error; 1589 } 1590 1591 static int 1592 dbcool_attach_sensor(struct dbcool_softc *sc, int idx) 1593 { 1594 int name_index; 1595 int error = 0; 1596 1597 name_index = sc->sc_dc.dc_chip->table[idx].name_index; 1598 strlcpy(sc->sc_sensor[idx].desc, dbc_sensor_names[name_index], 1599 sizeof(sc->sc_sensor[idx].desc)); 1600 sc->sc_regs[idx] = &sc->sc_dc.dc_chip->table[idx].reg; 1601 sc->sc_nom_volt[idx] = sc->sc_dc.dc_chip->table[idx].nom_volt_index; 1602 1603 error = sysmon_envsys_sensor_attach(sc->sc_sme, &sc->sc_sensor[idx]); 1604 return error; 1605 } 1606 1607 static int 1608 dbcool_attach_temp_control(struct dbcool_softc *sc, int idx, 1609 struct chip_id *chip) 1610 { 1611 const struct sysctlnode *me2 = NULL; 1612 struct sysctlnode *node = NULL; 1613 int j, ret, sysctl_index, rw_flag; 1614 uint8_t sysctl_reg; 1615 char name[SYSCTL_NAMELEN]; 1616 1617 /* Search for the corresponding temp sensor */ 1618 for (j = 0; j < idx; j++) { 1619 if (j >= DBCOOL_MAXSENSORS || chip->table[j].type != DBC_TEMP) 1620 continue; 1621 if (chip->table[j].name_index == chip->table[idx].name_index) 1622 break; 1623 } 1624 if (j >= idx) /* Temp sensor not found */ 1625 return ENOENT; 1626 1627 /* create sysctl node for the sensor if not one already there */ 1628 if (sc->sc_sysctl_num[j] == -1) { 1629 ret = sysctl_createv(NULL, 0, NULL, &me2, CTLFLAG_READWRITE, 1630 CTLTYPE_NODE, sc->sc_sensor[j].desc, NULL, 1631 NULL, 0, NULL, 0, 1632 CTL_HW, sc->sc_root_sysctl_num, CTL_CREATE, 1633 CTL_EOL); 1634 if (me2 != NULL) 1635 sc->sc_sysctl_num[j] = me2->sysctl_num; 1636 else 1637 return ret; 1638 } 1639 /* add sysctl leaf node for this control variable */ 1640 sysctl_index = chip->table[idx].sysctl_index; 1641 sysctl_reg = chip->table[idx].reg.val_reg; 1642 strlcpy(name, dbc_sysctl_table[sysctl_index].name, sizeof(name)); 1643 if (dbc_sysctl_table[sysctl_index].lockable && dbcool_islocked(sc)) 1644 rw_flag = CTLFLAG_READONLY | CTLFLAG_OWNDESC; 1645 else 1646 rw_flag = CTLFLAG_READWRITE | CTLFLAG_OWNDESC; 1647 ret = sysctl_createv(NULL, 0, NULL, 1648 (const struct sysctlnode **)&node, rw_flag, 1649 CTLTYPE_INT, name, 1650 SYSCTL_DESCR(dbc_sysctl_table[sysctl_index].desc), 1651 dbc_sysctl_table[sysctl_index].helper, 1652 0, sc, sizeof(int), 1653 CTL_HW, sc->sc_root_sysctl_num, 1654 sc->sc_sysctl_num[j], 1655 DBC_PWM_SYSCTL(idx, sysctl_reg), CTL_EOL); 1656 if (node != NULL) 1657 node->sysctl_data = sc; 1658 1659 return ret; 1660 } 1661 1662 static void 1663 dbcool_setup_controllers(struct dbcool_softc *sc) 1664 { 1665 int i, j, ret, rw_flag; 1666 uint8_t sysctl_reg; 1667 struct chip_id *chip = sc->sc_dc.dc_chip; 1668 const struct sysctlnode *me2 = NULL; 1669 struct sysctlnode *node = NULL; 1670 char name[SYSCTL_NAMELEN]; 1671 1672 for (i = 0; chip->power[i].desc != NULL; i++) { 1673 snprintf(name, sizeof(name), "fan_ctl_%d", i); 1674 ret = sysctl_createv(NULL, 0, NULL, &me2, 1675 CTLFLAG_READWRITE | CTLFLAG_OWNDESC, 1676 CTLTYPE_NODE, name, NULL, 1677 NULL, 0, NULL, 0, 1678 CTL_HW, sc->sc_root_sysctl_num, CTL_CREATE, CTL_EOL); 1679 1680 for (j = DBC_PWM_BEHAVIOR; j < DBC_PWM_LAST_PARAM; j++) { 1681 if (j == DBC_PWM_MAX_DUTY && 1682 (chip->flags & DBCFLAG_HAS_MAXDUTY) == 0) 1683 continue; 1684 sysctl_reg = chip->power[i].power_regs[j]; 1685 if (sysctl_reg == DBCOOL_NO_REG) 1686 continue; 1687 strlcpy(name, dbc_sysctl_table[j].name, sizeof(name)); 1688 if (dbc_sysctl_table[j].lockable && dbcool_islocked(sc)) 1689 rw_flag = CTLFLAG_READONLY | CTLFLAG_OWNDESC; 1690 else 1691 rw_flag = CTLFLAG_READWRITE | CTLFLAG_OWNDESC; 1692 ret = sysctl_createv(NULL, 0, NULL, 1693 (const struct sysctlnode **)&node, rw_flag, 1694 (j == DBC_PWM_BEHAVIOR)? 1695 CTLTYPE_STRING:CTLTYPE_INT, 1696 name, 1697 SYSCTL_DESCR(dbc_sysctl_table[j].desc), 1698 dbc_sysctl_table[j].helper, 1699 0, sc, 1700 ( j == DBC_PWM_BEHAVIOR)? 1701 sizeof(dbcool_cur_behav): sizeof(int), 1702 CTL_HW, sc->sc_root_sysctl_num, me2->sysctl_num, 1703 DBC_PWM_SYSCTL(j, sysctl_reg), CTL_EOL); 1704 if (node != NULL) 1705 node->sysctl_data = sc; 1706 } 1707 } 1708 } 1709 1710 static void 1711 dbcool_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 1712 { 1713 struct dbcool_softc *sc=sme->sme_cookie; 1714 int i, nom_volt_idx, cur; 1715 struct reg_list *reg; 1716 1717 i = edata->sensor; 1718 reg = sc->sc_regs[i]; 1719 1720 edata->state = ENVSYS_SVALID; 1721 switch (edata->units) 1722 { 1723 case ENVSYS_STEMP: 1724 cur = dbcool_read_temp(sc, reg->val_reg, true); 1725 break; 1726 case ENVSYS_SVOLTS_DC: 1727 nom_volt_idx = sc->sc_nom_volt[i]; 1728 cur = dbcool_read_volt(sc, reg->val_reg, nom_volt_idx, 1729 true); 1730 break; 1731 case ENVSYS_SFANRPM: 1732 cur = dbcool_read_rpm(sc, reg->val_reg); 1733 break; 1734 case ENVSYS_INTEGER: 1735 return; 1736 default: 1737 edata->state = ENVSYS_SINVALID; 1738 return; 1739 } 1740 1741 if (cur == 0 && (edata->units != ENVSYS_SFANRPM)) 1742 edata->state = ENVSYS_SINVALID; 1743 1744 /* 1745 * If fan is "stalled" but has no low limit, treat 1746 * it as though the fan is not installed. 1747 */ 1748 else if (edata->units == ENVSYS_SFANRPM && cur == 0 && 1749 !(edata->upropset & (PROP_CRITMIN | PROP_WARNMIN))) 1750 edata->state = ENVSYS_SINVALID; 1751 1752 edata->value_cur = cur; 1753 } 1754 1755 int 1756 dbcool_chip_ident(struct dbcool_chipset *dc) 1757 { 1758 /* verify this is a supported dbCool chip */ 1759 uint8_t c_id, d_id, r_id; 1760 int i; 1761 1762 c_id = dc->dc_readreg(dc, DBCOOL_COMPANYID_REG); 1763 d_id = dc->dc_readreg(dc, DBCOOL_DEVICEID_REG); 1764 r_id = dc->dc_readreg(dc, DBCOOL_REVISION_REG); 1765 1766 for (i = 0; chip_table[i].company != 0; i++) 1767 if ((c_id == chip_table[i].company) && 1768 (d_id == chip_table[i].device || 1769 chip_table[i].device == 0xff) && 1770 (r_id == chip_table[i].rev || 1771 chip_table[i].rev == 0xff)) { 1772 dc->dc_chip = &chip_table[i]; 1773 return i; 1774 } 1775 1776 aprint_verbose("dbcool_chip_ident: addr 0x%02x c_id 0x%02x d_id 0x%02x" 1777 " r_id 0x%02x: No match.\n", dc->dc_addr, c_id, d_id, 1778 r_id); 1779 1780 return -1; 1781 } 1782 1783 /* 1784 * Retrieve sensor limits from the chip registers 1785 */ 1786 static void 1787 dbcool_get_limits(struct sysmon_envsys *sme, envsys_data_t *edata, 1788 sysmon_envsys_lim_t *limits, uint32_t *props) 1789 { 1790 int index = edata->sensor; 1791 struct dbcool_softc *sc = sme->sme_cookie; 1792 1793 *props &= ~(PROP_CRITMIN | PROP_CRITMAX); 1794 switch (edata->units) { 1795 case ENVSYS_STEMP: 1796 dbcool_get_temp_limits(sc, index, limits, props); 1797 break; 1798 case ENVSYS_SVOLTS_DC: 1799 dbcool_get_volt_limits(sc, index, limits, props); 1800 break; 1801 case ENVSYS_SFANRPM: 1802 dbcool_get_fan_limits(sc, index, limits, props); 1803 1804 /* FALLTHROUGH */ 1805 default: 1806 break; 1807 } 1808 *props &= ~PROP_DRIVER_LIMITS; 1809 1810 /* If both limits provided, make sure they're sane */ 1811 if ((*props & PROP_CRITMIN) && 1812 (*props & PROP_CRITMAX) && 1813 (limits->sel_critmin >= limits->sel_critmax)) 1814 *props &= ~(PROP_CRITMIN | PROP_CRITMAX); 1815 1816 /* 1817 * If this is the first time through, save these values 1818 * in case user overrides them and then requests a reset. 1819 */ 1820 if (sc->sc_defprops[index] == 0) { 1821 sc->sc_defprops[index] = *props | PROP_DRIVER_LIMITS; 1822 sc->sc_deflims[index] = *limits; 1823 } 1824 } 1825 1826 static void 1827 dbcool_get_temp_limits(struct dbcool_softc *sc, int idx, 1828 sysmon_envsys_lim_t *lims, uint32_t *props) 1829 { 1830 struct reg_list *reg = sc->sc_regs[idx]; 1831 uint8_t lo_lim, hi_lim; 1832 1833 lo_lim = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->lo_lim_reg); 1834 hi_lim = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->hi_lim_reg); 1835 1836 if (sc->sc_temp_offset) { 1837 if (lo_lim > 0x01) { 1838 lims->sel_critmin = lo_lim - sc->sc_temp_offset; 1839 *props |= PROP_CRITMIN; 1840 } 1841 if (hi_lim != 0xff) { 1842 lims->sel_critmax = hi_lim - sc->sc_temp_offset; 1843 *props |= PROP_CRITMAX; 1844 } 1845 } else { 1846 if (lo_lim != 0x80 && lo_lim != 0x81) { 1847 lims->sel_critmin = (int8_t)lo_lim; 1848 *props |= PROP_CRITMIN; 1849 } 1850 1851 if (hi_lim != 0x7f) { 1852 lims->sel_critmax = (int8_t)hi_lim; 1853 *props |= PROP_CRITMAX; 1854 } 1855 } 1856 1857 /* Convert temp limits to microKelvin */ 1858 lims->sel_critmin *= 1000000; 1859 lims->sel_critmin += 273150000; 1860 lims->sel_critmax *= 1000000; 1861 lims->sel_critmax += 273150000; 1862 } 1863 1864 static void 1865 dbcool_get_volt_limits(struct dbcool_softc *sc, int idx, 1866 sysmon_envsys_lim_t *lims, uint32_t *props) 1867 { 1868 struct reg_list *reg = sc->sc_regs[idx]; 1869 int64_t limit; 1870 int nom; 1871 1872 nom = nominal_voltages[sc->sc_dc.dc_chip->table[idx].nom_volt_index]; 1873 if (nom < 0) 1874 nom = dbcool_supply_voltage(sc); 1875 nom *= 1000000; /* scale for microvolts */ 1876 1877 limit = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->lo_lim_reg); 1878 if (limit != 0x00 && limit != 0xff) { 1879 limit *= nom; 1880 limit /= 0xc0; 1881 lims->sel_critmin = limit; 1882 *props |= PROP_CRITMIN; 1883 } 1884 limit = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->hi_lim_reg); 1885 if (limit != 0x00 && limit != 0xff) { 1886 limit *= nom; 1887 limit /= 0xc0; 1888 lims->sel_critmax = limit; 1889 *props |= PROP_CRITMAX; 1890 } 1891 } 1892 1893 static void 1894 dbcool_get_fan_limits(struct dbcool_softc *sc, int idx, 1895 sysmon_envsys_lim_t *lims, uint32_t *props) 1896 { 1897 struct reg_list *reg = sc->sc_regs[idx]; 1898 int32_t limit; 1899 1900 limit = dbcool_read_rpm(sc, reg->lo_lim_reg); 1901 if (limit) { 1902 lims->sel_critmin = limit; 1903 *props |= PROP_CRITMIN; 1904 } 1905 } 1906 1907 /* 1908 * Update sensor limits in the chip registers 1909 */ 1910 static void 1911 dbcool_set_limits(struct sysmon_envsys *sme, envsys_data_t *edata, 1912 sysmon_envsys_lim_t *limits, uint32_t *props) 1913 { 1914 int index = edata->sensor; 1915 struct dbcool_softc *sc = sme->sme_cookie; 1916 1917 if (limits == NULL) { 1918 limits = &sc->sc_deflims[index]; 1919 props = &sc->sc_defprops[index]; 1920 } 1921 switch (edata->units) { 1922 case ENVSYS_STEMP: 1923 dbcool_set_temp_limits(sc, index, limits, props); 1924 break; 1925 case ENVSYS_SVOLTS_DC: 1926 dbcool_set_volt_limits(sc, index, limits, props); 1927 break; 1928 case ENVSYS_SFANRPM: 1929 dbcool_set_fan_limits(sc, index, limits, props); 1930 1931 /* FALLTHROUGH */ 1932 default: 1933 break; 1934 } 1935 *props &= ~PROP_DRIVER_LIMITS; 1936 } 1937 1938 static void 1939 dbcool_set_temp_limits(struct dbcool_softc *sc, int idx, 1940 sysmon_envsys_lim_t *lims, uint32_t *props) 1941 { 1942 struct reg_list *reg = sc->sc_regs[idx]; 1943 int32_t limit; 1944 1945 if (*props & PROP_CRITMIN) { 1946 limit = lims->sel_critmin - 273150000; 1947 limit /= 1000000; 1948 if (sc->sc_temp_offset) { 1949 limit += sc->sc_temp_offset; 1950 if (limit < 0) 1951 limit = 0; 1952 else if (limit > 255) 1953 limit = 255; 1954 } else { 1955 if (limit < -127) 1956 limit = -127; 1957 else if (limit > 127) 1958 limit = 127; 1959 } 1960 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, 1961 (uint8_t)limit); 1962 } else if (*props & PROP_DRIVER_LIMITS) { 1963 if (sc->sc_temp_offset) 1964 limit = 0x00; 1965 else 1966 limit = 0x80; 1967 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, 1968 (uint8_t)limit); 1969 } 1970 1971 if (*props & PROP_CRITMAX) { 1972 limit = lims->sel_critmax - 273150000; 1973 limit /= 1000000; 1974 if (sc->sc_temp_offset) { 1975 limit += sc->sc_temp_offset; 1976 if (limit < 0) 1977 limit = 0; 1978 else if (limit > 255) 1979 limit = 255; 1980 } else { 1981 if (limit < -127) 1982 limit = -127; 1983 else if (limit > 127) 1984 limit = 127; 1985 } 1986 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg, 1987 (uint8_t)limit); 1988 } else if (*props & PROP_DRIVER_LIMITS) { 1989 if (sc->sc_temp_offset) 1990 limit = 0xff; 1991 else 1992 limit = 0x7f; 1993 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg, 1994 (uint8_t)limit); 1995 } 1996 } 1997 1998 static void 1999 dbcool_set_volt_limits(struct dbcool_softc *sc, int idx, 2000 sysmon_envsys_lim_t *lims, uint32_t *props) 2001 { 2002 struct reg_list *reg = sc->sc_regs[idx]; 2003 int64_t limit; 2004 int nom; 2005 2006 nom = nominal_voltages[sc->sc_dc.dc_chip->table[idx].nom_volt_index]; 2007 if (nom < 0) 2008 nom = dbcool_supply_voltage(sc); 2009 nom *= 1000000; /* scale for microvolts */ 2010 2011 if (*props & PROP_CRITMIN) { 2012 limit = lims->sel_critmin; 2013 limit *= 0xc0; 2014 limit /= nom; 2015 if (limit > 0xff) 2016 limit = 0xff; 2017 else if (limit < 0) 2018 limit = 0; 2019 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, limit); 2020 } else if (*props & PROP_DRIVER_LIMITS) 2021 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, 0); 2022 2023 if (*props & PROP_CRITMAX) { 2024 limit = lims->sel_critmax; 2025 limit *= 0xc0; 2026 limit /= nom; 2027 if (limit > 0xff) 2028 limit = 0xff; 2029 else if (limit < 0) 2030 limit = 0; 2031 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg, limit); 2032 } else if (*props & PROP_DRIVER_LIMITS) 2033 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg, 0xff); 2034 } 2035 2036 static void 2037 dbcool_set_fan_limits(struct dbcool_softc *sc, int idx, 2038 sysmon_envsys_lim_t *lims, uint32_t *props) 2039 { 2040 struct reg_list *reg = sc->sc_regs[idx]; 2041 int32_t limit, dividend; 2042 2043 if (*props & PROP_CRITMIN) { 2044 limit = lims->sel_critmin; 2045 if (limit == 0) 2046 limit = 0xffff; 2047 else { 2048 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 2049 dividend = 11250 * 60; 2050 else 2051 dividend = 90000 * 60; 2052 limit = limit / dividend; 2053 if (limit > 0xffff) 2054 limit = 0xffff; 2055 } 2056 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, 2057 limit & 0xff); 2058 limit >>= 8; 2059 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg + 1, 2060 limit & 0xff); 2061 } else if (*props & PROP_DRIVER_LIMITS) { 2062 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, 0xff); 2063 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg + 1, 0xff); 2064 } 2065 } 2066
Indexes created Tue Sep 23 22:09:46 GMT 2025