dbcool.c revision 1.32
1 /* $NetBSD: dbcool.c,v 1.32 2011/08/01 22:42:57 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Goyette 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * a driver for the dbCool(tm) family of environmental controllers 34 * 35 * Data sheets for the various supported chips are available at 36 * 37 * http://www.onsemi.com/pub/Collateral/ADM1027-D.PDF 38 * http://www.onsemi.com/pub/Collateral/ADM1030-D.PDF 39 * http://www.onsemi.com/pub/Collateral/ADT7463-D.PDF 40 * http://www.onsemi.com/pub/Collateral/ADT7466.PDF 41 * http://www.onsemi.com/pub/Collateral/ADT7467-D.PDF 42 * http://www.onsemi.com/pub/Collateral/ADT7468-D.PDF 43 * http://www.onsemi.com/pub/Collateral/ADT7473-D.PDF 44 * http://www.onsemi.com/pub/Collateral/ADT7475-D.PDF 45 * http://www.onsemi.com/pub/Collateral/ADT7476-D.PDF 46 * http://www.onsemi.com/pub/Collateral/ADT7490-D.PDF 47 * http://www.smsc.com/media/Downloads_Public/Data_Sheets/6d103s.pdf 48 * 49 * (URLs are correct as of October 5, 2008) 50 */ 51 52 #include <sys/cdefs.h> 53 __KERNEL_RCSID(0, "$NetBSD: dbcool.c,v 1.32 2011/08/01 22:42:57 macallan Exp $"); 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/kernel.h> 58 #include <sys/device.h> 59 #include <sys/malloc.h> 60 #include <sys/sysctl.h> 61 #include <sys/module.h> 62 63 #include <dev/i2c/dbcool_var.h> 64 #include <dev/i2c/dbcool_reg.h> 65 66 /* Config interface */ 67 static int dbcool_match(device_t, cfdata_t, void *); 68 static void dbcool_attach(device_t, device_t, void *); 69 static int dbcool_detach(device_t, int); 70 71 /* Device attributes */ 72 static int dbcool_supply_voltage(struct dbcool_softc *); 73 static bool dbcool_islocked(struct dbcool_softc *); 74 75 /* Sensor read functions */ 76 static void dbcool_refresh(struct sysmon_envsys *, envsys_data_t *); 77 static int dbcool_read_rpm(struct dbcool_softc *, uint8_t); 78 static int dbcool_read_temp(struct dbcool_softc *, uint8_t, bool); 79 static int dbcool_read_volt(struct dbcool_softc *, uint8_t, int, bool); 80 81 /* Sensor get/set limit functions */ 82 static void dbcool_get_limits(struct sysmon_envsys *, envsys_data_t *, 83 sysmon_envsys_lim_t *, uint32_t *); 84 static void dbcool_get_temp_limits(struct dbcool_softc *, int, 85 sysmon_envsys_lim_t *, uint32_t *); 86 static void dbcool_get_volt_limits(struct dbcool_softc *, int, 87 sysmon_envsys_lim_t *, uint32_t *); 88 static void dbcool_get_fan_limits(struct dbcool_softc *, int, 89 sysmon_envsys_lim_t *, uint32_t *); 90 91 static void dbcool_set_limits(struct sysmon_envsys *, envsys_data_t *, 92 sysmon_envsys_lim_t *, uint32_t *); 93 static void dbcool_set_temp_limits(struct dbcool_softc *, int, 94 sysmon_envsys_lim_t *, uint32_t *); 95 static void dbcool_set_volt_limits(struct dbcool_softc *, int, 96 sysmon_envsys_lim_t *, uint32_t *); 97 static void dbcool_set_fan_limits(struct dbcool_softc *, int, 98 sysmon_envsys_lim_t *, uint32_t *); 99 100 /* SYSCTL Helpers */ 101 static int sysctl_dbcool_temp(SYSCTLFN_PROTO); 102 static int sysctl_adm1030_temp(SYSCTLFN_PROTO); 103 static int sysctl_adm1030_trange(SYSCTLFN_PROTO); 104 static int sysctl_dbcool_duty(SYSCTLFN_PROTO); 105 static int sysctl_dbcool_behavior(SYSCTLFN_PROTO); 106 static int sysctl_dbcool_slope(SYSCTLFN_PROTO); 107 static int sysctl_dbcool_thyst(SYSCTLFN_PROTO); 108 109 /* Set-up subroutines */ 110 static void dbcool_setup_controllers(struct dbcool_softc *); 111 static int dbcool_setup_sensors(struct dbcool_softc *); 112 static int dbcool_attach_sensor(struct dbcool_softc *, int); 113 static int dbcool_attach_temp_control(struct dbcool_softc *, int, 114 struct chip_id *); 115 116 #ifdef DBCOOL_DEBUG 117 static int sysctl_dbcool_reg_select(SYSCTLFN_PROTO); 118 static int sysctl_dbcool_reg_access(SYSCTLFN_PROTO); 119 #endif /* DBCOOL_DEBUG */ 120 121 /* 122 * Descriptions for SYSCTL entries 123 */ 124 struct dbc_sysctl_info { 125 const char *name; 126 const char *desc; 127 bool lockable; 128 int (*helper)(SYSCTLFN_PROTO); 129 }; 130 131 static struct dbc_sysctl_info dbc_sysctl_table[] = { 132 /* 133 * The first several entries must remain in the same order as the 134 * corresponding entries in enum dbc_pwm_params 135 */ 136 { "behavior", "operating behavior and temp selector", 137 true, sysctl_dbcool_behavior }, 138 { "min_duty", "minimum fan controller PWM duty cycle", 139 true, sysctl_dbcool_duty }, 140 { "max_duty", "maximum fan controller PWM duty cycle", 141 true, sysctl_dbcool_duty }, 142 { "cur_duty", "current fan controller PWM duty cycle", 143 false, sysctl_dbcool_duty }, 144 145 /* 146 * The rest of these should be in the order in which they 147 * are to be stored in the sysctl tree; the table index is 148 * used as the high-order bits of the sysctl_num to maintain 149 * the sequence. 150 * 151 * If you rearrange the order of these items, be sure to 152 * update the sysctl_index in the XXX_sensor_table[] for 153 * the various chips! 154 */ 155 { "Trange", "temp slope/range to reach 100% duty cycle", 156 true, sysctl_dbcool_slope }, 157 { "Tmin", "temp at which to start fan controller", 158 true, sysctl_dbcool_temp }, 159 { "Ttherm", "temp at which THERM is asserted", 160 true, sysctl_dbcool_temp }, 161 { "Thyst", "temp hysteresis for stopping fan controller", 162 true, sysctl_dbcool_thyst }, 163 { "Tmin", "temp at which to start fan controller", 164 true, sysctl_adm1030_temp }, 165 { "Trange", "temp slope/range to reach 100% duty cycle", 166 true, sysctl_adm1030_trange }, 167 }; 168 169 static const char *dbc_sensor_names[] = { 170 "l_temp", "r1_temp", "r2_temp", "Vccp", "Vcc", "fan1", 171 "fan2", "fan3", "fan4", "AIN1", "AIN2", "V2dot5", 172 "V5", "V12", "Vtt", "Imon", "VID" 173 }; 174 175 /* 176 * Following table derived from product data-sheets 177 */ 178 static int64_t nominal_voltages[] = { 179 -1, /* Vcc can be either 3.3 or 5.0V 180 at 3/4 scale */ 181 2249939, /* Vccp 2.25V 3/4 scale */ 182 2497436, /* 2.5VIN 2.5V 3/4 scale */ 183 5002466, /* 5VIN 5V 3/4 scale */ 184 12000000, /* 12VIN 12V 3/4 scale */ 185 1690809, /* Vtt, Imon 2.25V full scale */ 186 1689600, /* AIN1, AIN2 2.25V full scale */ 187 0 188 }; 189 190 /* 191 * Sensor-type, { val-reg, hilim-reg, lolim-reg}, name-idx, sysctl-table-idx, 192 * nom-voltage-index 193 */ 194 struct dbcool_sensor ADT7490_sensor_table[] = { 195 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 196 DBCOOL_LOCAL_HIGHLIM, 197 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 198 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 199 DBCOOL_REMOTE1_HIGHLIM, 200 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 201 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 202 DBCOOL_REMOTE2_HIGHLIM, 203 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 204 { DBC_VOLT, { DBCOOL_VCCP, 205 DBCOOL_VCCP_HIGHLIM, 206 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 207 { DBC_VOLT, { DBCOOL_VCC, 208 DBCOOL_VCC_HIGHLIM, 209 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 210 { DBC_VOLT, { DBCOOL_25VIN, 211 DBCOOL_25VIN_HIGHLIM, 212 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 }, 213 { DBC_VOLT, { DBCOOL_5VIN, 214 DBCOOL_5VIN_HIGHLIM, 215 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 }, 216 { DBC_VOLT, { DBCOOL_12VIN, 217 DBCOOL_12VIN_HIGHLIM, 218 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 }, 219 { DBC_VOLT, { DBCOOL_VTT, 220 DBCOOL_VTT_HIGHLIM, 221 DBCOOL_VTT_LOWLIM }, 14, 0, 5 }, 222 { DBC_VOLT, { DBCOOL_IMON, 223 DBCOOL_IMON_HIGHLIM, 224 DBCOOL_IMON_LOWLIM }, 15, 0, 5 }, 225 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 226 DBCOOL_NO_REG, 227 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 228 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 229 DBCOOL_NO_REG, 230 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 231 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 232 DBCOOL_NO_REG, 233 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 234 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 235 DBCOOL_NO_REG, 236 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 237 { DBC_VID, { DBCOOL_VID_REG, 238 DBCOOL_NO_REG, 239 DBCOOL_NO_REG }, 16, 0, 0 }, 240 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 241 DBCOOL_NO_REG, 242 DBCOOL_NO_REG }, 0, 5, 0 }, 243 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 244 DBCOOL_NO_REG, 245 DBCOOL_NO_REG }, 0, 6, 0 }, 246 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 247 DBCOOL_NO_REG, 248 DBCOOL_NO_REG }, 0, 7, 0 }, 249 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 250 DBCOOL_NO_REG, 251 DBCOOL_NO_REG }, 1, 5, 0 }, 252 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 253 DBCOOL_NO_REG, 254 DBCOOL_NO_REG }, 1, 6, 0 }, 255 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 256 DBCOOL_NO_REG, 257 DBCOOL_NO_REG }, 1, 7, 0 }, 258 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 259 DBCOOL_NO_REG, 260 DBCOOL_NO_REG }, 2, 5, 0 }, 261 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 262 DBCOOL_NO_REG, 263 DBCOOL_NO_REG }, 2, 6, 0 }, 264 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 265 DBCOOL_NO_REG, 266 DBCOOL_NO_REG }, 2, 7, 0 }, 267 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 268 }; 269 270 struct dbcool_sensor ADT7476_sensor_table[] = { 271 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 272 DBCOOL_LOCAL_HIGHLIM, 273 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 274 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 275 DBCOOL_REMOTE1_HIGHLIM, 276 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 277 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 278 DBCOOL_REMOTE2_HIGHLIM, 279 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 280 { DBC_VOLT, { DBCOOL_VCCP, 281 DBCOOL_VCCP_HIGHLIM, 282 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 283 { DBC_VOLT, { DBCOOL_VCC, 284 DBCOOL_VCC_HIGHLIM, 285 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 286 { DBC_VOLT, { DBCOOL_25VIN, 287 DBCOOL_25VIN_HIGHLIM, 288 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 }, 289 { DBC_VOLT, { DBCOOL_5VIN, 290 DBCOOL_5VIN_HIGHLIM, 291 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 }, 292 { DBC_VOLT, { DBCOOL_12VIN, 293 DBCOOL_12VIN_HIGHLIM, 294 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 }, 295 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 296 DBCOOL_NO_REG, 297 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 298 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 299 DBCOOL_NO_REG, 300 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 301 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 302 DBCOOL_NO_REG, 303 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 304 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 305 DBCOOL_NO_REG, 306 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 307 { DBC_VID, { DBCOOL_VID_REG, 308 DBCOOL_NO_REG, 309 DBCOOL_NO_REG }, 16, 0, 0 }, 310 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 311 DBCOOL_NO_REG, 312 DBCOOL_NO_REG }, 0, 5, 0 }, 313 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 314 DBCOOL_NO_REG, 315 DBCOOL_NO_REG }, 0, 6, 0 }, 316 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 317 DBCOOL_NO_REG, 318 DBCOOL_NO_REG }, 0, 7, 0 }, 319 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 320 DBCOOL_NO_REG, 321 DBCOOL_NO_REG }, 1, 5, 0 }, 322 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 323 DBCOOL_NO_REG, 324 DBCOOL_NO_REG }, 1, 6, 0 }, 325 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 326 DBCOOL_NO_REG, 327 DBCOOL_NO_REG }, 1, 7, 0 }, 328 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 329 DBCOOL_NO_REG, 330 DBCOOL_NO_REG }, 2, 5, 0 }, 331 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 332 DBCOOL_NO_REG, 333 DBCOOL_NO_REG }, 2, 6, 0 }, 334 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 335 DBCOOL_NO_REG, 336 DBCOOL_NO_REG }, 2, 7, 0 }, 337 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 338 }; 339 340 struct dbcool_sensor ADT7475_sensor_table[] = { 341 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 342 DBCOOL_LOCAL_HIGHLIM, 343 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 344 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 345 DBCOOL_REMOTE1_HIGHLIM, 346 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 347 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 348 DBCOOL_REMOTE2_HIGHLIM, 349 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 350 { DBC_VOLT, { DBCOOL_VCCP, 351 DBCOOL_VCCP_HIGHLIM, 352 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 353 { DBC_VOLT, { DBCOOL_VCC, 354 DBCOOL_VCC_HIGHLIM, 355 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 356 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 357 DBCOOL_NO_REG, 358 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 359 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 360 DBCOOL_NO_REG, 361 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 362 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 363 DBCOOL_NO_REG, 364 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 365 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 366 DBCOOL_NO_REG, 367 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 368 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 369 DBCOOL_NO_REG, 370 DBCOOL_NO_REG }, 0, 5, 0 }, 371 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 372 DBCOOL_NO_REG, 373 DBCOOL_NO_REG }, 0, 6, 0 }, 374 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 375 DBCOOL_NO_REG, 376 DBCOOL_NO_REG }, 0, 7, 0 }, 377 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 378 DBCOOL_NO_REG, 379 DBCOOL_NO_REG }, 1, 5, 0 }, 380 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 381 DBCOOL_NO_REG, 382 DBCOOL_NO_REG }, 1, 6, 0 }, 383 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 384 DBCOOL_NO_REG, 385 DBCOOL_NO_REG }, 1, 7, 0 }, 386 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 387 DBCOOL_NO_REG, 388 DBCOOL_NO_REG }, 2, 5, 0 }, 389 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 390 DBCOOL_NO_REG, 391 DBCOOL_NO_REG }, 2, 6, 0 }, 392 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 393 DBCOOL_NO_REG, 394 DBCOOL_NO_REG }, 2, 7, 0 }, 395 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 396 }; 397 398 /* 399 * The registers of dbcool_power_control must be in the same order as 400 * in enum dbc_pwm_params 401 */ 402 struct dbcool_power_control ADT7475_power_table[] = { 403 { { DBCOOL_PWM1_CTL, DBCOOL_PWM1_MINDUTY, 404 DBCOOL_PWM1_MAXDUTY, DBCOOL_PWM1_CURDUTY }, 405 "fan_control_1" }, 406 { { DBCOOL_PWM2_CTL, DBCOOL_PWM2_MINDUTY, 407 DBCOOL_PWM2_MAXDUTY, DBCOOL_PWM2_CURDUTY }, 408 "fan_control_2" }, 409 { { DBCOOL_PWM3_CTL, DBCOOL_PWM3_MINDUTY, 410 DBCOOL_PWM3_MAXDUTY, DBCOOL_PWM3_CURDUTY }, 411 "fan_control_3" }, 412 { { 0, 0, 0, 0 }, NULL } 413 }; 414 415 struct dbcool_sensor ADT7466_sensor_table[] = { 416 { DBC_TEMP, { DBCOOL_ADT7466_LCL_TEMP_MSB, 417 DBCOOL_ADT7466_LCL_TEMP_HILIM, 418 DBCOOL_ADT7466_LCL_TEMP_LOLIM }, 0, 0, 0 }, 419 { DBC_TEMP, { DBCOOL_ADT7466_REM_TEMP_MSB, 420 DBCOOL_ADT7466_REM_TEMP_HILIM, 421 DBCOOL_ADT7466_REM_TEMP_LOLIM }, 1, 0, 0 }, 422 { DBC_VOLT, { DBCOOL_ADT7466_VCC, 423 DBCOOL_ADT7466_VCC_HILIM, 424 DBCOOL_ADT7466_VCC_LOLIM }, 4, 0, 0 }, 425 { DBC_VOLT, { DBCOOL_ADT7466_AIN1, 426 DBCOOL_ADT7466_AIN1_HILIM, 427 DBCOOL_ADT7466_AIN1_LOLIM }, 9, 0, 6 }, 428 { DBC_VOLT, { DBCOOL_ADT7466_AIN2, 429 DBCOOL_ADT7466_AIN2_HILIM, 430 DBCOOL_ADT7466_AIN2_LOLIM }, 10, 0, 6 }, 431 { DBC_FAN, { DBCOOL_ADT7466_FANA_LSB, 432 DBCOOL_NO_REG, 433 DBCOOL_ADT7466_FANA_LOLIM_LSB }, 5, 0, 0 }, 434 { DBC_FAN, { DBCOOL_ADT7466_FANB_LSB, 435 DBCOOL_NO_REG, 436 DBCOOL_ADT7466_FANB_LOLIM_LSB }, 6, 0, 0 }, 437 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 438 }; 439 440 struct dbcool_sensor ADM1027_sensor_table[] = { 441 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 442 DBCOOL_LOCAL_HIGHLIM, 443 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 444 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 445 DBCOOL_REMOTE1_HIGHLIM, 446 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 447 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 448 DBCOOL_REMOTE2_HIGHLIM, 449 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 450 { DBC_VOLT, { DBCOOL_VCCP, 451 DBCOOL_VCCP_HIGHLIM, 452 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 453 { DBC_VOLT, { DBCOOL_VCC, 454 DBCOOL_VCC_HIGHLIM, 455 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 456 { DBC_VOLT, { DBCOOL_25VIN, 457 DBCOOL_25VIN_HIGHLIM, 458 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 }, 459 { DBC_VOLT, { DBCOOL_5VIN, 460 DBCOOL_5VIN_HIGHLIM, 461 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 }, 462 { DBC_VOLT, { DBCOOL_12VIN, 463 DBCOOL_12VIN_HIGHLIM, 464 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 }, 465 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 466 DBCOOL_NO_REG, 467 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 468 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 469 DBCOOL_NO_REG, 470 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 471 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 472 DBCOOL_NO_REG, 473 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 474 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 475 DBCOOL_NO_REG, 476 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 477 { DBC_VID, { DBCOOL_VID_REG, 478 DBCOOL_NO_REG, 479 DBCOOL_NO_REG }, 16, 0, 0 }, 480 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 481 DBCOOL_NO_REG, 482 DBCOOL_NO_REG }, 0, 5, 0 }, 483 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 484 DBCOOL_NO_REG, 485 DBCOOL_NO_REG }, 0, 6, 0 }, 486 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 487 DBCOOL_NO_REG, 488 DBCOOL_NO_REG }, 0, 7, 0 }, 489 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 490 DBCOOL_NO_REG, 491 DBCOOL_NO_REG }, 1, 5, 0 }, 492 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 493 DBCOOL_NO_REG, 494 DBCOOL_NO_REG }, 1, 6, 0 }, 495 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 496 DBCOOL_NO_REG, 497 DBCOOL_NO_REG }, 1, 7, 0 }, 498 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 499 DBCOOL_NO_REG, 500 DBCOOL_NO_REG }, 2, 5, 0 }, 501 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 502 DBCOOL_NO_REG, 503 DBCOOL_NO_REG }, 2, 6, 0 }, 504 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 505 DBCOOL_NO_REG, 506 DBCOOL_NO_REG }, 2, 7, 0 }, 507 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 508 }; 509 510 struct dbcool_sensor ADM1030_sensor_table[] = { 511 { DBC_TEMP, { DBCOOL_ADM1030_L_TEMP, 512 DBCOOL_ADM1030_L_HI_LIM, 513 DBCOOL_ADM1030_L_LO_LIM }, 0, 0, 0 }, 514 { DBC_TEMP, { DBCOOL_ADM1030_R_TEMP, 515 DBCOOL_ADM1030_R_HI_LIM, 516 DBCOOL_ADM1030_R_LO_LIM }, 1, 0, 0 }, 517 { DBC_FAN, { DBCOOL_ADM1030_FAN_TACH, 518 DBCOOL_NO_REG, 519 DBCOOL_ADM1030_FAN_LO_LIM }, 5, 0, 0 }, 520 { DBC_CTL, { DBCOOL_ADM1030_L_TMIN, 521 DBCOOL_NO_REG, 522 DBCOOL_NO_REG }, 0, 8, 0 }, 523 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH, 524 DBCOOL_NO_REG, 525 DBCOOL_NO_REG }, 0, 9, 0 }, 526 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH, 527 DBCOOL_NO_REG, 528 DBCOOL_NO_REG }, 0, 6, 0 }, 529 { DBC_CTL, { DBCOOL_ADM1030_R_TMIN, 530 DBCOOL_NO_REG, 531 DBCOOL_NO_REG }, 1, 8, 0 }, 532 { DBC_CTL, { DBCOOL_ADM1030_R_TTHRESH, 533 DBCOOL_NO_REG, 534 DBCOOL_NO_REG }, 1, 9, 0 }, 535 { DBC_CTL, { DBCOOL_ADM1030_R_TTHRESH, 536 DBCOOL_NO_REG, 537 DBCOOL_NO_REG }, 1, 6, 0 }, 538 { DBC_EOF, {0, 0, 0 }, 0, 0, 0 } 539 }; 540 541 struct dbcool_power_control ADM1030_power_table[] = { 542 { { DBCOOL_ADM1030_CFG1, DBCOOL_NO_REG, DBCOOL_NO_REG, 543 DBCOOL_ADM1030_FAN_SPEED_CFG }, 544 "fan_control_1" }, 545 { { 0, 0, 0, 0 }, NULL } 546 }; 547 548 struct dbcool_sensor ADM1031_sensor_table[] = { 549 { DBC_TEMP, { DBCOOL_ADM1030_L_TEMP, 550 DBCOOL_ADM1030_L_HI_LIM, 551 DBCOOL_ADM1030_L_LO_LIM }, 0, 0, 0 }, 552 { DBC_TEMP, { DBCOOL_ADM1030_R_TEMP, 553 DBCOOL_ADM1030_R_HI_LIM, 554 DBCOOL_ADM1030_R_LO_LIM }, 1, 0, 0 }, 555 { DBC_TEMP, { DBCOOL_ADM1031_R2_TEMP, 556 DBCOOL_ADM1031_R2_HI_LIM, 557 DBCOOL_ADM1031_R2_LO_LIM }, 2, 0, 0 }, 558 { DBC_FAN, { DBCOOL_ADM1030_FAN_TACH, 559 DBCOOL_NO_REG, 560 DBCOOL_ADM1030_FAN_LO_LIM }, 5, 0, 0 }, 561 { DBC_FAN, { DBCOOL_ADM1031_FAN2_TACH, 562 DBCOOL_NO_REG, 563 DBCOOL_ADM1031_FAN2_LO_LIM }, 6, 0, 0 }, 564 { DBC_CTL, { DBCOOL_ADM1030_L_TMIN, 565 DBCOOL_NO_REG, 566 DBCOOL_NO_REG }, 0, 8, 0 }, 567 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH, 568 DBCOOL_NO_REG, 569 DBCOOL_NO_REG }, 0, 9, 0 }, 570 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH, 571 DBCOOL_NO_REG, 572 DBCOOL_NO_REG }, 0, 6, 0 }, 573 { DBC_CTL, { DBCOOL_ADM1030_R_TMIN, 574 DBCOOL_NO_REG, 575 DBCOOL_NO_REG }, 1, 8, 0 }, 576 { DBC_CTL, { DBCOOL_ADM1030_R_TTHRESH, 577 DBCOOL_NO_REG, 578 DBCOOL_NO_REG }, 1, 9, 0 }, 579 { DBC_CTL, { DBCOOL_ADM1030_R_TTHRESH, 580 DBCOOL_NO_REG, 581 DBCOOL_NO_REG }, 1, 6, 0 }, 582 { DBC_CTL, { DBCOOL_ADM1031_R2_TMIN, 583 DBCOOL_NO_REG, 584 DBCOOL_NO_REG }, 2, 8, 0 }, 585 { DBC_CTL, { DBCOOL_ADM1031_R2_TTHRESH, 586 DBCOOL_NO_REG, 587 DBCOOL_NO_REG }, 2, 9, 0 }, 588 { DBC_CTL, { DBCOOL_ADM1031_R2_TTHRESH, 589 DBCOOL_NO_REG, 590 DBCOOL_NO_REG }, 2, 6, 0 }, 591 { DBC_EOF, {0, 0, 0 }, 0, 0, 0 } 592 }; 593 594 struct dbcool_power_control ADM1031_power_table[] = { 595 { { DBCOOL_ADM1030_CFG1, DBCOOL_NO_REG, DBCOOL_NO_REG, 596 DBCOOL_ADM1030_FAN_SPEED_CFG }, 597 "fan_control_1" }, 598 { { DBCOOL_ADM1030_CFG1, DBCOOL_NO_REG, DBCOOL_NO_REG, 599 DBCOOL_ADM1030_FAN_SPEED_CFG }, 600 "fan_control_2" }, 601 { { 0, 0, 0, 0 }, NULL } 602 }; 603 604 struct dbcool_sensor EMC6D103S_sensor_table[] = { 605 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 606 DBCOOL_LOCAL_HIGHLIM, 607 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 608 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 609 DBCOOL_REMOTE1_HIGHLIM, 610 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 611 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 612 DBCOOL_REMOTE2_HIGHLIM, 613 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 614 { DBC_VOLT, { DBCOOL_VCCP, 615 DBCOOL_VCCP_HIGHLIM, 616 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 617 { DBC_VOLT, { DBCOOL_VCC, 618 DBCOOL_VCC_HIGHLIM, 619 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 620 { DBC_VOLT, { DBCOOL_25VIN, 621 DBCOOL_25VIN_HIGHLIM, 622 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 }, 623 { DBC_VOLT, { DBCOOL_5VIN, 624 DBCOOL_5VIN_HIGHLIM, 625 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 }, 626 { DBC_VOLT, { DBCOOL_12VIN, 627 DBCOOL_12VIN_HIGHLIM, 628 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 }, 629 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 630 DBCOOL_NO_REG, 631 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 632 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 633 DBCOOL_NO_REG, 634 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 635 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 636 DBCOOL_NO_REG, 637 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 638 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 639 DBCOOL_NO_REG, 640 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 641 { DBC_VID, { DBCOOL_VID_REG, 642 DBCOOL_NO_REG, 643 DBCOOL_NO_REG }, 16, 0, 0 }, 644 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 645 DBCOOL_NO_REG, 646 DBCOOL_NO_REG }, 0, 5, 0 }, 647 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 648 DBCOOL_NO_REG, 649 DBCOOL_NO_REG }, 0, 6, 0 }, 650 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 651 DBCOOL_NO_REG, 652 DBCOOL_NO_REG }, 1, 5, 0 }, 653 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 654 DBCOOL_NO_REG, 655 DBCOOL_NO_REG }, 1, 6, 0 }, 656 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 657 DBCOOL_NO_REG, 658 DBCOOL_NO_REG }, 2, 5, 0 }, 659 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 660 DBCOOL_NO_REG, 661 DBCOOL_NO_REG }, 2, 6, 0 }, 662 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 663 }; 664 665 struct chip_id chip_table[] = { 666 { DBCOOL_COMPANYID, ADT7490_DEVICEID, ADT7490_REV_ID, 667 ADT7490_sensor_table, ADT7475_power_table, 668 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_PECI, 669 90000 * 60, "ADT7490" }, 670 { DBCOOL_COMPANYID, ADT7476_DEVICEID, 0xff, 671 ADT7476_sensor_table, ADT7475_power_table, 672 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY, 673 90000 * 60, "ADT7476" }, 674 { DBCOOL_COMPANYID, ADT7475_DEVICEID, 0xff, 675 ADT7475_sensor_table, ADT7475_power_table, 676 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_SHDN, 677 90000 * 60, "ADT7475" }, 678 { DBCOOL_COMPANYID, ADT7473_DEVICEID, ADT7473_REV_ID1, 679 ADT7475_sensor_table, ADT7475_power_table, 680 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_SHDN, 681 90000 * 60, "ADT7460/ADT7463" }, 682 { DBCOOL_COMPANYID, ADT7473_DEVICEID, ADT7473_REV_ID2, 683 ADT7475_sensor_table, ADT7475_power_table, 684 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_SHDN, 685 90000 * 60, "ADT7463-1" }, 686 { DBCOOL_COMPANYID, ADT7468_DEVICEID, 0xff, 687 ADT7476_sensor_table, ADT7475_power_table, 688 DBCFLAG_TEMPOFFSET | DBCFLAG_MULTI_VCC | DBCFLAG_HAS_MAXDUTY | 689 DBCFLAG_4BIT_VER | DBCFLAG_HAS_SHDN, 690 90000 * 60, "ADT7467/ADT7468" }, 691 { DBCOOL_COMPANYID, ADT7466_DEVICEID, 0xff, 692 ADT7466_sensor_table, NULL, 693 DBCFLAG_ADT7466 | DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_SHDN, 694 82000 * 60, "ADT7466" }, 695 { DBCOOL_COMPANYID, ADT7463_DEVICEID, ADT7463_REV_ID1, 696 ADM1027_sensor_table, ADT7475_power_table, 697 DBCFLAG_MULTI_VCC | DBCFLAG_4BIT_VER | DBCFLAG_HAS_SHDN, 698 90000 * 60, "ADT7463" }, 699 { DBCOOL_COMPANYID, ADT7463_DEVICEID, ADT7463_REV_ID2, 700 ADM1027_sensor_table, ADT7475_power_table, 701 DBCFLAG_MULTI_VCC | DBCFLAG_4BIT_VER | DBCFLAG_HAS_SHDN | 702 DBCFLAG_HAS_VID_SEL, 703 90000 * 60, "ADT7463" }, 704 { DBCOOL_COMPANYID, ADM1027_DEVICEID, ADM1027_REV_ID, 705 ADM1027_sensor_table, ADT7475_power_table, 706 DBCFLAG_MULTI_VCC | DBCFLAG_4BIT_VER, 707 90000 * 60, "ADM1027" }, 708 { DBCOOL_COMPANYID, ADM1030_DEVICEID, 0xff, 709 ADM1030_sensor_table, ADM1030_power_table, 710 DBCFLAG_ADM1030 | DBCFLAG_NO_READBYTE, 711 11250 * 60, "ADM1030" }, 712 { DBCOOL_COMPANYID, ADM1031_DEVICEID, 0xff, 713 ADM1031_sensor_table, ADM1030_power_table, 714 DBCFLAG_ADM1030 | DBCFLAG_NO_READBYTE, 715 11250 * 60, "ADM1031" }, 716 { SMSC_COMPANYID, EMC6D103S_DEVICEID, EMC6D103S_REV_ID, 717 EMC6D103S_sensor_table, ADT7475_power_table, 718 DBCFLAG_4BIT_VER, 719 90000 * 60, "EMC6D103S" }, 720 { 0, 0, 0, NULL, NULL, 0, 0, NULL } 721 }; 722 723 static const char *behavior[] = { 724 "remote1", "local", "remote2", "full-speed", 725 "disabled", "local+remote2","all-temps", "manual" 726 }; 727 728 static char dbcool_cur_behav[16]; 729 730 CFATTACH_DECL_NEW(dbcool, sizeof(struct dbcool_softc), 731 dbcool_match, dbcool_attach, dbcool_detach, NULL); 732 733 int 734 dbcool_match(device_t parent, cfdata_t cf, void *aux) 735 { 736 struct i2c_attach_args *ia = aux; 737 struct dbcool_chipset dc; 738 dc.dc_tag = ia->ia_tag; 739 dc.dc_addr = ia->ia_addr; 740 dc.dc_chip = NULL; 741 dc.dc_readreg = dbcool_readreg; 742 dc.dc_writereg = dbcool_writereg; 743 744 /* no probing if we attach to iic, but verify chip id and address */ 745 if ((ia->ia_addr & DBCOOL_ADDRMASK) != DBCOOL_ADDR) 746 return 0; 747 if (dbcool_chip_ident(&dc) >= 0) 748 return 1; 749 750 return 0; 751 } 752 753 void 754 dbcool_attach(device_t parent, device_t self, void *aux) 755 { 756 struct dbcool_softc *sc = device_private(self); 757 struct i2c_attach_args *args = aux; 758 uint8_t ver; 759 760 sc->sc_dc.dc_addr = args->ia_addr; 761 sc->sc_dc.dc_tag = args->ia_tag; 762 sc->sc_dc.dc_chip = NULL; 763 sc->sc_dc.dc_readreg = dbcool_readreg; 764 sc->sc_dc.dc_writereg = dbcool_writereg; 765 (void)dbcool_chip_ident(&sc->sc_dc); 766 sc->sc_dev = self; 767 768 aprint_naive("\n"); 769 aprint_normal("\n"); 770 771 ver = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_REVISION_REG); 772 if (sc->sc_dc.dc_chip->flags & DBCFLAG_4BIT_VER) 773 if (sc->sc_dc.dc_chip->company == SMSC_COMPANYID) 774 { 775 aprint_normal_dev(self, "SMSC %s Controller " 776 "(rev 0x%02x, stepping 0x%02x)\n", sc->sc_dc.dc_chip->name, 777 ver >> 4, ver & 0x0f); 778 } else { 779 aprint_normal_dev(self, "%s dBCool(tm) Controller " 780 "(rev 0x%02x, stepping 0x%02x)\n", sc->sc_dc.dc_chip->name, 781 ver >> 4, ver & 0x0f); 782 } 783 else 784 aprint_normal_dev(self, "%s dBCool(tm) Controller " 785 "(rev 0x%04x)\n", sc->sc_dc.dc_chip->name, ver); 786 787 dbcool_setup(self); 788 789 if (!pmf_device_register(self, dbcool_pmf_suspend, dbcool_pmf_resume)) 790 aprint_error_dev(self, "couldn't establish power handler\n"); 791 } 792 793 static int 794 dbcool_detach(device_t self, int flags) 795 { 796 struct dbcool_softc *sc = device_private(self); 797 798 pmf_device_deregister(self); 799 800 sysmon_envsys_unregister(sc->sc_sme); 801 sc->sc_sme = NULL; 802 return 0; 803 } 804 805 /* On suspend, we save the state of the SHDN bit, then set it */ 806 bool dbcool_pmf_suspend(device_t dev, const pmf_qual_t *qual) 807 { 808 struct dbcool_softc *sc = device_private(dev); 809 uint8_t reg, bit, cfg; 810 811 if ((sc->sc_dc.dc_chip->flags && DBCFLAG_HAS_SHDN) == 0) 812 return true; 813 814 if (sc->sc_dc.dc_chip->flags && DBCFLAG_ADT7466) { 815 reg = DBCOOL_ADT7466_CONFIG2; 816 bit = DBCOOL_ADT7466_CFG2_SHDN; 817 } else { 818 reg = DBCOOL_CONFIG2_REG; 819 bit = DBCOOL_CFG2_SHDN; 820 } 821 cfg = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 822 sc->sc_suspend = cfg & bit; 823 cfg |= bit; 824 sc->sc_dc.dc_writereg(&sc->sc_dc, reg, cfg); 825 826 return true; 827 } 828 829 /* On resume, we restore the previous state of the SHDN bit */ 830 bool dbcool_pmf_resume(device_t dev, const pmf_qual_t *qual) 831 { 832 struct dbcool_softc *sc = device_private(dev); 833 uint8_t reg, bit, cfg; 834 835 if ((sc->sc_dc.dc_chip->flags && DBCFLAG_HAS_SHDN) == 0) 836 return true; 837 838 if (sc->sc_dc.dc_chip->flags && DBCFLAG_ADT7466) { 839 reg = DBCOOL_ADT7466_CONFIG2; 840 bit = DBCOOL_ADT7466_CFG2_SHDN; 841 } else { 842 reg = DBCOOL_CONFIG2_REG; 843 bit = DBCOOL_CFG2_SHDN; 844 } 845 cfg = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 846 cfg &= ~sc->sc_suspend; 847 sc->sc_dc.dc_writereg(&sc->sc_dc, reg, cfg); 848 849 return true; 850 851 } 852 853 uint8_t 854 dbcool_readreg(struct dbcool_chipset *dc, uint8_t reg) 855 { 856 uint8_t data = 0; 857 858 if (iic_acquire_bus(dc->dc_tag, 0) != 0) 859 return data; 860 861 if (dc->dc_chip == NULL || dc->dc_chip->flags & DBCFLAG_NO_READBYTE) { 862 /* ADM1027 doesn't support i2c read_byte protocol */ 863 if (iic_smbus_send_byte(dc->dc_tag, dc->dc_addr, reg, 0) != 0) 864 goto bad; 865 (void)iic_smbus_receive_byte(dc->dc_tag, dc->dc_addr, &data, 0); 866 } else 867 (void)iic_smbus_read_byte(dc->dc_tag, dc->dc_addr, reg, &data, 868 0); 869 870 bad: 871 iic_release_bus(dc->dc_tag, 0); 872 return data; 873 } 874 875 void 876 dbcool_writereg(struct dbcool_chipset *dc, uint8_t reg, uint8_t val) 877 { 878 if (iic_acquire_bus(dc->dc_tag, 0) != 0) 879 return; 880 881 (void)iic_smbus_write_byte(dc->dc_tag, dc->dc_addr, reg, val, 0); 882 883 iic_release_bus(dc->dc_tag, 0); 884 } 885 886 static bool 887 dbcool_islocked(struct dbcool_softc *sc) 888 { 889 uint8_t cfg_reg; 890 891 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 892 return 0; 893 894 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) 895 cfg_reg = DBCOOL_ADT7466_CONFIG1; 896 else 897 cfg_reg = DBCOOL_CONFIG1_REG; 898 899 if (sc->sc_dc.dc_readreg(&sc->sc_dc, cfg_reg) & DBCOOL_CFG1_LOCK) 900 return 1; 901 else 902 return 0; 903 } 904 905 static int 906 dbcool_read_temp(struct dbcool_softc *sc, uint8_t reg, bool extres) 907 { 908 uint8_t t1, t2, t3, val, ext = 0; 909 int temp; 910 911 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) { 912 /* 913 * ADT7466 temps are in strange location 914 */ 915 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADT7466_CONFIG1); 916 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 917 if (extres) 918 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, reg + 1); 919 } else if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) { 920 /* 921 * ADM1030 temps are in their own special place, too 922 */ 923 if (extres) { 924 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_TEMP_EXTRES); 925 if (reg == DBCOOL_ADM1030_L_TEMP) 926 ext >>= 6; 927 else if (reg == DBCOOL_ADM1031_R2_TEMP) 928 ext >>= 4; 929 else 930 ext >>= 1; 931 ext &= 0x03; 932 } 933 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 934 } else if (extres) { 935 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES2_REG); 936 937 /* Read all msb regs to unlatch them */ 938 t1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_12VIN); 939 t1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_REMOTE1_TEMP); 940 t2 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_REMOTE2_TEMP); 941 t3 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_LOCAL_TEMP); 942 switch (reg) { 943 case DBCOOL_REMOTE1_TEMP: 944 val = t1; 945 ext >>= 2; 946 break; 947 case DBCOOL_LOCAL_TEMP: 948 val = t3; 949 ext >>= 4; 950 break; 951 case DBCOOL_REMOTE2_TEMP: 952 val = t2; 953 ext >>= 6; 954 break; 955 default: 956 val = 0; 957 break; 958 } 959 ext &= 0x03; 960 } 961 else 962 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 963 964 /* Check for invalid temp values */ 965 if ((sc->sc_temp_offset == 0 && val == 0x80) || 966 (sc->sc_temp_offset != 0 && val == 0)) 967 return 0; 968 969 /* If using offset mode, adjust, else treat as signed */ 970 if (sc->sc_temp_offset) { 971 temp = val; 972 temp -= sc->sc_temp_offset; 973 } else 974 temp = (int8_t)val; 975 976 /* Convert degC to uK and include extended precision bits */ 977 temp *= 1000000; 978 temp += 250000 * (int)ext; 979 temp += 273150000U; 980 981 return temp; 982 } 983 984 static int 985 dbcool_read_rpm(struct dbcool_softc *sc, uint8_t reg) 986 { 987 int rpm; 988 uint8_t rpm_lo, rpm_hi; 989 990 rpm_lo = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 991 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 992 rpm_hi = (rpm_lo == 0xff)?0xff:0x0; 993 else 994 rpm_hi = sc->sc_dc.dc_readreg(&sc->sc_dc, reg + 1); 995 996 rpm = (rpm_hi << 8) | rpm_lo; 997 if (rpm == 0xffff) 998 return 0; /* 0xffff indicates stalled/failed fan */ 999 1000 /* don't divide by zero */ 1001 return (rpm == 0)? 0 : (sc->sc_dc.dc_chip->rpm_dividend / rpm); 1002 } 1003 1004 /* Provide chip's supply voltage, in microvolts */ 1005 static int 1006 dbcool_supply_voltage(struct dbcool_softc *sc) 1007 { 1008 if (sc->sc_dc.dc_chip->flags & DBCFLAG_MULTI_VCC) { 1009 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_CONFIG1_REG) & DBCOOL_CFG1_Vcc) 1010 return 5002500; 1011 else 1012 return 3300000; 1013 } else if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) { 1014 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADT7466_CONFIG1) & 1015 DBCOOL_ADT7466_CFG1_Vcc) 1016 return 5000000; 1017 else 1018 return 3300000; 1019 } else 1020 return 3300000; 1021 } 1022 1023 /* 1024 * Nominal voltages are calculated in microvolts 1025 */ 1026 static int 1027 dbcool_read_volt(struct dbcool_softc *sc, uint8_t reg, int nom_idx, bool extres) 1028 { 1029 uint8_t ext = 0, v1, v2, v3, v4, val; 1030 int64_t ret; 1031 int64_t nom; 1032 1033 nom = nominal_voltages[nom_idx]; 1034 if (nom < 0) 1035 nom = sc->sc_supply_voltage; 1036 1037 /* ADT7466 voltages are in strange locations with only 8-bits */ 1038 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) 1039 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 1040 else 1041 /* 1042 * It's a "normal" dbCool chip - check for regs that 1043 * share extended resolution bits since we have to 1044 * read all the MSB registers to unlatch them. 1045 */ 1046 if (!extres) 1047 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 1048 else if (reg == DBCOOL_12VIN) { 1049 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES2_REG) && 0x03; 1050 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 1051 (void)dbcool_read_temp(sc, DBCOOL_LOCAL_TEMP, true); 1052 } else if (reg == DBCOOL_VTT || reg == DBCOOL_IMON) { 1053 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES_VTT_IMON); 1054 v1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_IMON); 1055 v2 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VTT); 1056 if (reg == DBCOOL_IMON) { 1057 val = v1; 1058 ext >>= 6; 1059 } else 1060 val = v2; 1061 ext >>= 4; 1062 ext &= 0x0f; 1063 } else { 1064 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES1_REG); 1065 v1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_25VIN); 1066 v2 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VCCP); 1067 v3 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VCC); 1068 v4 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_5VIN); 1069 1070 switch (reg) { 1071 case DBCOOL_25VIN: 1072 val = v1; 1073 break; 1074 case DBCOOL_VCCP: 1075 val = v2; 1076 ext >>= 2; 1077 break; 1078 case DBCOOL_VCC: 1079 val = v3; 1080 ext >>= 4; 1081 break; 1082 case DBCOOL_5VIN: 1083 val = v4; 1084 ext >>= 6; 1085 break; 1086 default: 1087 val = nom = 0; 1088 } 1089 ext &= 0x03; 1090 } 1091 1092 /* 1093 * Scale the nominal value by the 10-bit fraction 1094 * 1095 * Returned value is in microvolts. 1096 */ 1097 ret = val; 1098 ret <<= 2; 1099 ret |= ext; 1100 ret = (ret * nom) / 0x300; 1101 1102 return ret; 1103 } 1104 1105 SYSCTL_SETUP(sysctl_dbcoolsetup, "sysctl dBCool subtree setup") 1106 { 1107 sysctl_createv(NULL, 0, NULL, NULL, 1108 CTLFLAG_PERMANENT, 1109 CTLTYPE_NODE, "hw", NULL, 1110 NULL, 0, NULL, 0, 1111 CTL_HW, CTL_EOL); 1112 } 1113 1114 static int 1115 sysctl_dbcool_temp(SYSCTLFN_ARGS) 1116 { 1117 struct sysctlnode node; 1118 struct dbcool_softc *sc; 1119 int reg, error; 1120 uint8_t chipreg; 1121 uint8_t newreg; 1122 1123 node = *rnode; 1124 sc = (struct dbcool_softc *)node.sysctl_data; 1125 chipreg = node.sysctl_num & 0xff; 1126 1127 if (sc->sc_temp_offset) { 1128 reg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1129 reg -= sc->sc_temp_offset; 1130 } else 1131 reg = (int8_t)sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1132 1133 node.sysctl_data = ® 1134 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1135 1136 if (error || newp == NULL) 1137 return error; 1138 1139 /* We were asked to update the value - sanity check before writing */ 1140 if (*(int *)node.sysctl_data < -64 || 1141 *(int *)node.sysctl_data > 127 + sc->sc_temp_offset) 1142 return EINVAL; 1143 1144 newreg = *(int *)node.sysctl_data; 1145 newreg += sc->sc_temp_offset; 1146 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1147 return 0; 1148 } 1149 1150 static int 1151 sysctl_adm1030_temp(SYSCTLFN_ARGS) 1152 { 1153 struct sysctlnode node; 1154 struct dbcool_softc *sc; 1155 int reg, error; 1156 uint8_t chipreg, oldreg, newreg; 1157 1158 node = *rnode; 1159 sc = (struct dbcool_softc *)node.sysctl_data; 1160 chipreg = node.sysctl_num & 0xff; 1161 1162 oldreg = (int8_t)sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1163 reg = (oldreg >> 1) & ~0x03; 1164 1165 node.sysctl_data = ® 1166 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1167 1168 if (error || newp == NULL) 1169 return error; 1170 1171 /* We were asked to update the value - sanity check before writing */ 1172 if (*(int *)node.sysctl_data < 0 || *(int *)node.sysctl_data > 127) 1173 return EINVAL; 1174 1175 newreg = *(int *)node.sysctl_data; 1176 newreg &= ~0x03; 1177 newreg <<= 1; 1178 newreg |= (oldreg & 0x07); 1179 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1180 return 0; 1181 } 1182 1183 static int 1184 sysctl_adm1030_trange(SYSCTLFN_ARGS) 1185 { 1186 struct sysctlnode node; 1187 struct dbcool_softc *sc; 1188 int reg, error, newval; 1189 uint8_t chipreg, oldreg, newreg; 1190 1191 node = *rnode; 1192 sc = (struct dbcool_softc *)node.sysctl_data; 1193 chipreg = node.sysctl_num & 0xff; 1194 1195 oldreg = (int8_t)sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1196 reg = oldreg & 0x07; 1197 1198 node.sysctl_data = ® 1199 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1200 1201 if (error || newp == NULL) 1202 return error; 1203 1204 /* We were asked to update the value - sanity check before writing */ 1205 newval = *(int *)node.sysctl_data; 1206 1207 if (newval == 5) 1208 newreg = 0; 1209 else if (newval == 10) 1210 newreg = 1; 1211 else if (newval == 20) 1212 newreg = 2; 1213 else if (newval == 40) 1214 newreg = 3; 1215 else if (newval == 80) 1216 newreg = 4; 1217 else 1218 return EINVAL; 1219 1220 newreg |= (oldreg & ~0x07); 1221 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1222 return 0; 1223 } 1224 1225 static int 1226 sysctl_dbcool_duty(SYSCTLFN_ARGS) 1227 { 1228 struct sysctlnode node; 1229 struct dbcool_softc *sc; 1230 int reg, error; 1231 uint8_t chipreg, oldreg, newreg; 1232 1233 node = *rnode; 1234 sc = (struct dbcool_softc *)node.sysctl_data; 1235 chipreg = node.sysctl_num & 0xff; 1236 1237 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1238 reg = (uint32_t)oldreg; 1239 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 1240 reg = ((reg & 0x0f) * 100) / 15; 1241 else 1242 reg = (reg * 100) / 255; 1243 node.sysctl_data = ® 1244 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1245 1246 if (error || newp == NULL) 1247 return error; 1248 1249 /* We were asked to update the value - sanity check before writing */ 1250 if (*(int *)node.sysctl_data < 0 || *(int *)node.sysctl_data > 100) 1251 return EINVAL; 1252 1253 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) { 1254 newreg = *(uint8_t *)(node.sysctl_data) * 15 / 100; 1255 newreg |= oldreg & 0xf0; 1256 } else 1257 newreg = *(uint8_t *)(node.sysctl_data) * 255 / 100; 1258 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1259 return 0; 1260 } 1261 1262 static int 1263 sysctl_dbcool_behavior(SYSCTLFN_ARGS) 1264 { 1265 struct sysctlnode node; 1266 struct dbcool_softc *sc; 1267 int i, reg, error; 1268 uint8_t chipreg, oldreg, newreg; 1269 1270 node = *rnode; 1271 sc = (struct dbcool_softc *)node.sysctl_data; 1272 chipreg = node.sysctl_num & 0xff; 1273 1274 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1275 1276 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) { 1277 if ((sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_CFG2) & 1) == 0) 1278 reg = 4; 1279 else if ((oldreg & 0x80) == 0) 1280 reg = 7; 1281 else if ((oldreg & 0x60) == 0) 1282 reg = 4; 1283 else 1284 reg = 6; 1285 } else 1286 reg = (oldreg >> 5) & 0x07; 1287 1288 strlcpy(dbcool_cur_behav, behavior[reg], sizeof(dbcool_cur_behav)); 1289 node.sysctl_data = dbcool_cur_behav; 1290 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1291 1292 if (error || newp == NULL) 1293 return error; 1294 1295 /* We were asked to update the value - convert string to value */ 1296 newreg = __arraycount(behavior); 1297 for (i = 0; i < __arraycount(behavior); i++) 1298 if (strcmp(node.sysctl_data, behavior[i]) == 0) 1299 break; 1300 if (i >= __arraycount(behavior)) 1301 return EINVAL; 1302 1303 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) { 1304 /* 1305 * ADM1030 splits fan controller behavior across two 1306 * registers. We also do not support Auto-Filter mode 1307 * nor do we support Manual-RPM-feedback. 1308 */ 1309 if (newreg == 4) { 1310 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_CFG2); 1311 oldreg &= ~0x01; 1312 sc->sc_dc.dc_writereg(&sc->sc_dc, DBCOOL_ADM1030_CFG2, oldreg); 1313 } else { 1314 if (newreg == 0) 1315 newreg = 4; 1316 else if (newreg == 6) 1317 newreg = 7; 1318 else if (newreg == 7) 1319 newreg = 0; 1320 else 1321 return EINVAL; 1322 newreg <<= 5; 1323 newreg |= (oldreg & 0x1f); 1324 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1325 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_CFG2) | 1; 1326 sc->sc_dc.dc_writereg(&sc->sc_dc, DBCOOL_ADM1030_CFG2, oldreg); 1327 } 1328 } else { 1329 newreg = (sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg) & 0x1f) | (i << 5); 1330 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1331 } 1332 return 0; 1333 } 1334 1335 static int 1336 sysctl_dbcool_slope(SYSCTLFN_ARGS) 1337 { 1338 struct sysctlnode node; 1339 struct dbcool_softc *sc; 1340 int reg, error; 1341 uint8_t chipreg; 1342 uint8_t newreg; 1343 1344 node = *rnode; 1345 sc = (struct dbcool_softc *)node.sysctl_data; 1346 chipreg = node.sysctl_num & 0xff; 1347 1348 reg = (sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg) >> 4) & 0x0f; 1349 node.sysctl_data = ® 1350 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1351 1352 if (error || newp == NULL) 1353 return error; 1354 1355 /* We were asked to update the value - sanity check before writing */ 1356 if (*(int *)node.sysctl_data < 0 || *(int *)node.sysctl_data > 0x0f) 1357 return EINVAL; 1358 1359 newreg = (sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg) & 0x0f) | 1360 (*(int *)node.sysctl_data << 4); 1361 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1362 return 0; 1363 } 1364 1365 static int 1366 sysctl_dbcool_thyst(SYSCTLFN_ARGS) 1367 { 1368 struct sysctlnode node; 1369 struct dbcool_softc *sc; 1370 int reg, error; 1371 uint8_t chipreg; 1372 uint8_t newreg, newhyst; 1373 1374 node = *rnode; 1375 sc = (struct dbcool_softc *)node.sysctl_data; 1376 chipreg = node.sysctl_num & 0x7f; 1377 1378 /* retrieve 4-bit value */ 1379 newreg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1380 if ((node.sysctl_num & 0x80) == 0) 1381 reg = newreg >> 4; 1382 else 1383 reg = newreg; 1384 reg = reg & 0x0f; 1385 1386 node.sysctl_data = ® 1387 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1388 1389 if (error || newp == NULL) 1390 return error; 1391 1392 /* We were asked to update the value - sanity check before writing */ 1393 newhyst = *(int *)node.sysctl_data; 1394 if (newhyst > 0x0f) 1395 return EINVAL; 1396 1397 /* Insert new value into field and update register */ 1398 if ((node.sysctl_num & 0x80) == 0) { 1399 newreg &= 0x0f; 1400 newreg |= (newhyst << 4); 1401 } else { 1402 newreg &= 0xf0; 1403 newreg |= newhyst; 1404 } 1405 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1406 return 0; 1407 } 1408 1409 #ifdef DBCOOL_DEBUG 1410 1411 /* 1412 * These routines can be used for debugging. reg_select is used to 1413 * select any arbitrary register in the device. reg_access is used 1414 * to read (and optionally update) the selected register. 1415 * 1416 * No attempt is made to validate the data passed. If you use these 1417 * routines, you are assumed to know what you're doing! 1418 * 1419 * Caveat user 1420 */ 1421 static int 1422 sysctl_dbcool_reg_select(SYSCTLFN_ARGS) 1423 { 1424 struct sysctlnode node; 1425 struct dbcool_softc *sc; 1426 int reg, error; 1427 1428 node = *rnode; 1429 sc = (struct dbcool_softc *)node.sysctl_data; 1430 1431 reg = sc->sc_user_reg; 1432 node.sysctl_data = ® 1433 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1434 1435 if (error || newp == NULL) 1436 return error; 1437 1438 sc->sc_user_reg = *(int *)node.sysctl_data; 1439 return 0; 1440 } 1441 1442 static int 1443 sysctl_dbcool_reg_access(SYSCTLFN_ARGS) 1444 { 1445 struct sysctlnode node; 1446 struct dbcool_softc *sc; 1447 int reg, error; 1448 uint8_t chipreg; 1449 uint8_t newreg; 1450 1451 node = *rnode; 1452 sc = (struct dbcool_softc *)node.sysctl_data; 1453 chipreg = sc->sc_user_reg; 1454 1455 reg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1456 node.sysctl_data = ® 1457 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1458 1459 if (error || newp == NULL) 1460 return error; 1461 1462 newreg = *(int *)node.sysctl_data; 1463 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1464 return 0; 1465 } 1466 #endif /* DBCOOL_DEBUG */ 1467 1468 /* 1469 * Encode an index number and register number for use as a sysctl_num 1470 * so we can select the correct device register later. 1471 */ 1472 #define DBC_PWM_SYSCTL(seq, reg) ((seq << 8) | reg) 1473 1474 void 1475 dbcool_setup(device_t self) 1476 { 1477 struct dbcool_softc *sc = device_private(self); 1478 const struct sysctlnode *me = NULL; 1479 #ifdef DBCOOL_DEBUG 1480 struct sysctlnode *node = NULL; 1481 #endif 1482 uint8_t cfg_val, cfg_reg; 1483 int ret, error; 1484 1485 /* 1486 * Some chips are capable of reporting an extended temperature range 1487 * by default. On these models, config register 5 bit 0 can be set 1488 * to 1 for compatability with other chips that report 2s complement. 1489 */ 1490 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) { 1491 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADT7466_CONFIG1) & 0x80) 1492 sc->sc_temp_offset = 64; 1493 else 1494 sc->sc_temp_offset = 0; 1495 } else if (sc->sc_dc.dc_chip->flags & DBCFLAG_TEMPOFFSET) { 1496 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_CONFIG5_REG) & 1497 DBCOOL_CFG5_TWOSCOMP) 1498 sc->sc_temp_offset = 0; 1499 else 1500 sc->sc_temp_offset = 64; 1501 } else 1502 sc->sc_temp_offset = 0; 1503 1504 /* Determine Vcc for this chip */ 1505 sc->sc_supply_voltage = dbcool_supply_voltage(sc); 1506 1507 ret = sysctl_createv(NULL, 0, NULL, &me, 1508 CTLFLAG_READWRITE, 1509 CTLTYPE_NODE, device_xname(self), NULL, 1510 NULL, 0, NULL, 0, 1511 CTL_HW, CTL_CREATE, CTL_EOL); 1512 if (ret == 0) 1513 sc->sc_root_sysctl_num = me->sysctl_num; 1514 else 1515 sc->sc_root_sysctl_num = 0; 1516 1517 aprint_debug_dev(self, 1518 "Supply voltage %"PRId64".%06"PRId64"V, %s temp range\n", 1519 sc->sc_supply_voltage / 1000000, 1520 sc->sc_supply_voltage % 1000000, 1521 sc->sc_temp_offset ? "extended" : "normal"); 1522 1523 /* Create the sensors for this device */ 1524 sc->sc_sme = sysmon_envsys_create(); 1525 if (dbcool_setup_sensors(sc)) 1526 goto out; 1527 1528 if (sc->sc_root_sysctl_num != 0) { 1529 /* If supported, create sysctl tree for fan PWM controllers */ 1530 if (sc->sc_dc.dc_chip->power != NULL) 1531 dbcool_setup_controllers(sc); 1532 1533 #ifdef DBCOOL_DEBUG 1534 ret = sysctl_createv(NULL, 0, NULL, 1535 (const struct sysctlnode **)&node, 1536 CTLFLAG_READWRITE, CTLTYPE_INT, "reg_select", NULL, 1537 sysctl_dbcool_reg_select, 1538 0, sc, sizeof(int), 1539 CTL_HW, me->sysctl_num, CTL_CREATE, CTL_EOL); 1540 if (node != NULL) 1541 node->sysctl_data = sc; 1542 1543 ret = sysctl_createv(NULL, 0, NULL, 1544 (const struct sysctlnode **)&node, 1545 CTLFLAG_READWRITE, CTLTYPE_INT, "reg_access", NULL, 1546 sysctl_dbcool_reg_access, 1547 0, sc, sizeof(int), 1548 CTL_HW, me->sysctl_num, CTL_CREATE, CTL_EOL); 1549 if (node != NULL) 1550 node->sysctl_data = sc; 1551 #endif /* DBCOOL_DEBUG */ 1552 } 1553 1554 /* 1555 * Read and rewrite config register to activate device 1556 */ 1557 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 1558 cfg_reg = DBCOOL_ADM1030_CFG1; 1559 else if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) 1560 cfg_reg = DBCOOL_ADT7466_CONFIG1; 1561 else 1562 cfg_reg = DBCOOL_CONFIG1_REG; 1563 cfg_val = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_CONFIG1_REG); 1564 if ((cfg_val & DBCOOL_CFG1_START) == 0) { 1565 cfg_val |= DBCOOL_CFG1_START; 1566 sc->sc_dc.dc_writereg(&sc->sc_dc, cfg_reg, cfg_val); 1567 } 1568 if (dbcool_islocked(sc)) 1569 aprint_normal_dev(self, "configuration locked\n"); 1570 1571 sc->sc_sme->sme_name = device_xname(self); 1572 sc->sc_sme->sme_cookie = sc; 1573 sc->sc_sme->sme_refresh = dbcool_refresh; 1574 sc->sc_sme->sme_set_limits = dbcool_set_limits; 1575 sc->sc_sme->sme_get_limits = dbcool_get_limits; 1576 1577 if ((error = sysmon_envsys_register(sc->sc_sme)) != 0) { 1578 aprint_error_dev(self, 1579 "unable to register with sysmon (%d)\n", error); 1580 goto out; 1581 } 1582 1583 return; 1584 1585 out: 1586 sysmon_envsys_destroy(sc->sc_sme); 1587 } 1588 1589 static int 1590 dbcool_setup_sensors(struct dbcool_softc *sc) 1591 { 1592 int i; 1593 int error = 0; 1594 uint8_t vid_reg, vid_val; 1595 struct chip_id *chip = sc->sc_dc.dc_chip; 1596 1597 for (i=0; chip->table[i].type != DBC_EOF; i++) { 1598 if (i < DBCOOL_MAXSENSORS) 1599 sc->sc_sysctl_num[i] = -1; 1600 else if (chip->table[i].type != DBC_CTL) { 1601 aprint_normal_dev(sc->sc_dev, "chip table too big!\n"); 1602 break; 1603 } 1604 switch (chip->table[i].type) { 1605 case DBC_TEMP: 1606 sc->sc_sensor[i].units = ENVSYS_STEMP; 1607 sc->sc_sensor[i].state = ENVSYS_SINVALID; 1608 sc->sc_sensor[i].flags |= ENVSYS_FMONLIMITS; 1609 error = dbcool_attach_sensor(sc, i); 1610 break; 1611 case DBC_VOLT: 1612 /* 1613 * If 12V-In pin has been reconfigured as 6th bit 1614 * of VID code, don't create a 12V-In sensor 1615 */ 1616 if ((chip->flags & DBCFLAG_HAS_VID_SEL) && 1617 (chip->table[i].reg.val_reg == DBCOOL_12VIN) && 1618 (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VID_REG) & 1619 0x80)) 1620 break; 1621 1622 sc->sc_sensor[i].units = ENVSYS_SVOLTS_DC; 1623 sc->sc_sensor[i].state = ENVSYS_SINVALID; 1624 sc->sc_sensor[i].flags |= ENVSYS_FMONLIMITS; 1625 error = dbcool_attach_sensor(sc, i); 1626 break; 1627 case DBC_FAN: 1628 sc->sc_sensor[i].units = ENVSYS_SFANRPM; 1629 sc->sc_sensor[i].state = ENVSYS_SINVALID; 1630 sc->sc_sensor[i].flags |= ENVSYS_FMONLIMITS; 1631 error = dbcool_attach_sensor(sc, i); 1632 break; 1633 case DBC_VID: 1634 sc->sc_sensor[i].units = ENVSYS_INTEGER; 1635 sc->sc_sensor[i].state = ENVSYS_SINVALID; 1636 sc->sc_sensor[i].flags |= ENVSYS_FMONNOTSUPP; 1637 1638 /* retrieve 5- or 6-bit value */ 1639 vid_reg = chip->table[i].reg.val_reg; 1640 vid_val = sc->sc_dc.dc_readreg(&sc->sc_dc, vid_reg); 1641 if (chip->flags & DBCFLAG_HAS_VID_SEL) 1642 vid_val &= 0x3f; 1643 else 1644 vid_val &= 0x1f; 1645 sc->sc_sensor[i].value_cur = vid_val; 1646 1647 error = dbcool_attach_sensor(sc, i); 1648 break; 1649 case DBC_CTL: 1650 error = dbcool_attach_temp_control(sc, i, chip); 1651 if (error) { 1652 aprint_error_dev(sc->sc_dev, 1653 "attach index %d failed %d\n", 1654 i, error); 1655 error = 0; 1656 } 1657 break; 1658 default: 1659 aprint_error_dev(sc->sc_dev, 1660 "sensor_table index %d has bad type %d\n", 1661 i, chip->table[i].type); 1662 break; 1663 } 1664 if (error) 1665 break; 1666 } 1667 return error; 1668 } 1669 1670 static int 1671 dbcool_attach_sensor(struct dbcool_softc *sc, int idx) 1672 { 1673 int name_index; 1674 int error = 0; 1675 1676 name_index = sc->sc_dc.dc_chip->table[idx].name_index; 1677 strlcpy(sc->sc_sensor[idx].desc, dbc_sensor_names[name_index], 1678 sizeof(sc->sc_sensor[idx].desc)); 1679 sc->sc_regs[idx] = &sc->sc_dc.dc_chip->table[idx].reg; 1680 sc->sc_nom_volt[idx] = sc->sc_dc.dc_chip->table[idx].nom_volt_index; 1681 1682 error = sysmon_envsys_sensor_attach(sc->sc_sme, &sc->sc_sensor[idx]); 1683 return error; 1684 } 1685 1686 static int 1687 dbcool_attach_temp_control(struct dbcool_softc *sc, int idx, 1688 struct chip_id *chip) 1689 { 1690 const struct sysctlnode *me2 = NULL, *node; 1691 int j, ret, sysctl_index, rw_flag; 1692 uint8_t sysctl_reg; 1693 char name[SYSCTL_NAMELEN]; 1694 1695 /* Search for the corresponding temp sensor */ 1696 for (j = 0; j < idx; j++) { 1697 if (j >= DBCOOL_MAXSENSORS || chip->table[j].type != DBC_TEMP) 1698 continue; 1699 if (chip->table[j].name_index == chip->table[idx].name_index) 1700 break; 1701 } 1702 if (j >= idx) /* Temp sensor not found */ 1703 return ENOENT; 1704 1705 /* create sysctl node for the sensor if not one already there */ 1706 if (sc->sc_sysctl_num[j] == -1) { 1707 ret = sysctl_createv(NULL, 0, NULL, &me2, CTLFLAG_READWRITE, 1708 CTLTYPE_NODE, sc->sc_sensor[j].desc, NULL, 1709 NULL, 0, NULL, 0, 1710 CTL_HW, sc->sc_root_sysctl_num, CTL_CREATE, 1711 CTL_EOL); 1712 if (me2 != NULL) 1713 sc->sc_sysctl_num[j] = me2->sysctl_num; 1714 else 1715 return ret; 1716 } 1717 /* add sysctl leaf node for this control variable */ 1718 sysctl_index = chip->table[idx].sysctl_index; 1719 sysctl_reg = chip->table[idx].reg.val_reg; 1720 strlcpy(name, dbc_sysctl_table[sysctl_index].name, sizeof(name)); 1721 if (dbc_sysctl_table[sysctl_index].lockable && dbcool_islocked(sc)) 1722 rw_flag = CTLFLAG_READONLY | CTLFLAG_OWNDESC; 1723 else 1724 rw_flag = CTLFLAG_READWRITE | CTLFLAG_OWNDESC; 1725 1726 ret = sysctl_createv(NULL, 0, NULL, 1727 &node, rw_flag, 1728 CTLTYPE_INT, name, 1729 SYSCTL_DESCR(dbc_sysctl_table[sysctl_index].desc), 1730 dbc_sysctl_table[sysctl_index].helper, 1731 0, sc, sizeof(int), 1732 CTL_HW, sc->sc_root_sysctl_num, 1733 sc->sc_sysctl_num[j], 1734 DBC_PWM_SYSCTL(idx, sysctl_reg), CTL_EOL); 1735 1736 return ret; 1737 } 1738 1739 static void 1740 dbcool_setup_controllers(struct dbcool_softc *sc) 1741 { 1742 int i, j, ret, rw_flag; 1743 uint8_t sysctl_reg; 1744 struct chip_id *chip = sc->sc_dc.dc_chip; 1745 const struct sysctlnode *me2 = NULL; 1746 const struct sysctlnode *node = NULL; 1747 char name[SYSCTL_NAMELEN]; 1748 1749 for (i = 0; chip->power[i].desc != NULL; i++) { 1750 snprintf(name, sizeof(name), "fan_ctl_%d", i); 1751 ret = sysctl_createv(NULL, 0, NULL, &me2, 1752 CTLFLAG_READWRITE | CTLFLAG_OWNDESC, 1753 CTLTYPE_NODE, name, NULL, 1754 NULL, 0, NULL, 0, 1755 CTL_HW, sc->sc_root_sysctl_num, CTL_CREATE, CTL_EOL); 1756 1757 for (j = DBC_PWM_BEHAVIOR; j < DBC_PWM_LAST_PARAM; j++) { 1758 if (j == DBC_PWM_MAX_DUTY && 1759 (chip->flags & DBCFLAG_HAS_MAXDUTY) == 0) 1760 continue; 1761 sysctl_reg = chip->power[i].power_regs[j]; 1762 if (sysctl_reg == DBCOOL_NO_REG) 1763 continue; 1764 strlcpy(name, dbc_sysctl_table[j].name, sizeof(name)); 1765 if (dbc_sysctl_table[j].lockable && dbcool_islocked(sc)) 1766 rw_flag = CTLFLAG_READONLY | CTLFLAG_OWNDESC; 1767 else 1768 rw_flag = CTLFLAG_READWRITE | CTLFLAG_OWNDESC; 1769 ret = sysctl_createv(NULL, 0, NULL, 1770 &node, rw_flag, 1771 (j == DBC_PWM_BEHAVIOR)? 1772 CTLTYPE_STRING:CTLTYPE_INT, 1773 name, 1774 SYSCTL_DESCR(dbc_sysctl_table[j].desc), 1775 dbc_sysctl_table[j].helper, 1776 0, sc, 1777 ( j == DBC_PWM_BEHAVIOR)? 1778 sizeof(dbcool_cur_behav): sizeof(int), 1779 CTL_HW, sc->sc_root_sysctl_num, me2->sysctl_num, 1780 DBC_PWM_SYSCTL(j, sysctl_reg), CTL_EOL); 1781 } 1782 } 1783 } 1784 1785 static void 1786 dbcool_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 1787 { 1788 struct dbcool_softc *sc=sme->sme_cookie; 1789 int i, nom_volt_idx, cur; 1790 struct reg_list *reg; 1791 1792 i = edata->sensor; 1793 reg = sc->sc_regs[i]; 1794 1795 edata->state = ENVSYS_SVALID; 1796 switch (edata->units) 1797 { 1798 case ENVSYS_STEMP: 1799 cur = dbcool_read_temp(sc, reg->val_reg, true); 1800 break; 1801 case ENVSYS_SVOLTS_DC: 1802 nom_volt_idx = sc->sc_nom_volt[i]; 1803 cur = dbcool_read_volt(sc, reg->val_reg, nom_volt_idx, 1804 true); 1805 break; 1806 case ENVSYS_SFANRPM: 1807 cur = dbcool_read_rpm(sc, reg->val_reg); 1808 break; 1809 case ENVSYS_INTEGER: 1810 return; 1811 default: 1812 edata->state = ENVSYS_SINVALID; 1813 return; 1814 } 1815 1816 if (cur == 0 && (edata->units != ENVSYS_SFANRPM)) 1817 edata->state = ENVSYS_SINVALID; 1818 1819 /* 1820 * If fan is "stalled" but has no low limit, treat 1821 * it as though the fan is not installed. 1822 */ 1823 else if (edata->units == ENVSYS_SFANRPM && cur == 0 && 1824 !(edata->upropset & (PROP_CRITMIN | PROP_WARNMIN))) 1825 edata->state = ENVSYS_SINVALID; 1826 1827 edata->value_cur = cur; 1828 } 1829 1830 int 1831 dbcool_chip_ident(struct dbcool_chipset *dc) 1832 { 1833 /* verify this is a supported dbCool chip */ 1834 uint8_t c_id, d_id, r_id; 1835 int i; 1836 1837 c_id = dc->dc_readreg(dc, DBCOOL_COMPANYID_REG); 1838 d_id = dc->dc_readreg(dc, DBCOOL_DEVICEID_REG); 1839 r_id = dc->dc_readreg(dc, DBCOOL_REVISION_REG); 1840 1841 /* The EMC6D103S only supports read_byte and since dc->dc_chip is 1842 * NULL when we call dc->dc_readreg above we use 1843 * send_byte/receive_byte which doesn't work. 1844 * 1845 * So if we only get 0's back then try again with dc->dc_chip 1846 * set to the EMC6D103S_DEVICEID and which doesn't have 1847 * DBCFLAG_NO_READBYTE set so read_byte will be used 1848 */ 1849 if ((c_id == 0) && (d_id == 0) && (r_id == 0)) { 1850 for (i = 0; chip_table[i].company != 0; i++) 1851 if ((SMSC_COMPANYID == chip_table[i].company) && 1852 (EMC6D103S_DEVICEID == chip_table[i].device)) { 1853 dc->dc_chip = &chip_table[i]; 1854 break; 1855 } 1856 c_id = dc->dc_readreg(dc, DBCOOL_COMPANYID_REG); 1857 d_id = dc->dc_readreg(dc, DBCOOL_DEVICEID_REG); 1858 r_id = dc->dc_readreg(dc, DBCOOL_REVISION_REG); 1859 } 1860 1861 for (i = 0; chip_table[i].company != 0; i++) 1862 if ((c_id == chip_table[i].company) && 1863 (d_id == chip_table[i].device || 1864 chip_table[i].device == 0xff) && 1865 (r_id == chip_table[i].rev || 1866 chip_table[i].rev == 0xff)) { 1867 dc->dc_chip = &chip_table[i]; 1868 return i; 1869 } 1870 1871 aprint_verbose("dbcool_chip_ident: addr 0x%02x c_id 0x%02x d_id 0x%02x" 1872 " r_id 0x%02x: No match.\n", dc->dc_addr, c_id, d_id, 1873 r_id); 1874 1875 return -1; 1876 } 1877 1878 /* 1879 * Retrieve sensor limits from the chip registers 1880 */ 1881 static void 1882 dbcool_get_limits(struct sysmon_envsys *sme, envsys_data_t *edata, 1883 sysmon_envsys_lim_t *limits, uint32_t *props) 1884 { 1885 int index = edata->sensor; 1886 struct dbcool_softc *sc = sme->sme_cookie; 1887 1888 *props &= ~(PROP_CRITMIN | PROP_CRITMAX); 1889 switch (edata->units) { 1890 case ENVSYS_STEMP: 1891 dbcool_get_temp_limits(sc, index, limits, props); 1892 break; 1893 case ENVSYS_SVOLTS_DC: 1894 dbcool_get_volt_limits(sc, index, limits, props); 1895 break; 1896 case ENVSYS_SFANRPM: 1897 dbcool_get_fan_limits(sc, index, limits, props); 1898 1899 /* FALLTHROUGH */ 1900 default: 1901 break; 1902 } 1903 *props &= ~PROP_DRIVER_LIMITS; 1904 1905 /* If both limits provided, make sure they're sane */ 1906 if ((*props & PROP_CRITMIN) && 1907 (*props & PROP_CRITMAX) && 1908 (limits->sel_critmin >= limits->sel_critmax)) 1909 *props &= ~(PROP_CRITMIN | PROP_CRITMAX); 1910 1911 /* 1912 * If this is the first time through, save these values 1913 * in case user overrides them and then requests a reset. 1914 */ 1915 if (sc->sc_defprops[index] == 0) { 1916 sc->sc_defprops[index] = *props | PROP_DRIVER_LIMITS; 1917 sc->sc_deflims[index] = *limits; 1918 } 1919 } 1920 1921 static void 1922 dbcool_get_temp_limits(struct dbcool_softc *sc, int idx, 1923 sysmon_envsys_lim_t *lims, uint32_t *props) 1924 { 1925 struct reg_list *reg = sc->sc_regs[idx]; 1926 uint8_t lo_lim, hi_lim; 1927 1928 lo_lim = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->lo_lim_reg); 1929 hi_lim = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->hi_lim_reg); 1930 1931 if (sc->sc_temp_offset) { 1932 if (lo_lim > 0x01) { 1933 lims->sel_critmin = lo_lim - sc->sc_temp_offset; 1934 *props |= PROP_CRITMIN; 1935 } 1936 if (hi_lim != 0xff) { 1937 lims->sel_critmax = hi_lim - sc->sc_temp_offset; 1938 *props |= PROP_CRITMAX; 1939 } 1940 } else { 1941 if (lo_lim != 0x80 && lo_lim != 0x81) { 1942 lims->sel_critmin = (int8_t)lo_lim; 1943 *props |= PROP_CRITMIN; 1944 } 1945 1946 if (hi_lim != 0x7f) { 1947 lims->sel_critmax = (int8_t)hi_lim; 1948 *props |= PROP_CRITMAX; 1949 } 1950 } 1951 1952 /* Convert temp limits to microKelvin */ 1953 lims->sel_critmin *= 1000000; 1954 lims->sel_critmin += 273150000; 1955 lims->sel_critmax *= 1000000; 1956 lims->sel_critmax += 273150000; 1957 } 1958 1959 static void 1960 dbcool_get_volt_limits(struct dbcool_softc *sc, int idx, 1961 sysmon_envsys_lim_t *lims, uint32_t *props) 1962 { 1963 struct reg_list *reg = sc->sc_regs[idx]; 1964 int64_t limit; 1965 int nom; 1966 1967 nom = nominal_voltages[sc->sc_dc.dc_chip->table[idx].nom_volt_index]; 1968 if (nom < 0) 1969 nom = dbcool_supply_voltage(sc); 1970 nom *= 1000000; /* scale for microvolts */ 1971 1972 limit = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->lo_lim_reg); 1973 if (limit != 0x00 && limit != 0xff) { 1974 limit *= nom; 1975 limit /= 0xc0; 1976 lims->sel_critmin = limit; 1977 *props |= PROP_CRITMIN; 1978 } 1979 limit = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->hi_lim_reg); 1980 if (limit != 0x00 && limit != 0xff) { 1981 limit *= nom; 1982 limit /= 0xc0; 1983 lims->sel_critmax = limit; 1984 *props |= PROP_CRITMAX; 1985 } 1986 } 1987 1988 static void 1989 dbcool_get_fan_limits(struct dbcool_softc *sc, int idx, 1990 sysmon_envsys_lim_t *lims, uint32_t *props) 1991 { 1992 struct reg_list *reg = sc->sc_regs[idx]; 1993 int32_t limit; 1994 1995 limit = dbcool_read_rpm(sc, reg->lo_lim_reg); 1996 if (limit) { 1997 lims->sel_critmin = limit; 1998 *props |= PROP_CRITMIN; 1999 } 2000 } 2001 2002 /* 2003 * Update sensor limits in the chip registers 2004 */ 2005 static void 2006 dbcool_set_limits(struct sysmon_envsys *sme, envsys_data_t *edata, 2007 sysmon_envsys_lim_t *limits, uint32_t *props) 2008 { 2009 int index = edata->sensor; 2010 struct dbcool_softc *sc = sme->sme_cookie; 2011 2012 if (limits == NULL) { 2013 limits = &sc->sc_deflims[index]; 2014 props = &sc->sc_defprops[index]; 2015 } 2016 switch (edata->units) { 2017 case ENVSYS_STEMP: 2018 dbcool_set_temp_limits(sc, index, limits, props); 2019 break; 2020 case ENVSYS_SVOLTS_DC: 2021 dbcool_set_volt_limits(sc, index, limits, props); 2022 break; 2023 case ENVSYS_SFANRPM: 2024 dbcool_set_fan_limits(sc, index, limits, props); 2025 2026 /* FALLTHROUGH */ 2027 default: 2028 break; 2029 } 2030 *props &= ~PROP_DRIVER_LIMITS; 2031 } 2032 2033 static void 2034 dbcool_set_temp_limits(struct dbcool_softc *sc, int idx, 2035 sysmon_envsys_lim_t *lims, uint32_t *props) 2036 { 2037 struct reg_list *reg = sc->sc_regs[idx]; 2038 int32_t limit; 2039 2040 if (*props & PROP_CRITMIN) { 2041 limit = lims->sel_critmin - 273150000; 2042 limit /= 1000000; 2043 if (sc->sc_temp_offset) { 2044 limit += sc->sc_temp_offset; 2045 if (limit < 0) 2046 limit = 0; 2047 else if (limit > 255) 2048 limit = 255; 2049 } else { 2050 if (limit < -127) 2051 limit = -127; 2052 else if (limit > 127) 2053 limit = 127; 2054 } 2055 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, 2056 (uint8_t)limit); 2057 } else if (*props & PROP_DRIVER_LIMITS) { 2058 if (sc->sc_temp_offset) 2059 limit = 0x00; 2060 else 2061 limit = 0x80; 2062 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, 2063 (uint8_t)limit); 2064 } 2065 2066 if (*props & PROP_CRITMAX) { 2067 limit = lims->sel_critmax - 273150000; 2068 limit /= 1000000; 2069 if (sc->sc_temp_offset) { 2070 limit += sc->sc_temp_offset; 2071 if (limit < 0) 2072 limit = 0; 2073 else if (limit > 255) 2074 limit = 255; 2075 } else { 2076 if (limit < -127) 2077 limit = -127; 2078 else if (limit > 127) 2079 limit = 127; 2080 } 2081 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg, 2082 (uint8_t)limit); 2083 } else if (*props & PROP_DRIVER_LIMITS) { 2084 if (sc->sc_temp_offset) 2085 limit = 0xff; 2086 else 2087 limit = 0x7f; 2088 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg, 2089 (uint8_t)limit); 2090 } 2091 } 2092 2093 static void 2094 dbcool_set_volt_limits(struct dbcool_softc *sc, int idx, 2095 sysmon_envsys_lim_t *lims, uint32_t *props) 2096 { 2097 struct reg_list *reg = sc->sc_regs[idx]; 2098 int64_t limit; 2099 int nom; 2100 2101 nom = nominal_voltages[sc->sc_dc.dc_chip->table[idx].nom_volt_index]; 2102 if (nom < 0) 2103 nom = dbcool_supply_voltage(sc); 2104 nom *= 1000000; /* scale for microvolts */ 2105 2106 if (*props & PROP_CRITMIN) { 2107 limit = lims->sel_critmin; 2108 limit *= 0xc0; 2109 limit /= nom; 2110 if (limit > 0xff) 2111 limit = 0xff; 2112 else if (limit < 0) 2113 limit = 0; 2114 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, limit); 2115 } else if (*props & PROP_DRIVER_LIMITS) 2116 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, 0); 2117 2118 if (*props & PROP_CRITMAX) { 2119 limit = lims->sel_critmax; 2120 limit *= 0xc0; 2121 limit /= nom; 2122 if (limit > 0xff) 2123 limit = 0xff; 2124 else if (limit < 0) 2125 limit = 0; 2126 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg, limit); 2127 } else if (*props & PROP_DRIVER_LIMITS) 2128 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg, 0xff); 2129 } 2130 2131 static void 2132 dbcool_set_fan_limits(struct dbcool_softc *sc, int idx, 2133 sysmon_envsys_lim_t *lims, uint32_t *props) 2134 { 2135 struct reg_list *reg = sc->sc_regs[idx]; 2136 int32_t limit, dividend; 2137 2138 if (*props & PROP_CRITMIN) { 2139 limit = lims->sel_critmin; 2140 if (limit == 0) 2141 limit = 0xffff; 2142 else { 2143 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 2144 dividend = 11250 * 60; 2145 else 2146 dividend = 90000 * 60; 2147 limit = limit / dividend; 2148 if (limit > 0xffff) 2149 limit = 0xffff; 2150 } 2151 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, 2152 limit & 0xff); 2153 limit >>= 8; 2154 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg + 1, 2155 limit & 0xff); 2156 } else if (*props & PROP_DRIVER_LIMITS) { 2157 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, 0xff); 2158 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg + 1, 0xff); 2159 } 2160 } 2161 2162 MODULE(MODULE_CLASS_DRIVER, dbcool, NULL); 2163 2164 #ifdef _MODULE 2165 #include "ioconf.c" 2166 #endif 2167 2168 static int 2169 dbcool_modcmd(modcmd_t cmd, void *opaque) 2170 { 2171 int error = 0; 2172 2173 switch (cmd) { 2174 case MODULE_CMD_INIT: 2175 #ifdef _MODULE 2176 error = config_init_component(cfdriver_ioconf_dbcool, 2177 cfattach_ioconf_dbcool, cfdata_ioconf_dbcool); 2178 #endif 2179 return error; 2180 case MODULE_CMD_FINI: 2181 #ifdef _MODULE 2182 error = config_fini_component(cfdriver_ioconf_dbcool, 2183 cfattach_ioconf_dbcool, cfdata_ioconf_dbcool); 2184 #endif 2185 return error; 2186 default: 2187 return ENOTTY; 2188 } 2189 } 2190
Indexes created Sat Sep 27 22:09:54 GMT 2025