dbcool.c revision 1.38
1 /* $NetBSD: dbcool.c,v 1.38 2012/06/02 21:36:44 dsl Exp $ */ 2 3 /*- 4 * Copyright (c) 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Goyette 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * a driver for the dbCool(tm) family of environmental controllers 34 * 35 * Data sheets for the various supported chips are available at 36 * 37 * http://www.onsemi.com/pub/Collateral/ADM1027-D.PDF 38 * http://www.onsemi.com/pub/Collateral/ADM1030-D.PDF 39 * http://www.onsemi.com/pub/Collateral/ADT7463-D.PDF 40 * http://www.onsemi.com/pub/Collateral/ADT7466.PDF 41 * http://www.onsemi.com/pub/Collateral/ADT7467-D.PDF 42 * http://www.onsemi.com/pub/Collateral/ADT7468-D.PDF 43 * http://www.onsemi.com/pub/Collateral/ADT7473-D.PDF 44 * http://www.onsemi.com/pub/Collateral/ADT7475-D.PDF 45 * http://www.onsemi.com/pub/Collateral/ADT7476-D.PDF 46 * http://www.onsemi.com/pub/Collateral/ADT7490-D.PDF 47 * http://www.smsc.com/media/Downloads_Public/Data_Sheets/6d103s.pdf 48 * 49 * (URLs are correct as of October 5, 2008) 50 */ 51 52 #include <sys/cdefs.h> 53 __KERNEL_RCSID(0, "$NetBSD: dbcool.c,v 1.38 2012/06/02 21:36:44 dsl Exp $"); 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/kernel.h> 58 #include <sys/device.h> 59 #include <sys/malloc.h> 60 #include <sys/sysctl.h> 61 #include <sys/module.h> 62 63 #include <dev/i2c/dbcool_var.h> 64 #include <dev/i2c/dbcool_reg.h> 65 66 /* Config interface */ 67 static int dbcool_match(device_t, cfdata_t, void *); 68 static void dbcool_attach(device_t, device_t, void *); 69 static int dbcool_detach(device_t, int); 70 71 /* Device attributes */ 72 static int dbcool_supply_voltage(struct dbcool_softc *); 73 static bool dbcool_islocked(struct dbcool_softc *); 74 75 /* Sensor read functions */ 76 static void dbcool_refresh(struct sysmon_envsys *, envsys_data_t *); 77 static int dbcool_read_rpm(struct dbcool_softc *, uint8_t); 78 static int dbcool_read_temp(struct dbcool_softc *, uint8_t, bool); 79 static int dbcool_read_volt(struct dbcool_softc *, uint8_t, int, bool); 80 81 /* Sensor get/set limit functions */ 82 static void dbcool_get_limits(struct sysmon_envsys *, envsys_data_t *, 83 sysmon_envsys_lim_t *, uint32_t *); 84 static void dbcool_get_temp_limits(struct dbcool_softc *, int, 85 sysmon_envsys_lim_t *, uint32_t *); 86 static void dbcool_get_volt_limits(struct dbcool_softc *, int, 87 sysmon_envsys_lim_t *, uint32_t *); 88 static void dbcool_get_fan_limits(struct dbcool_softc *, int, 89 sysmon_envsys_lim_t *, uint32_t *); 90 91 static void dbcool_set_limits(struct sysmon_envsys *, envsys_data_t *, 92 sysmon_envsys_lim_t *, uint32_t *); 93 static void dbcool_set_temp_limits(struct dbcool_softc *, int, 94 sysmon_envsys_lim_t *, uint32_t *); 95 static void dbcool_set_volt_limits(struct dbcool_softc *, int, 96 sysmon_envsys_lim_t *, uint32_t *); 97 static void dbcool_set_fan_limits(struct dbcool_softc *, int, 98 sysmon_envsys_lim_t *, uint32_t *); 99 100 /* SYSCTL Helpers */ 101 SYSCTL_SETUP_PROTO(sysctl_dbcoolsetup); 102 static int sysctl_dbcool_temp(SYSCTLFN_PROTO); 103 static int sysctl_adm1030_temp(SYSCTLFN_PROTO); 104 static int sysctl_adm1030_trange(SYSCTLFN_PROTO); 105 static int sysctl_dbcool_duty(SYSCTLFN_PROTO); 106 static int sysctl_dbcool_behavior(SYSCTLFN_PROTO); 107 static int sysctl_dbcool_slope(SYSCTLFN_PROTO); 108 static int sysctl_dbcool_thyst(SYSCTLFN_PROTO); 109 110 /* Set-up subroutines */ 111 static void dbcool_setup_controllers(struct dbcool_softc *); 112 static int dbcool_setup_sensors(struct dbcool_softc *); 113 static int dbcool_attach_sensor(struct dbcool_softc *, int); 114 static int dbcool_attach_temp_control(struct dbcool_softc *, int, 115 struct chip_id *); 116 117 #ifdef DBCOOL_DEBUG 118 static int sysctl_dbcool_reg_select(SYSCTLFN_PROTO); 119 static int sysctl_dbcool_reg_access(SYSCTLFN_PROTO); 120 #endif /* DBCOOL_DEBUG */ 121 122 /* 123 * Descriptions for SYSCTL entries 124 */ 125 struct dbc_sysctl_info { 126 const char *name; 127 const char *desc; 128 bool lockable; 129 int (*helper)(SYSCTLFN_PROTO); 130 }; 131 132 static struct dbc_sysctl_info dbc_sysctl_table[] = { 133 /* 134 * The first several entries must remain in the same order as the 135 * corresponding entries in enum dbc_pwm_params 136 */ 137 { "behavior", "operating behavior and temp selector", 138 true, sysctl_dbcool_behavior }, 139 { "min_duty", "minimum fan controller PWM duty cycle", 140 true, sysctl_dbcool_duty }, 141 { "max_duty", "maximum fan controller PWM duty cycle", 142 true, sysctl_dbcool_duty }, 143 { "cur_duty", "current fan controller PWM duty cycle", 144 false, sysctl_dbcool_duty }, 145 146 /* 147 * The rest of these should be in the order in which they 148 * are to be stored in the sysctl tree; the table index is 149 * used as the high-order bits of the sysctl_num to maintain 150 * the sequence. 151 * 152 * If you rearrange the order of these items, be sure to 153 * update the sysctl_index in the XXX_sensor_table[] for 154 * the various chips! 155 */ 156 { "Trange", "temp slope/range to reach 100% duty cycle", 157 true, sysctl_dbcool_slope }, 158 { "Tmin", "temp at which to start fan controller", 159 true, sysctl_dbcool_temp }, 160 { "Ttherm", "temp at which THERM is asserted", 161 true, sysctl_dbcool_temp }, 162 { "Thyst", "temp hysteresis for stopping fan controller", 163 true, sysctl_dbcool_thyst }, 164 { "Tmin", "temp at which to start fan controller", 165 true, sysctl_adm1030_temp }, 166 { "Trange", "temp slope/range to reach 100% duty cycle", 167 true, sysctl_adm1030_trange }, 168 }; 169 170 static const char *dbc_sensor_names[] = { 171 "l_temp", "r1_temp", "r2_temp", "Vccp", "Vcc", "fan1", 172 "fan2", "fan3", "fan4", "AIN1", "AIN2", "V2dot5", 173 "V5", "V12", "Vtt", "Imon", "VID" 174 }; 175 176 /* 177 * Following table derived from product data-sheets 178 */ 179 static int64_t nominal_voltages[] = { 180 -1, /* Vcc can be either 3.3 or 5.0V 181 at 3/4 scale */ 182 2249939, /* Vccp 2.25V 3/4 scale */ 183 2497436, /* 2.5VIN 2.5V 3/4 scale */ 184 5002466, /* 5VIN 5V 3/4 scale */ 185 12000000, /* 12VIN 12V 3/4 scale */ 186 1690809, /* Vtt, Imon 2.25V full scale */ 187 1689600, /* AIN1, AIN2 2.25V full scale */ 188 0 189 }; 190 191 /* 192 * Sensor-type, { val-reg, hilim-reg, lolim-reg}, name-idx, sysctl-table-idx, 193 * nom-voltage-index 194 */ 195 struct dbcool_sensor ADT7490_sensor_table[] = { 196 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 197 DBCOOL_LOCAL_HIGHLIM, 198 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 199 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 200 DBCOOL_REMOTE1_HIGHLIM, 201 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 202 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 203 DBCOOL_REMOTE2_HIGHLIM, 204 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 205 { DBC_VOLT, { DBCOOL_VCCP, 206 DBCOOL_VCCP_HIGHLIM, 207 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 208 { DBC_VOLT, { DBCOOL_VCC, 209 DBCOOL_VCC_HIGHLIM, 210 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 211 { DBC_VOLT, { DBCOOL_25VIN, 212 DBCOOL_25VIN_HIGHLIM, 213 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 }, 214 { DBC_VOLT, { DBCOOL_5VIN, 215 DBCOOL_5VIN_HIGHLIM, 216 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 }, 217 { DBC_VOLT, { DBCOOL_12VIN, 218 DBCOOL_12VIN_HIGHLIM, 219 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 }, 220 { DBC_VOLT, { DBCOOL_VTT, 221 DBCOOL_VTT_HIGHLIM, 222 DBCOOL_VTT_LOWLIM }, 14, 0, 5 }, 223 { DBC_VOLT, { DBCOOL_IMON, 224 DBCOOL_IMON_HIGHLIM, 225 DBCOOL_IMON_LOWLIM }, 15, 0, 5 }, 226 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 227 DBCOOL_NO_REG, 228 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 229 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 230 DBCOOL_NO_REG, 231 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 232 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 233 DBCOOL_NO_REG, 234 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 235 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 236 DBCOOL_NO_REG, 237 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 238 { DBC_VID, { DBCOOL_VID_REG, 239 DBCOOL_NO_REG, 240 DBCOOL_NO_REG }, 16, 0, 0 }, 241 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 242 DBCOOL_NO_REG, 243 DBCOOL_NO_REG }, 0, 5, 0 }, 244 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 245 DBCOOL_NO_REG, 246 DBCOOL_NO_REG }, 0, 6, 0 }, 247 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 248 DBCOOL_NO_REG, 249 DBCOOL_NO_REG }, 0, 7, 0 }, 250 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 251 DBCOOL_NO_REG, 252 DBCOOL_NO_REG }, 1, 5, 0 }, 253 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 254 DBCOOL_NO_REG, 255 DBCOOL_NO_REG }, 1, 6, 0 }, 256 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 257 DBCOOL_NO_REG, 258 DBCOOL_NO_REG }, 1, 7, 0 }, 259 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 260 DBCOOL_NO_REG, 261 DBCOOL_NO_REG }, 2, 5, 0 }, 262 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 263 DBCOOL_NO_REG, 264 DBCOOL_NO_REG }, 2, 6, 0 }, 265 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 266 DBCOOL_NO_REG, 267 DBCOOL_NO_REG }, 2, 7, 0 }, 268 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 269 }; 270 271 struct dbcool_sensor ADT7476_sensor_table[] = { 272 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 273 DBCOOL_LOCAL_HIGHLIM, 274 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 275 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 276 DBCOOL_REMOTE1_HIGHLIM, 277 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 278 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 279 DBCOOL_REMOTE2_HIGHLIM, 280 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 281 { DBC_VOLT, { DBCOOL_VCCP, 282 DBCOOL_VCCP_HIGHLIM, 283 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 284 { DBC_VOLT, { DBCOOL_VCC, 285 DBCOOL_VCC_HIGHLIM, 286 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 287 { DBC_VOLT, { DBCOOL_25VIN, 288 DBCOOL_25VIN_HIGHLIM, 289 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 }, 290 { DBC_VOLT, { DBCOOL_5VIN, 291 DBCOOL_5VIN_HIGHLIM, 292 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 }, 293 { DBC_VOLT, { DBCOOL_12VIN, 294 DBCOOL_12VIN_HIGHLIM, 295 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 }, 296 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 297 DBCOOL_NO_REG, 298 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 299 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 300 DBCOOL_NO_REG, 301 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 302 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 303 DBCOOL_NO_REG, 304 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 305 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 306 DBCOOL_NO_REG, 307 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 308 { DBC_VID, { DBCOOL_VID_REG, 309 DBCOOL_NO_REG, 310 DBCOOL_NO_REG }, 16, 0, 0 }, 311 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 312 DBCOOL_NO_REG, 313 DBCOOL_NO_REG }, 0, 5, 0 }, 314 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 315 DBCOOL_NO_REG, 316 DBCOOL_NO_REG }, 0, 6, 0 }, 317 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 318 DBCOOL_NO_REG, 319 DBCOOL_NO_REG }, 0, 7, 0 }, 320 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 321 DBCOOL_NO_REG, 322 DBCOOL_NO_REG }, 1, 5, 0 }, 323 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 324 DBCOOL_NO_REG, 325 DBCOOL_NO_REG }, 1, 6, 0 }, 326 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 327 DBCOOL_NO_REG, 328 DBCOOL_NO_REG }, 1, 7, 0 }, 329 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 330 DBCOOL_NO_REG, 331 DBCOOL_NO_REG }, 2, 5, 0 }, 332 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 333 DBCOOL_NO_REG, 334 DBCOOL_NO_REG }, 2, 6, 0 }, 335 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 336 DBCOOL_NO_REG, 337 DBCOOL_NO_REG }, 2, 7, 0 }, 338 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 339 }; 340 341 struct dbcool_sensor ADT7475_sensor_table[] = { 342 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 343 DBCOOL_LOCAL_HIGHLIM, 344 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 345 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 346 DBCOOL_REMOTE1_HIGHLIM, 347 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 348 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 349 DBCOOL_REMOTE2_HIGHLIM, 350 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 351 { DBC_VOLT, { DBCOOL_VCCP, 352 DBCOOL_VCCP_HIGHLIM, 353 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 354 { DBC_VOLT, { DBCOOL_VCC, 355 DBCOOL_VCC_HIGHLIM, 356 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 357 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 358 DBCOOL_NO_REG, 359 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 360 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 361 DBCOOL_NO_REG, 362 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 363 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 364 DBCOOL_NO_REG, 365 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 366 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 367 DBCOOL_NO_REG, 368 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 369 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 370 DBCOOL_NO_REG, 371 DBCOOL_NO_REG }, 0, 5, 0 }, 372 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 373 DBCOOL_NO_REG, 374 DBCOOL_NO_REG }, 0, 6, 0 }, 375 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 376 DBCOOL_NO_REG, 377 DBCOOL_NO_REG }, 0, 7, 0 }, 378 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 379 DBCOOL_NO_REG, 380 DBCOOL_NO_REG }, 1, 5, 0 }, 381 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 382 DBCOOL_NO_REG, 383 DBCOOL_NO_REG }, 1, 6, 0 }, 384 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 385 DBCOOL_NO_REG, 386 DBCOOL_NO_REG }, 1, 7, 0 }, 387 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 388 DBCOOL_NO_REG, 389 DBCOOL_NO_REG }, 2, 5, 0 }, 390 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 391 DBCOOL_NO_REG, 392 DBCOOL_NO_REG }, 2, 6, 0 }, 393 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 394 DBCOOL_NO_REG, 395 DBCOOL_NO_REG }, 2, 7, 0 }, 396 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 397 }; 398 399 /* 400 * The registers of dbcool_power_control must be in the same order as 401 * in enum dbc_pwm_params 402 */ 403 struct dbcool_power_control ADT7475_power_table[] = { 404 { { DBCOOL_PWM1_CTL, DBCOOL_PWM1_MINDUTY, 405 DBCOOL_PWM1_MAXDUTY, DBCOOL_PWM1_CURDUTY }, 406 "fan_control_1" }, 407 { { DBCOOL_PWM2_CTL, DBCOOL_PWM2_MINDUTY, 408 DBCOOL_PWM2_MAXDUTY, DBCOOL_PWM2_CURDUTY }, 409 "fan_control_2" }, 410 { { DBCOOL_PWM3_CTL, DBCOOL_PWM3_MINDUTY, 411 DBCOOL_PWM3_MAXDUTY, DBCOOL_PWM3_CURDUTY }, 412 "fan_control_3" }, 413 { { 0, 0, 0, 0 }, NULL } 414 }; 415 416 struct dbcool_sensor ADT7466_sensor_table[] = { 417 { DBC_TEMP, { DBCOOL_ADT7466_LCL_TEMP_MSB, 418 DBCOOL_ADT7466_LCL_TEMP_HILIM, 419 DBCOOL_ADT7466_LCL_TEMP_LOLIM }, 0, 0, 0 }, 420 { DBC_TEMP, { DBCOOL_ADT7466_REM_TEMP_MSB, 421 DBCOOL_ADT7466_REM_TEMP_HILIM, 422 DBCOOL_ADT7466_REM_TEMP_LOLIM }, 1, 0, 0 }, 423 { DBC_VOLT, { DBCOOL_ADT7466_VCC, 424 DBCOOL_ADT7466_VCC_HILIM, 425 DBCOOL_ADT7466_VCC_LOLIM }, 4, 0, 0 }, 426 { DBC_VOLT, { DBCOOL_ADT7466_AIN1, 427 DBCOOL_ADT7466_AIN1_HILIM, 428 DBCOOL_ADT7466_AIN1_LOLIM }, 9, 0, 6 }, 429 { DBC_VOLT, { DBCOOL_ADT7466_AIN2, 430 DBCOOL_ADT7466_AIN2_HILIM, 431 DBCOOL_ADT7466_AIN2_LOLIM }, 10, 0, 6 }, 432 { DBC_FAN, { DBCOOL_ADT7466_FANA_LSB, 433 DBCOOL_NO_REG, 434 DBCOOL_ADT7466_FANA_LOLIM_LSB }, 5, 0, 0 }, 435 { DBC_FAN, { DBCOOL_ADT7466_FANB_LSB, 436 DBCOOL_NO_REG, 437 DBCOOL_ADT7466_FANB_LOLIM_LSB }, 6, 0, 0 }, 438 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 439 }; 440 441 struct dbcool_sensor ADM1027_sensor_table[] = { 442 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 443 DBCOOL_LOCAL_HIGHLIM, 444 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 445 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 446 DBCOOL_REMOTE1_HIGHLIM, 447 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 448 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 449 DBCOOL_REMOTE2_HIGHLIM, 450 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 451 { DBC_VOLT, { DBCOOL_VCCP, 452 DBCOOL_VCCP_HIGHLIM, 453 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 454 { DBC_VOLT, { DBCOOL_VCC, 455 DBCOOL_VCC_HIGHLIM, 456 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 457 { DBC_VOLT, { DBCOOL_25VIN, 458 DBCOOL_25VIN_HIGHLIM, 459 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 }, 460 { DBC_VOLT, { DBCOOL_5VIN, 461 DBCOOL_5VIN_HIGHLIM, 462 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 }, 463 { DBC_VOLT, { DBCOOL_12VIN, 464 DBCOOL_12VIN_HIGHLIM, 465 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 }, 466 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 467 DBCOOL_NO_REG, 468 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 469 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 470 DBCOOL_NO_REG, 471 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 472 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 473 DBCOOL_NO_REG, 474 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 475 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 476 DBCOOL_NO_REG, 477 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 478 { DBC_VID, { DBCOOL_VID_REG, 479 DBCOOL_NO_REG, 480 DBCOOL_NO_REG }, 16, 0, 0 }, 481 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 482 DBCOOL_NO_REG, 483 DBCOOL_NO_REG }, 0, 5, 0 }, 484 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 485 DBCOOL_NO_REG, 486 DBCOOL_NO_REG }, 0, 6, 0 }, 487 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 488 DBCOOL_NO_REG, 489 DBCOOL_NO_REG }, 0, 7, 0 }, 490 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 491 DBCOOL_NO_REG, 492 DBCOOL_NO_REG }, 1, 5, 0 }, 493 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 494 DBCOOL_NO_REG, 495 DBCOOL_NO_REG }, 1, 6, 0 }, 496 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 497 DBCOOL_NO_REG, 498 DBCOOL_NO_REG }, 1, 7, 0 }, 499 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 500 DBCOOL_NO_REG, 501 DBCOOL_NO_REG }, 2, 5, 0 }, 502 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 503 DBCOOL_NO_REG, 504 DBCOOL_NO_REG }, 2, 6, 0 }, 505 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 506 DBCOOL_NO_REG, 507 DBCOOL_NO_REG }, 2, 7, 0 }, 508 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 509 }; 510 511 struct dbcool_sensor ADM1030_sensor_table[] = { 512 { DBC_TEMP, { DBCOOL_ADM1030_L_TEMP, 513 DBCOOL_ADM1030_L_HI_LIM, 514 DBCOOL_ADM1030_L_LO_LIM }, 0, 0, 0 }, 515 { DBC_TEMP, { DBCOOL_ADM1030_R_TEMP, 516 DBCOOL_ADM1030_R_HI_LIM, 517 DBCOOL_ADM1030_R_LO_LIM }, 1, 0, 0 }, 518 { DBC_FAN, { DBCOOL_ADM1030_FAN_TACH, 519 DBCOOL_NO_REG, 520 DBCOOL_ADM1030_FAN_LO_LIM }, 5, 0, 0 }, 521 { DBC_CTL, { DBCOOL_ADM1030_L_TMIN, 522 DBCOOL_NO_REG, 523 DBCOOL_NO_REG }, 0, 8, 0 }, 524 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH, 525 DBCOOL_NO_REG, 526 DBCOOL_NO_REG }, 0, 9, 0 }, 527 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH, 528 DBCOOL_NO_REG, 529 DBCOOL_NO_REG }, 0, 6, 0 }, 530 { DBC_CTL, { DBCOOL_ADM1030_R_TMIN, 531 DBCOOL_NO_REG, 532 DBCOOL_NO_REG }, 1, 8, 0 }, 533 { DBC_CTL, { DBCOOL_ADM1030_R_TTHRESH, 534 DBCOOL_NO_REG, 535 DBCOOL_NO_REG }, 1, 9, 0 }, 536 { DBC_CTL, { DBCOOL_ADM1030_R_TTHRESH, 537 DBCOOL_NO_REG, 538 DBCOOL_NO_REG }, 1, 6, 0 }, 539 { DBC_EOF, {0, 0, 0 }, 0, 0, 0 } 540 }; 541 542 struct dbcool_power_control ADM1030_power_table[] = { 543 { { DBCOOL_ADM1030_CFG1, DBCOOL_NO_REG, DBCOOL_NO_REG, 544 DBCOOL_ADM1030_FAN_SPEED_CFG }, 545 "fan_control_1" }, 546 { { 0, 0, 0, 0 }, NULL } 547 }; 548 549 struct dbcool_sensor ADM1031_sensor_table[] = { 550 { DBC_TEMP, { DBCOOL_ADM1030_L_TEMP, 551 DBCOOL_ADM1030_L_HI_LIM, 552 DBCOOL_ADM1030_L_LO_LIM }, 0, 0, 0 }, 553 { DBC_TEMP, { DBCOOL_ADM1030_R_TEMP, 554 DBCOOL_ADM1030_R_HI_LIM, 555 DBCOOL_ADM1030_R_LO_LIM }, 1, 0, 0 }, 556 { DBC_TEMP, { DBCOOL_ADM1031_R2_TEMP, 557 DBCOOL_ADM1031_R2_HI_LIM, 558 DBCOOL_ADM1031_R2_LO_LIM }, 2, 0, 0 }, 559 { DBC_FAN, { DBCOOL_ADM1030_FAN_TACH, 560 DBCOOL_NO_REG, 561 DBCOOL_ADM1030_FAN_LO_LIM }, 5, 0, 0 }, 562 { DBC_FAN, { DBCOOL_ADM1031_FAN2_TACH, 563 DBCOOL_NO_REG, 564 DBCOOL_ADM1031_FAN2_LO_LIM }, 6, 0, 0 }, 565 { DBC_CTL, { DBCOOL_ADM1030_L_TMIN, 566 DBCOOL_NO_REG, 567 DBCOOL_NO_REG }, 0, 8, 0 }, 568 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH, 569 DBCOOL_NO_REG, 570 DBCOOL_NO_REG }, 0, 9, 0 }, 571 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH, 572 DBCOOL_NO_REG, 573 DBCOOL_NO_REG }, 0, 6, 0 }, 574 { DBC_CTL, { DBCOOL_ADM1030_R_TMIN, 575 DBCOOL_NO_REG, 576 DBCOOL_NO_REG }, 1, 8, 0 }, 577 { DBC_CTL, { DBCOOL_ADM1030_R_TTHRESH, 578 DBCOOL_NO_REG, 579 DBCOOL_NO_REG }, 1, 9, 0 }, 580 { DBC_CTL, { DBCOOL_ADM1030_R_TTHRESH, 581 DBCOOL_NO_REG, 582 DBCOOL_NO_REG }, 1, 6, 0 }, 583 { DBC_CTL, { DBCOOL_ADM1031_R2_TMIN, 584 DBCOOL_NO_REG, 585 DBCOOL_NO_REG }, 2, 8, 0 }, 586 { DBC_CTL, { DBCOOL_ADM1031_R2_TTHRESH, 587 DBCOOL_NO_REG, 588 DBCOOL_NO_REG }, 2, 9, 0 }, 589 { DBC_CTL, { DBCOOL_ADM1031_R2_TTHRESH, 590 DBCOOL_NO_REG, 591 DBCOOL_NO_REG }, 2, 6, 0 }, 592 { DBC_EOF, {0, 0, 0 }, 0, 0, 0 } 593 }; 594 595 struct dbcool_power_control ADM1031_power_table[] = { 596 { { DBCOOL_ADM1030_CFG1, DBCOOL_NO_REG, DBCOOL_NO_REG, 597 DBCOOL_ADM1030_FAN_SPEED_CFG }, 598 "fan_control_1" }, 599 { { DBCOOL_ADM1030_CFG1, DBCOOL_NO_REG, DBCOOL_NO_REG, 600 DBCOOL_ADM1030_FAN_SPEED_CFG }, 601 "fan_control_2" }, 602 { { 0, 0, 0, 0 }, NULL } 603 }; 604 605 struct dbcool_sensor EMC6D103S_sensor_table[] = { 606 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 607 DBCOOL_LOCAL_HIGHLIM, 608 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 609 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 610 DBCOOL_REMOTE1_HIGHLIM, 611 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 612 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 613 DBCOOL_REMOTE2_HIGHLIM, 614 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 615 { DBC_VOLT, { DBCOOL_VCCP, 616 DBCOOL_VCCP_HIGHLIM, 617 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 618 { DBC_VOLT, { DBCOOL_VCC, 619 DBCOOL_VCC_HIGHLIM, 620 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 621 { DBC_VOLT, { DBCOOL_25VIN, 622 DBCOOL_25VIN_HIGHLIM, 623 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 }, 624 { DBC_VOLT, { DBCOOL_5VIN, 625 DBCOOL_5VIN_HIGHLIM, 626 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 }, 627 { DBC_VOLT, { DBCOOL_12VIN, 628 DBCOOL_12VIN_HIGHLIM, 629 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 }, 630 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 631 DBCOOL_NO_REG, 632 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 633 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 634 DBCOOL_NO_REG, 635 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 636 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 637 DBCOOL_NO_REG, 638 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 639 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 640 DBCOOL_NO_REG, 641 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 642 { DBC_VID, { DBCOOL_VID_REG, 643 DBCOOL_NO_REG, 644 DBCOOL_NO_REG }, 16, 0, 0 }, 645 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 646 DBCOOL_NO_REG, 647 DBCOOL_NO_REG }, 0, 5, 0 }, 648 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 649 DBCOOL_NO_REG, 650 DBCOOL_NO_REG }, 0, 6, 0 }, 651 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 652 DBCOOL_NO_REG, 653 DBCOOL_NO_REG }, 1, 5, 0 }, 654 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 655 DBCOOL_NO_REG, 656 DBCOOL_NO_REG }, 1, 6, 0 }, 657 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 658 DBCOOL_NO_REG, 659 DBCOOL_NO_REG }, 2, 5, 0 }, 660 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 661 DBCOOL_NO_REG, 662 DBCOOL_NO_REG }, 2, 6, 0 }, 663 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 664 }; 665 666 struct chip_id chip_table[] = { 667 { DBCOOL_COMPANYID, ADT7490_DEVICEID, ADT7490_REV_ID, 668 ADT7490_sensor_table, ADT7475_power_table, 669 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_PECI, 670 90000 * 60, "ADT7490" }, 671 { DBCOOL_COMPANYID, ADT7476_DEVICEID, 0xff, 672 ADT7476_sensor_table, ADT7475_power_table, 673 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY, 674 90000 * 60, "ADT7476" }, 675 { DBCOOL_COMPANYID, ADT7475_DEVICEID, 0xff, 676 ADT7475_sensor_table, ADT7475_power_table, 677 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_SHDN, 678 90000 * 60, "ADT7475" }, 679 { DBCOOL_COMPANYID, ADT7473_DEVICEID, ADT7473_REV_ID1, 680 ADT7475_sensor_table, ADT7475_power_table, 681 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_SHDN, 682 90000 * 60, "ADT7460/ADT7463" }, 683 { DBCOOL_COMPANYID, ADT7473_DEVICEID, ADT7473_REV_ID2, 684 ADT7475_sensor_table, ADT7475_power_table, 685 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_SHDN, 686 90000 * 60, "ADT7463-1" }, 687 { DBCOOL_COMPANYID, ADT7468_DEVICEID, 0xff, 688 ADT7476_sensor_table, ADT7475_power_table, 689 DBCFLAG_TEMPOFFSET | DBCFLAG_MULTI_VCC | DBCFLAG_HAS_MAXDUTY | 690 DBCFLAG_4BIT_VER | DBCFLAG_HAS_SHDN, 691 90000 * 60, "ADT7467/ADT7468" }, 692 { DBCOOL_COMPANYID, ADT7466_DEVICEID, 0xff, 693 ADT7466_sensor_table, NULL, 694 DBCFLAG_ADT7466 | DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_SHDN, 695 82000 * 60, "ADT7466" }, 696 { DBCOOL_COMPANYID, ADT7463_DEVICEID, ADT7463_REV_ID1, 697 ADM1027_sensor_table, ADT7475_power_table, 698 DBCFLAG_MULTI_VCC | DBCFLAG_4BIT_VER | DBCFLAG_HAS_SHDN, 699 90000 * 60, "ADT7463" }, 700 { DBCOOL_COMPANYID, ADT7463_DEVICEID, ADT7463_REV_ID2, 701 ADM1027_sensor_table, ADT7475_power_table, 702 DBCFLAG_MULTI_VCC | DBCFLAG_4BIT_VER | DBCFLAG_HAS_SHDN | 703 DBCFLAG_HAS_VID_SEL, 704 90000 * 60, "ADT7463" }, 705 { DBCOOL_COMPANYID, ADM1027_DEVICEID, ADM1027_REV_ID, 706 ADM1027_sensor_table, ADT7475_power_table, 707 DBCFLAG_MULTI_VCC | DBCFLAG_4BIT_VER, 708 90000 * 60, "ADM1027" }, 709 { DBCOOL_COMPANYID, ADM1030_DEVICEID, 0xff, 710 ADM1030_sensor_table, ADM1030_power_table, 711 DBCFLAG_ADM1030 | DBCFLAG_NO_READBYTE, 712 11250 * 60, "ADM1030" }, 713 { DBCOOL_COMPANYID, ADM1031_DEVICEID, 0xff, 714 ADM1031_sensor_table, ADM1030_power_table, 715 DBCFLAG_ADM1030 | DBCFLAG_NO_READBYTE, 716 11250 * 60, "ADM1031" }, 717 { SMSC_COMPANYID, EMC6D103S_DEVICEID, EMC6D103S_REV_ID, 718 EMC6D103S_sensor_table, ADT7475_power_table, 719 DBCFLAG_4BIT_VER, 720 90000 * 60, "EMC6D103S" }, 721 { 0, 0, 0, NULL, NULL, 0, 0, NULL } 722 }; 723 724 static const char *behavior[] = { 725 "remote1", "local", "remote2", "full-speed", 726 "disabled", "local+remote2","all-temps", "manual" 727 }; 728 729 static char dbcool_cur_behav[16]; 730 731 CFATTACH_DECL_NEW(dbcool, sizeof(struct dbcool_softc), 732 dbcool_match, dbcool_attach, dbcool_detach, NULL); 733 734 int 735 dbcool_match(device_t parent, cfdata_t cf, void *aux) 736 { 737 struct i2c_attach_args *ia = aux; 738 struct dbcool_chipset dc; 739 dc.dc_tag = ia->ia_tag; 740 dc.dc_addr = ia->ia_addr; 741 dc.dc_chip = NULL; 742 dc.dc_readreg = dbcool_readreg; 743 dc.dc_writereg = dbcool_writereg; 744 745 /* no probing if we attach to iic, but verify chip id and address */ 746 if ((ia->ia_addr & DBCOOL_ADDRMASK) != DBCOOL_ADDR) 747 return 0; 748 if (dbcool_chip_ident(&dc) >= 0) 749 return 1; 750 751 return 0; 752 } 753 754 void 755 dbcool_attach(device_t parent, device_t self, void *aux) 756 { 757 struct dbcool_softc *sc = device_private(self); 758 struct i2c_attach_args *args = aux; 759 uint8_t ver; 760 761 sc->sc_dc.dc_addr = args->ia_addr; 762 sc->sc_dc.dc_tag = args->ia_tag; 763 sc->sc_dc.dc_chip = NULL; 764 sc->sc_dc.dc_readreg = dbcool_readreg; 765 sc->sc_dc.dc_writereg = dbcool_writereg; 766 (void)dbcool_chip_ident(&sc->sc_dc); 767 sc->sc_dev = self; 768 769 aprint_naive("\n"); 770 aprint_normal("\n"); 771 772 ver = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_REVISION_REG); 773 if (sc->sc_dc.dc_chip->flags & DBCFLAG_4BIT_VER) 774 if (sc->sc_dc.dc_chip->company == SMSC_COMPANYID) 775 { 776 aprint_normal_dev(self, "SMSC %s Controller " 777 "(rev 0x%02x, stepping 0x%02x)\n", sc->sc_dc.dc_chip->name, 778 ver >> 4, ver & 0x0f); 779 } else { 780 aprint_normal_dev(self, "%s dBCool(tm) Controller " 781 "(rev 0x%02x, stepping 0x%02x)\n", sc->sc_dc.dc_chip->name, 782 ver >> 4, ver & 0x0f); 783 } 784 else 785 aprint_normal_dev(self, "%s dBCool(tm) Controller " 786 "(rev 0x%04x)\n", sc->sc_dc.dc_chip->name, ver); 787 788 sc->sc_sysctl_log = NULL; 789 790 #ifdef _MODULE 791 sysctl_dbcoolsetup(&sc->sc_sysctl_log); 792 #endif 793 794 dbcool_setup(self); 795 796 if (!pmf_device_register(self, dbcool_pmf_suspend, dbcool_pmf_resume)) 797 aprint_error_dev(self, "couldn't establish power handler\n"); 798 } 799 800 static int 801 dbcool_detach(device_t self, int flags) 802 { 803 struct dbcool_softc *sc = device_private(self); 804 805 pmf_device_deregister(self); 806 807 sysmon_envsys_unregister(sc->sc_sme); 808 809 sysctl_teardown(&sc->sc_sysctl_log); 810 811 sc->sc_sme = NULL; 812 return 0; 813 } 814 815 /* On suspend, we save the state of the SHDN bit, then set it */ 816 bool dbcool_pmf_suspend(device_t dev, const pmf_qual_t *qual) 817 { 818 struct dbcool_softc *sc = device_private(dev); 819 uint8_t reg, bit, cfg; 820 821 if ((sc->sc_dc.dc_chip->flags & DBCFLAG_HAS_SHDN) == 0) 822 return true; 823 824 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) { 825 reg = DBCOOL_ADT7466_CONFIG2; 826 bit = DBCOOL_ADT7466_CFG2_SHDN; 827 } else { 828 reg = DBCOOL_CONFIG2_REG; 829 bit = DBCOOL_CFG2_SHDN; 830 } 831 cfg = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 832 sc->sc_suspend = cfg & bit; 833 cfg |= bit; 834 sc->sc_dc.dc_writereg(&sc->sc_dc, reg, cfg); 835 836 return true; 837 } 838 839 /* On resume, we restore the previous state of the SHDN bit */ 840 bool dbcool_pmf_resume(device_t dev, const pmf_qual_t *qual) 841 { 842 struct dbcool_softc *sc = device_private(dev); 843 uint8_t reg, bit, cfg; 844 845 if ((sc->sc_dc.dc_chip->flags & DBCFLAG_HAS_SHDN) == 0) 846 return true; 847 848 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) { 849 reg = DBCOOL_ADT7466_CONFIG2; 850 bit = DBCOOL_ADT7466_CFG2_SHDN; 851 } else { 852 reg = DBCOOL_CONFIG2_REG; 853 bit = DBCOOL_CFG2_SHDN; 854 } 855 cfg = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 856 cfg &= ~sc->sc_suspend; 857 sc->sc_dc.dc_writereg(&sc->sc_dc, reg, cfg); 858 859 return true; 860 861 } 862 863 uint8_t 864 dbcool_readreg(struct dbcool_chipset *dc, uint8_t reg) 865 { 866 uint8_t data = 0; 867 868 if (iic_acquire_bus(dc->dc_tag, 0) != 0) 869 return data; 870 871 if (dc->dc_chip == NULL || dc->dc_chip->flags & DBCFLAG_NO_READBYTE) { 872 /* ADM1027 doesn't support i2c read_byte protocol */ 873 if (iic_smbus_send_byte(dc->dc_tag, dc->dc_addr, reg, 0) != 0) 874 goto bad; 875 (void)iic_smbus_receive_byte(dc->dc_tag, dc->dc_addr, &data, 0); 876 } else 877 (void)iic_smbus_read_byte(dc->dc_tag, dc->dc_addr, reg, &data, 878 0); 879 880 bad: 881 iic_release_bus(dc->dc_tag, 0); 882 return data; 883 } 884 885 void 886 dbcool_writereg(struct dbcool_chipset *dc, uint8_t reg, uint8_t val) 887 { 888 if (iic_acquire_bus(dc->dc_tag, 0) != 0) 889 return; 890 891 (void)iic_smbus_write_byte(dc->dc_tag, dc->dc_addr, reg, val, 0); 892 893 iic_release_bus(dc->dc_tag, 0); 894 } 895 896 static bool 897 dbcool_islocked(struct dbcool_softc *sc) 898 { 899 uint8_t cfg_reg; 900 901 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 902 return 0; 903 904 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) 905 cfg_reg = DBCOOL_ADT7466_CONFIG1; 906 else 907 cfg_reg = DBCOOL_CONFIG1_REG; 908 909 if (sc->sc_dc.dc_readreg(&sc->sc_dc, cfg_reg) & DBCOOL_CFG1_LOCK) 910 return 1; 911 else 912 return 0; 913 } 914 915 static int 916 dbcool_read_temp(struct dbcool_softc *sc, uint8_t reg, bool extres) 917 { 918 uint8_t t1, t2, t3, val, ext = 0; 919 int temp; 920 921 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) { 922 /* 923 * ADT7466 temps are in strange location 924 */ 925 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADT7466_CONFIG1); 926 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 927 if (extres) 928 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, reg + 1); 929 } else if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) { 930 /* 931 * ADM1030 temps are in their own special place, too 932 */ 933 if (extres) { 934 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_TEMP_EXTRES); 935 if (reg == DBCOOL_ADM1030_L_TEMP) 936 ext >>= 6; 937 else if (reg == DBCOOL_ADM1031_R2_TEMP) 938 ext >>= 4; 939 else 940 ext >>= 1; 941 ext &= 0x03; 942 } 943 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 944 } else if (extres) { 945 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES2_REG); 946 947 /* Read all msb regs to unlatch them */ 948 t1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_12VIN); 949 t1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_REMOTE1_TEMP); 950 t2 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_REMOTE2_TEMP); 951 t3 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_LOCAL_TEMP); 952 switch (reg) { 953 case DBCOOL_REMOTE1_TEMP: 954 val = t1; 955 ext >>= 2; 956 break; 957 case DBCOOL_LOCAL_TEMP: 958 val = t3; 959 ext >>= 4; 960 break; 961 case DBCOOL_REMOTE2_TEMP: 962 val = t2; 963 ext >>= 6; 964 break; 965 default: 966 val = 0; 967 break; 968 } 969 ext &= 0x03; 970 } 971 else 972 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 973 974 /* Check for invalid temp values */ 975 if ((sc->sc_temp_offset == 0 && val == 0x80) || 976 (sc->sc_temp_offset != 0 && val == 0)) 977 return 0; 978 979 /* If using offset mode, adjust, else treat as signed */ 980 if (sc->sc_temp_offset) { 981 temp = val; 982 temp -= sc->sc_temp_offset; 983 } else 984 temp = (int8_t)val; 985 986 /* Convert degC to uK and include extended precision bits */ 987 temp *= 1000000; 988 temp += 250000 * (int)ext; 989 temp += 273150000U; 990 991 return temp; 992 } 993 994 static int 995 dbcool_read_rpm(struct dbcool_softc *sc, uint8_t reg) 996 { 997 int rpm; 998 uint8_t rpm_lo, rpm_hi; 999 1000 rpm_lo = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 1001 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 1002 rpm_hi = (rpm_lo == 0xff)?0xff:0x0; 1003 else 1004 rpm_hi = sc->sc_dc.dc_readreg(&sc->sc_dc, reg + 1); 1005 1006 rpm = (rpm_hi << 8) | rpm_lo; 1007 if (rpm == 0xffff) 1008 return 0; /* 0xffff indicates stalled/failed fan */ 1009 1010 /* don't divide by zero */ 1011 return (rpm == 0)? 0 : (sc->sc_dc.dc_chip->rpm_dividend / rpm); 1012 } 1013 1014 /* Provide chip's supply voltage, in microvolts */ 1015 static int 1016 dbcool_supply_voltage(struct dbcool_softc *sc) 1017 { 1018 if (sc->sc_dc.dc_chip->flags & DBCFLAG_MULTI_VCC) { 1019 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_CONFIG1_REG) & DBCOOL_CFG1_Vcc) 1020 return 5002500; 1021 else 1022 return 3300000; 1023 } else if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) { 1024 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADT7466_CONFIG1) & 1025 DBCOOL_ADT7466_CFG1_Vcc) 1026 return 5000000; 1027 else 1028 return 3300000; 1029 } else 1030 return 3300000; 1031 } 1032 1033 /* 1034 * Nominal voltages are calculated in microvolts 1035 */ 1036 static int 1037 dbcool_read_volt(struct dbcool_softc *sc, uint8_t reg, int nom_idx, bool extres) 1038 { 1039 uint8_t ext = 0, v1, v2, v3, v4, val; 1040 int64_t ret; 1041 int64_t nom; 1042 1043 nom = nominal_voltages[nom_idx]; 1044 if (nom < 0) 1045 nom = sc->sc_supply_voltage; 1046 1047 /* ADT7466 voltages are in strange locations with only 8-bits */ 1048 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) 1049 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 1050 else 1051 /* 1052 * It's a "normal" dbCool chip - check for regs that 1053 * share extended resolution bits since we have to 1054 * read all the MSB registers to unlatch them. 1055 */ 1056 if (!extres) 1057 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 1058 else if (reg == DBCOOL_12VIN) { 1059 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES2_REG) & 0x03; 1060 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 1061 (void)dbcool_read_temp(sc, DBCOOL_LOCAL_TEMP, true); 1062 } else if (reg == DBCOOL_VTT || reg == DBCOOL_IMON) { 1063 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES_VTT_IMON); 1064 v1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_IMON); 1065 v2 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VTT); 1066 if (reg == DBCOOL_IMON) { 1067 val = v1; 1068 ext >>= 6; 1069 } else 1070 val = v2; 1071 ext >>= 4; 1072 ext &= 0x0f; 1073 } else { 1074 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES1_REG); 1075 v1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_25VIN); 1076 v2 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VCCP); 1077 v3 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VCC); 1078 v4 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_5VIN); 1079 1080 switch (reg) { 1081 case DBCOOL_25VIN: 1082 val = v1; 1083 break; 1084 case DBCOOL_VCCP: 1085 val = v2; 1086 ext >>= 2; 1087 break; 1088 case DBCOOL_VCC: 1089 val = v3; 1090 ext >>= 4; 1091 break; 1092 case DBCOOL_5VIN: 1093 val = v4; 1094 ext >>= 6; 1095 break; 1096 default: 1097 val = nom = 0; 1098 } 1099 ext &= 0x03; 1100 } 1101 1102 /* 1103 * Scale the nominal value by the 10-bit fraction 1104 * 1105 * Returned value is in microvolts. 1106 */ 1107 ret = val; 1108 ret <<= 2; 1109 ret |= ext; 1110 ret = (ret * nom) / 0x300; 1111 1112 return ret; 1113 } 1114 1115 SYSCTL_SETUP(sysctl_dbcoolsetup, "sysctl dBCool subtree setup") 1116 { 1117 sysctl_createv(clog, 0, NULL, NULL, 1118 #ifdef _MODULE 1119 0, 1120 #else 1121 CTLFLAG_PERMANENT, 1122 #endif 1123 CTLTYPE_NODE, "hw", NULL, 1124 NULL, 0, NULL, 0, 1125 CTL_HW, CTL_EOL); 1126 } 1127 1128 static int 1129 sysctl_dbcool_temp(SYSCTLFN_ARGS) 1130 { 1131 struct sysctlnode node; 1132 struct dbcool_softc *sc; 1133 int reg, error; 1134 uint8_t chipreg; 1135 uint8_t newreg; 1136 1137 node = *rnode; 1138 sc = (struct dbcool_softc *)node.sysctl_data; 1139 chipreg = node.sysctl_num & 0xff; 1140 1141 if (sc->sc_temp_offset) { 1142 reg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1143 reg -= sc->sc_temp_offset; 1144 } else 1145 reg = (int8_t)sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1146 1147 node.sysctl_data = ® 1148 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1149 1150 if (error || newp == NULL) 1151 return error; 1152 1153 /* We were asked to update the value - sanity check before writing */ 1154 if (*(int *)node.sysctl_data < -64 || 1155 *(int *)node.sysctl_data > 127 + sc->sc_temp_offset) 1156 return EINVAL; 1157 1158 newreg = *(int *)node.sysctl_data; 1159 newreg += sc->sc_temp_offset; 1160 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1161 return 0; 1162 } 1163 1164 static int 1165 sysctl_adm1030_temp(SYSCTLFN_ARGS) 1166 { 1167 struct sysctlnode node; 1168 struct dbcool_softc *sc; 1169 int reg, error; 1170 uint8_t chipreg, oldreg, newreg; 1171 1172 node = *rnode; 1173 sc = (struct dbcool_softc *)node.sysctl_data; 1174 chipreg = node.sysctl_num & 0xff; 1175 1176 oldreg = (int8_t)sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1177 reg = (oldreg >> 1) & ~0x03; 1178 1179 node.sysctl_data = ® 1180 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1181 1182 if (error || newp == NULL) 1183 return error; 1184 1185 /* We were asked to update the value - sanity check before writing */ 1186 if (*(int *)node.sysctl_data < 0 || *(int *)node.sysctl_data > 127) 1187 return EINVAL; 1188 1189 newreg = *(int *)node.sysctl_data; 1190 newreg &= ~0x03; 1191 newreg <<= 1; 1192 newreg |= (oldreg & 0x07); 1193 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1194 return 0; 1195 } 1196 1197 static int 1198 sysctl_adm1030_trange(SYSCTLFN_ARGS) 1199 { 1200 struct sysctlnode node; 1201 struct dbcool_softc *sc; 1202 int reg, error, newval; 1203 uint8_t chipreg, oldreg, newreg; 1204 1205 node = *rnode; 1206 sc = (struct dbcool_softc *)node.sysctl_data; 1207 chipreg = node.sysctl_num & 0xff; 1208 1209 oldreg = (int8_t)sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1210 reg = oldreg & 0x07; 1211 1212 node.sysctl_data = ® 1213 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1214 1215 if (error || newp == NULL) 1216 return error; 1217 1218 /* We were asked to update the value - sanity check before writing */ 1219 newval = *(int *)node.sysctl_data; 1220 1221 if (newval == 5) 1222 newreg = 0; 1223 else if (newval == 10) 1224 newreg = 1; 1225 else if (newval == 20) 1226 newreg = 2; 1227 else if (newval == 40) 1228 newreg = 3; 1229 else if (newval == 80) 1230 newreg = 4; 1231 else 1232 return EINVAL; 1233 1234 newreg |= (oldreg & ~0x07); 1235 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1236 return 0; 1237 } 1238 1239 static int 1240 sysctl_dbcool_duty(SYSCTLFN_ARGS) 1241 { 1242 struct sysctlnode node; 1243 struct dbcool_softc *sc; 1244 int reg, error; 1245 uint8_t chipreg, oldreg, newreg; 1246 1247 node = *rnode; 1248 sc = (struct dbcool_softc *)node.sysctl_data; 1249 chipreg = node.sysctl_num & 0xff; 1250 1251 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1252 reg = (uint32_t)oldreg; 1253 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 1254 reg = ((reg & 0x0f) * 100) / 15; 1255 else 1256 reg = (reg * 100) / 255; 1257 node.sysctl_data = ® 1258 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1259 1260 if (error || newp == NULL) 1261 return error; 1262 1263 /* We were asked to update the value - sanity check before writing */ 1264 if (*(int *)node.sysctl_data < 0 || *(int *)node.sysctl_data > 100) 1265 return EINVAL; 1266 1267 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) { 1268 newreg = *(uint8_t *)(node.sysctl_data) * 15 / 100; 1269 newreg |= oldreg & 0xf0; 1270 } else 1271 newreg = *(uint8_t *)(node.sysctl_data) * 255 / 100; 1272 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1273 return 0; 1274 } 1275 1276 static int 1277 sysctl_dbcool_behavior(SYSCTLFN_ARGS) 1278 { 1279 struct sysctlnode node; 1280 struct dbcool_softc *sc; 1281 int i, reg, error; 1282 uint8_t chipreg, oldreg, newreg; 1283 1284 node = *rnode; 1285 sc = (struct dbcool_softc *)node.sysctl_data; 1286 chipreg = node.sysctl_num & 0xff; 1287 1288 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1289 1290 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) { 1291 if ((sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_CFG2) & 1) == 0) 1292 reg = 4; 1293 else if ((oldreg & 0x80) == 0) 1294 reg = 7; 1295 else if ((oldreg & 0x60) == 0) 1296 reg = 4; 1297 else 1298 reg = 6; 1299 } else 1300 reg = (oldreg >> 5) & 0x07; 1301 1302 strlcpy(dbcool_cur_behav, behavior[reg], sizeof(dbcool_cur_behav)); 1303 node.sysctl_data = dbcool_cur_behav; 1304 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1305 1306 if (error || newp == NULL) 1307 return error; 1308 1309 /* We were asked to update the value - convert string to value */ 1310 newreg = __arraycount(behavior); 1311 for (i = 0; i < __arraycount(behavior); i++) 1312 if (strcmp(node.sysctl_data, behavior[i]) == 0) 1313 break; 1314 if (i >= __arraycount(behavior)) 1315 return EINVAL; 1316 1317 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) { 1318 /* 1319 * ADM1030 splits fan controller behavior across two 1320 * registers. We also do not support Auto-Filter mode 1321 * nor do we support Manual-RPM-feedback. 1322 */ 1323 if (newreg == 4) { 1324 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_CFG2); 1325 oldreg &= ~0x01; 1326 sc->sc_dc.dc_writereg(&sc->sc_dc, DBCOOL_ADM1030_CFG2, oldreg); 1327 } else { 1328 if (newreg == 0) 1329 newreg = 4; 1330 else if (newreg == 6) 1331 newreg = 7; 1332 else if (newreg == 7) 1333 newreg = 0; 1334 else 1335 return EINVAL; 1336 newreg <<= 5; 1337 newreg |= (oldreg & 0x1f); 1338 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1339 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_CFG2) | 1; 1340 sc->sc_dc.dc_writereg(&sc->sc_dc, DBCOOL_ADM1030_CFG2, oldreg); 1341 } 1342 } else { 1343 newreg = (sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg) & 0x1f) | (i << 5); 1344 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1345 } 1346 return 0; 1347 } 1348 1349 static int 1350 sysctl_dbcool_slope(SYSCTLFN_ARGS) 1351 { 1352 struct sysctlnode node; 1353 struct dbcool_softc *sc; 1354 int reg, error; 1355 uint8_t chipreg; 1356 uint8_t newreg; 1357 1358 node = *rnode; 1359 sc = (struct dbcool_softc *)node.sysctl_data; 1360 chipreg = node.sysctl_num & 0xff; 1361 1362 reg = (sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg) >> 4) & 0x0f; 1363 node.sysctl_data = ® 1364 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1365 1366 if (error || newp == NULL) 1367 return error; 1368 1369 /* We were asked to update the value - sanity check before writing */ 1370 if (*(int *)node.sysctl_data < 0 || *(int *)node.sysctl_data > 0x0f) 1371 return EINVAL; 1372 1373 newreg = (sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg) & 0x0f) | 1374 (*(int *)node.sysctl_data << 4); 1375 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1376 return 0; 1377 } 1378 1379 static int 1380 sysctl_dbcool_thyst(SYSCTLFN_ARGS) 1381 { 1382 struct sysctlnode node; 1383 struct dbcool_softc *sc; 1384 int reg, error; 1385 uint8_t chipreg; 1386 uint8_t newreg, newhyst; 1387 1388 node = *rnode; 1389 sc = (struct dbcool_softc *)node.sysctl_data; 1390 chipreg = node.sysctl_num & 0x7f; 1391 1392 /* retrieve 4-bit value */ 1393 newreg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1394 if ((node.sysctl_num & 0x80) == 0) 1395 reg = newreg >> 4; 1396 else 1397 reg = newreg; 1398 reg = reg & 0x0f; 1399 1400 node.sysctl_data = ® 1401 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1402 1403 if (error || newp == NULL) 1404 return error; 1405 1406 /* We were asked to update the value - sanity check before writing */ 1407 newhyst = *(int *)node.sysctl_data; 1408 if (newhyst > 0x0f) 1409 return EINVAL; 1410 1411 /* Insert new value into field and update register */ 1412 if ((node.sysctl_num & 0x80) == 0) { 1413 newreg &= 0x0f; 1414 newreg |= (newhyst << 4); 1415 } else { 1416 newreg &= 0xf0; 1417 newreg |= newhyst; 1418 } 1419 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1420 return 0; 1421 } 1422 1423 #ifdef DBCOOL_DEBUG 1424 1425 /* 1426 * These routines can be used for debugging. reg_select is used to 1427 * select any arbitrary register in the device. reg_access is used 1428 * to read (and optionally update) the selected register. 1429 * 1430 * No attempt is made to validate the data passed. If you use these 1431 * routines, you are assumed to know what you're doing! 1432 * 1433 * Caveat user 1434 */ 1435 static int 1436 sysctl_dbcool_reg_select(SYSCTLFN_ARGS) 1437 { 1438 struct sysctlnode node; 1439 struct dbcool_softc *sc; 1440 int reg, error; 1441 1442 node = *rnode; 1443 sc = (struct dbcool_softc *)node.sysctl_data; 1444 1445 reg = sc->sc_user_reg; 1446 node.sysctl_data = ® 1447 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1448 1449 if (error || newp == NULL) 1450 return error; 1451 1452 sc->sc_user_reg = *(int *)node.sysctl_data; 1453 return 0; 1454 } 1455 1456 static int 1457 sysctl_dbcool_reg_access(SYSCTLFN_ARGS) 1458 { 1459 struct sysctlnode node; 1460 struct dbcool_softc *sc; 1461 int reg, error; 1462 uint8_t chipreg; 1463 uint8_t newreg; 1464 1465 node = *rnode; 1466 sc = (struct dbcool_softc *)node.sysctl_data; 1467 chipreg = sc->sc_user_reg; 1468 1469 reg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1470 node.sysctl_data = ® 1471 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1472 1473 if (error || newp == NULL) 1474 return error; 1475 1476 newreg = *(int *)node.sysctl_data; 1477 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1478 return 0; 1479 } 1480 #endif /* DBCOOL_DEBUG */ 1481 1482 /* 1483 * Encode an index number and register number for use as a sysctl_num 1484 * so we can select the correct device register later. 1485 */ 1486 #define DBC_PWM_SYSCTL(seq, reg) ((seq << 8) | reg) 1487 1488 void 1489 dbcool_setup(device_t self) 1490 { 1491 struct dbcool_softc *sc = device_private(self); 1492 const struct sysctlnode *me = NULL; 1493 #ifdef DBCOOL_DEBUG 1494 struct sysctlnode *node = NULL; 1495 #endif 1496 uint8_t cfg_val, cfg_reg; 1497 int ret, error; 1498 1499 /* 1500 * Some chips are capable of reporting an extended temperature range 1501 * by default. On these models, config register 5 bit 0 can be set 1502 * to 1 for compatability with other chips that report 2s complement. 1503 */ 1504 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) { 1505 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADT7466_CONFIG1) & 0x80) 1506 sc->sc_temp_offset = 64; 1507 else 1508 sc->sc_temp_offset = 0; 1509 } else if (sc->sc_dc.dc_chip->flags & DBCFLAG_TEMPOFFSET) { 1510 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_CONFIG5_REG) & 1511 DBCOOL_CFG5_TWOSCOMP) 1512 sc->sc_temp_offset = 0; 1513 else 1514 sc->sc_temp_offset = 64; 1515 } else 1516 sc->sc_temp_offset = 0; 1517 1518 /* Determine Vcc for this chip */ 1519 sc->sc_supply_voltage = dbcool_supply_voltage(sc); 1520 1521 ret = sysctl_createv(&sc->sc_sysctl_log, 0, NULL, &me, 1522 CTLFLAG_READWRITE, 1523 CTLTYPE_NODE, device_xname(self), NULL, 1524 NULL, 0, NULL, 0, 1525 CTL_HW, CTL_CREATE, CTL_EOL); 1526 if (ret == 0) 1527 sc->sc_root_sysctl_num = me->sysctl_num; 1528 else 1529 sc->sc_root_sysctl_num = 0; 1530 1531 aprint_debug_dev(self, 1532 "Supply voltage %"PRId64".%06"PRId64"V, %s temp range\n", 1533 sc->sc_supply_voltage / 1000000, 1534 sc->sc_supply_voltage % 1000000, 1535 sc->sc_temp_offset ? "extended" : "normal"); 1536 1537 /* Create the sensors for this device */ 1538 sc->sc_sme = sysmon_envsys_create(); 1539 if (dbcool_setup_sensors(sc)) 1540 goto out; 1541 1542 if (sc->sc_root_sysctl_num != 0) { 1543 /* If supported, create sysctl tree for fan PWM controllers */ 1544 if (sc->sc_dc.dc_chip->power != NULL) 1545 dbcool_setup_controllers(sc); 1546 1547 #ifdef DBCOOL_DEBUG 1548 ret = sysctl_createv(&sc->sc_sysctl_log, 0, NULL, 1549 (void *)&node, 1550 CTLFLAG_READWRITE, CTLTYPE_INT, "reg_select", NULL, 1551 sysctl_dbcool_reg_select, 1552 0, (void *)sc, sizeof(int), 1553 CTL_HW, me->sysctl_num, CTL_CREATE, CTL_EOL); 1554 if (node != NULL) 1555 node->sysctl_data = sc; 1556 1557 ret = sysctl_createv(&sc->sc_sysctl_log, 0, NULL, 1558 (void *)&node, 1559 CTLFLAG_READWRITE, CTLTYPE_INT, "reg_access", NULL, 1560 sysctl_dbcool_reg_access, 1561 0, (void *)sc, sizeof(int), 1562 CTL_HW, me->sysctl_num, CTL_CREATE, CTL_EOL); 1563 if (node != NULL) 1564 node->sysctl_data = sc; 1565 #endif /* DBCOOL_DEBUG */ 1566 } 1567 1568 /* 1569 * Read and rewrite config register to activate device 1570 */ 1571 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 1572 cfg_reg = DBCOOL_ADM1030_CFG1; 1573 else if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) 1574 cfg_reg = DBCOOL_ADT7466_CONFIG1; 1575 else 1576 cfg_reg = DBCOOL_CONFIG1_REG; 1577 cfg_val = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_CONFIG1_REG); 1578 if ((cfg_val & DBCOOL_CFG1_START) == 0) { 1579 cfg_val |= DBCOOL_CFG1_START; 1580 sc->sc_dc.dc_writereg(&sc->sc_dc, cfg_reg, cfg_val); 1581 } 1582 if (dbcool_islocked(sc)) 1583 aprint_normal_dev(self, "configuration locked\n"); 1584 1585 sc->sc_sme->sme_name = device_xname(self); 1586 sc->sc_sme->sme_cookie = sc; 1587 sc->sc_sme->sme_refresh = dbcool_refresh; 1588 sc->sc_sme->sme_set_limits = dbcool_set_limits; 1589 sc->sc_sme->sme_get_limits = dbcool_get_limits; 1590 1591 if ((error = sysmon_envsys_register(sc->sc_sme)) != 0) { 1592 aprint_error_dev(self, 1593 "unable to register with sysmon (%d)\n", error); 1594 goto out; 1595 } 1596 1597 return; 1598 1599 out: 1600 sysmon_envsys_destroy(sc->sc_sme); 1601 } 1602 1603 static int 1604 dbcool_setup_sensors(struct dbcool_softc *sc) 1605 { 1606 int i; 1607 int error = 0; 1608 uint8_t vid_reg, vid_val; 1609 struct chip_id *chip = sc->sc_dc.dc_chip; 1610 1611 for (i=0; chip->table[i].type != DBC_EOF; i++) { 1612 if (i < DBCOOL_MAXSENSORS) 1613 sc->sc_sysctl_num[i] = -1; 1614 else if (chip->table[i].type != DBC_CTL) { 1615 aprint_normal_dev(sc->sc_dev, "chip table too big!\n"); 1616 break; 1617 } 1618 switch (chip->table[i].type) { 1619 case DBC_TEMP: 1620 sc->sc_sensor[i].units = ENVSYS_STEMP; 1621 sc->sc_sensor[i].state = ENVSYS_SINVALID; 1622 sc->sc_sensor[i].flags |= ENVSYS_FMONLIMITS; 1623 error = dbcool_attach_sensor(sc, i); 1624 break; 1625 case DBC_VOLT: 1626 /* 1627 * If 12V-In pin has been reconfigured as 6th bit 1628 * of VID code, don't create a 12V-In sensor 1629 */ 1630 if ((chip->flags & DBCFLAG_HAS_VID_SEL) && 1631 (chip->table[i].reg.val_reg == DBCOOL_12VIN) && 1632 (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VID_REG) & 1633 0x80)) 1634 break; 1635 1636 sc->sc_sensor[i].units = ENVSYS_SVOLTS_DC; 1637 sc->sc_sensor[i].state = ENVSYS_SINVALID; 1638 sc->sc_sensor[i].flags |= ENVSYS_FMONLIMITS; 1639 error = dbcool_attach_sensor(sc, i); 1640 break; 1641 case DBC_FAN: 1642 sc->sc_sensor[i].units = ENVSYS_SFANRPM; 1643 sc->sc_sensor[i].state = ENVSYS_SINVALID; 1644 sc->sc_sensor[i].flags |= ENVSYS_FMONLIMITS; 1645 error = dbcool_attach_sensor(sc, i); 1646 break; 1647 case DBC_VID: 1648 sc->sc_sensor[i].units = ENVSYS_INTEGER; 1649 sc->sc_sensor[i].state = ENVSYS_SINVALID; 1650 sc->sc_sensor[i].flags |= ENVSYS_FMONNOTSUPP; 1651 1652 /* retrieve 5- or 6-bit value */ 1653 vid_reg = chip->table[i].reg.val_reg; 1654 vid_val = sc->sc_dc.dc_readreg(&sc->sc_dc, vid_reg); 1655 if (chip->flags & DBCFLAG_HAS_VID_SEL) 1656 vid_val &= 0x3f; 1657 else 1658 vid_val &= 0x1f; 1659 sc->sc_sensor[i].value_cur = vid_val; 1660 1661 error = dbcool_attach_sensor(sc, i); 1662 break; 1663 case DBC_CTL: 1664 error = dbcool_attach_temp_control(sc, i, chip); 1665 if (error) { 1666 aprint_error_dev(sc->sc_dev, 1667 "attach index %d failed %d\n", 1668 i, error); 1669 error = 0; 1670 } 1671 break; 1672 default: 1673 aprint_error_dev(sc->sc_dev, 1674 "sensor_table index %d has bad type %d\n", 1675 i, chip->table[i].type); 1676 break; 1677 } 1678 if (error) 1679 break; 1680 } 1681 return error; 1682 } 1683 1684 static int 1685 dbcool_attach_sensor(struct dbcool_softc *sc, int idx) 1686 { 1687 int name_index; 1688 int error = 0; 1689 1690 name_index = sc->sc_dc.dc_chip->table[idx].name_index; 1691 strlcpy(sc->sc_sensor[idx].desc, dbc_sensor_names[name_index], 1692 sizeof(sc->sc_sensor[idx].desc)); 1693 sc->sc_regs[idx] = &sc->sc_dc.dc_chip->table[idx].reg; 1694 sc->sc_nom_volt[idx] = sc->sc_dc.dc_chip->table[idx].nom_volt_index; 1695 1696 error = sysmon_envsys_sensor_attach(sc->sc_sme, &sc->sc_sensor[idx]); 1697 return error; 1698 } 1699 1700 static int 1701 dbcool_attach_temp_control(struct dbcool_softc *sc, int idx, 1702 struct chip_id *chip) 1703 { 1704 const struct sysctlnode *me2 = NULL, *node; 1705 int j, ret, sysctl_index, rw_flag; 1706 uint8_t sysctl_reg; 1707 char name[SYSCTL_NAMELEN]; 1708 1709 /* Search for the corresponding temp sensor */ 1710 for (j = 0; j < idx; j++) { 1711 if (j >= DBCOOL_MAXSENSORS || chip->table[j].type != DBC_TEMP) 1712 continue; 1713 if (chip->table[j].name_index == chip->table[idx].name_index) 1714 break; 1715 } 1716 if (j >= idx) /* Temp sensor not found */ 1717 return ENOENT; 1718 1719 /* create sysctl node for the sensor if not one already there */ 1720 if (sc->sc_sysctl_num[j] == -1) { 1721 ret = sysctl_createv(&sc->sc_sysctl_log, 0, NULL, &me2, 1722 CTLFLAG_READWRITE, 1723 CTLTYPE_NODE, sc->sc_sensor[j].desc, NULL, 1724 NULL, 0, NULL, 0, 1725 CTL_HW, sc->sc_root_sysctl_num, CTL_CREATE, 1726 CTL_EOL); 1727 if (me2 != NULL) 1728 sc->sc_sysctl_num[j] = me2->sysctl_num; 1729 else 1730 return ret; 1731 } 1732 /* add sysctl leaf node for this control variable */ 1733 sysctl_index = chip->table[idx].sysctl_index; 1734 sysctl_reg = chip->table[idx].reg.val_reg; 1735 strlcpy(name, dbc_sysctl_table[sysctl_index].name, sizeof(name)); 1736 if (dbc_sysctl_table[sysctl_index].lockable && dbcool_islocked(sc)) 1737 rw_flag = CTLFLAG_READONLY | CTLFLAG_OWNDESC; 1738 else 1739 rw_flag = CTLFLAG_READWRITE | CTLFLAG_OWNDESC; 1740 ret = sysctl_createv(&sc->sc_sysctl_log, 0, NULL, &node, rw_flag, 1741 CTLTYPE_INT, name, 1742 SYSCTL_DESCR(dbc_sysctl_table[sysctl_index].desc), 1743 dbc_sysctl_table[sysctl_index].helper, 1744 0, (void *)sc, sizeof(int), 1745 CTL_HW, sc->sc_root_sysctl_num, 1746 sc->sc_sysctl_num[j], 1747 DBC_PWM_SYSCTL(idx, sysctl_reg), CTL_EOL); 1748 1749 return ret; 1750 } 1751 1752 static void 1753 dbcool_setup_controllers(struct dbcool_softc *sc) 1754 { 1755 int i, j, ret, rw_flag; 1756 uint8_t sysctl_reg; 1757 struct chip_id *chip = sc->sc_dc.dc_chip; 1758 const struct sysctlnode *me2 = NULL; 1759 const struct sysctlnode *node = NULL; 1760 char name[SYSCTL_NAMELEN]; 1761 1762 for (i = 0; chip->power[i].desc != NULL; i++) { 1763 snprintf(name, sizeof(name), "fan_ctl_%d", i); 1764 ret = sysctl_createv(&sc->sc_sysctl_log, 0, NULL, &me2, 1765 CTLFLAG_READWRITE | CTLFLAG_OWNDESC, 1766 CTLTYPE_NODE, name, NULL, 1767 NULL, 0, NULL, 0, 1768 CTL_HW, sc->sc_root_sysctl_num, CTL_CREATE, CTL_EOL); 1769 1770 for (j = DBC_PWM_BEHAVIOR; j < DBC_PWM_LAST_PARAM; j++) { 1771 if (j == DBC_PWM_MAX_DUTY && 1772 (chip->flags & DBCFLAG_HAS_MAXDUTY) == 0) 1773 continue; 1774 sysctl_reg = chip->power[i].power_regs[j]; 1775 if (sysctl_reg == DBCOOL_NO_REG) 1776 continue; 1777 strlcpy(name, dbc_sysctl_table[j].name, sizeof(name)); 1778 if (dbc_sysctl_table[j].lockable && dbcool_islocked(sc)) 1779 rw_flag = CTLFLAG_READONLY | CTLFLAG_OWNDESC; 1780 else 1781 rw_flag = CTLFLAG_READWRITE | CTLFLAG_OWNDESC; 1782 ret = (sysctl_createv)(&sc->sc_sysctl_log, 0, NULL, 1783 &node, rw_flag, 1784 (j == DBC_PWM_BEHAVIOR)? 1785 CTLTYPE_STRING:CTLTYPE_INT, 1786 name, 1787 SYSCTL_DESCR(dbc_sysctl_table[j].desc), 1788 dbc_sysctl_table[j].helper, 1789 0, sc, 1790 ( j == DBC_PWM_BEHAVIOR)? 1791 sizeof(dbcool_cur_behav): sizeof(int), 1792 CTL_HW, sc->sc_root_sysctl_num, me2->sysctl_num, 1793 DBC_PWM_SYSCTL(j, sysctl_reg), CTL_EOL); 1794 } 1795 } 1796 } 1797 1798 static void 1799 dbcool_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 1800 { 1801 struct dbcool_softc *sc=sme->sme_cookie; 1802 int i, nom_volt_idx, cur; 1803 struct reg_list *reg; 1804 1805 i = edata->sensor; 1806 reg = sc->sc_regs[i]; 1807 1808 edata->state = ENVSYS_SVALID; 1809 switch (edata->units) 1810 { 1811 case ENVSYS_STEMP: 1812 cur = dbcool_read_temp(sc, reg->val_reg, true); 1813 break; 1814 case ENVSYS_SVOLTS_DC: 1815 nom_volt_idx = sc->sc_nom_volt[i]; 1816 cur = dbcool_read_volt(sc, reg->val_reg, nom_volt_idx, 1817 true); 1818 break; 1819 case ENVSYS_SFANRPM: 1820 cur = dbcool_read_rpm(sc, reg->val_reg); 1821 break; 1822 case ENVSYS_INTEGER: 1823 return; 1824 default: 1825 edata->state = ENVSYS_SINVALID; 1826 return; 1827 } 1828 1829 if (cur == 0 && (edata->units != ENVSYS_SFANRPM)) 1830 edata->state = ENVSYS_SINVALID; 1831 1832 /* 1833 * If fan is "stalled" but has no low limit, treat 1834 * it as though the fan is not installed. 1835 */ 1836 else if (edata->units == ENVSYS_SFANRPM && cur == 0 && 1837 !(edata->upropset & (PROP_CRITMIN | PROP_WARNMIN))) 1838 edata->state = ENVSYS_SINVALID; 1839 1840 edata->value_cur = cur; 1841 } 1842 1843 int 1844 dbcool_chip_ident(struct dbcool_chipset *dc) 1845 { 1846 /* verify this is a supported dbCool chip */ 1847 uint8_t c_id, d_id, r_id; 1848 int i; 1849 1850 c_id = dc->dc_readreg(dc, DBCOOL_COMPANYID_REG); 1851 d_id = dc->dc_readreg(dc, DBCOOL_DEVICEID_REG); 1852 r_id = dc->dc_readreg(dc, DBCOOL_REVISION_REG); 1853 1854 /* The EMC6D103S only supports read_byte and since dc->dc_chip is 1855 * NULL when we call dc->dc_readreg above we use 1856 * send_byte/receive_byte which doesn't work. 1857 * 1858 * So if we only get 0's back then try again with dc->dc_chip 1859 * set to the EMC6D103S_DEVICEID and which doesn't have 1860 * DBCFLAG_NO_READBYTE set so read_byte will be used 1861 */ 1862 if ((c_id == 0) && (d_id == 0) && (r_id == 0)) { 1863 for (i = 0; chip_table[i].company != 0; i++) 1864 if ((SMSC_COMPANYID == chip_table[i].company) && 1865 (EMC6D103S_DEVICEID == chip_table[i].device)) { 1866 dc->dc_chip = &chip_table[i]; 1867 break; 1868 } 1869 c_id = dc->dc_readreg(dc, DBCOOL_COMPANYID_REG); 1870 d_id = dc->dc_readreg(dc, DBCOOL_DEVICEID_REG); 1871 r_id = dc->dc_readreg(dc, DBCOOL_REVISION_REG); 1872 } 1873 1874 for (i = 0; chip_table[i].company != 0; i++) 1875 if ((c_id == chip_table[i].company) && 1876 (d_id == chip_table[i].device || 1877 chip_table[i].device == 0xff) && 1878 (r_id == chip_table[i].rev || 1879 chip_table[i].rev == 0xff)) { 1880 dc->dc_chip = &chip_table[i]; 1881 return i; 1882 } 1883 1884 aprint_verbose("dbcool_chip_ident: addr 0x%02x c_id 0x%02x d_id 0x%02x" 1885 " r_id 0x%02x: No match.\n", dc->dc_addr, c_id, d_id, 1886 r_id); 1887 1888 return -1; 1889 } 1890 1891 /* 1892 * Retrieve sensor limits from the chip registers 1893 */ 1894 static void 1895 dbcool_get_limits(struct sysmon_envsys *sme, envsys_data_t *edata, 1896 sysmon_envsys_lim_t *limits, uint32_t *props) 1897 { 1898 int index = edata->sensor; 1899 struct dbcool_softc *sc = sme->sme_cookie; 1900 1901 *props &= ~(PROP_CRITMIN | PROP_CRITMAX); 1902 switch (edata->units) { 1903 case ENVSYS_STEMP: 1904 dbcool_get_temp_limits(sc, index, limits, props); 1905 break; 1906 case ENVSYS_SVOLTS_DC: 1907 dbcool_get_volt_limits(sc, index, limits, props); 1908 break; 1909 case ENVSYS_SFANRPM: 1910 dbcool_get_fan_limits(sc, index, limits, props); 1911 1912 /* FALLTHROUGH */ 1913 default: 1914 break; 1915 } 1916 *props &= ~PROP_DRIVER_LIMITS; 1917 1918 /* If both limits provided, make sure they're sane */ 1919 if ((*props & PROP_CRITMIN) && 1920 (*props & PROP_CRITMAX) && 1921 (limits->sel_critmin >= limits->sel_critmax)) 1922 *props &= ~(PROP_CRITMIN | PROP_CRITMAX); 1923 1924 /* 1925 * If this is the first time through, save these values 1926 * in case user overrides them and then requests a reset. 1927 */ 1928 if (sc->sc_defprops[index] == 0) { 1929 sc->sc_defprops[index] = *props | PROP_DRIVER_LIMITS; 1930 sc->sc_deflims[index] = *limits; 1931 } 1932 } 1933 1934 static void 1935 dbcool_get_temp_limits(struct dbcool_softc *sc, int idx, 1936 sysmon_envsys_lim_t *lims, uint32_t *props) 1937 { 1938 struct reg_list *reg = sc->sc_regs[idx]; 1939 uint8_t lo_lim, hi_lim; 1940 1941 lo_lim = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->lo_lim_reg); 1942 hi_lim = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->hi_lim_reg); 1943 1944 if (sc->sc_temp_offset) { 1945 if (lo_lim > 0x01) { 1946 lims->sel_critmin = lo_lim - sc->sc_temp_offset; 1947 *props |= PROP_CRITMIN; 1948 } 1949 if (hi_lim != 0xff) { 1950 lims->sel_critmax = hi_lim - sc->sc_temp_offset; 1951 *props |= PROP_CRITMAX; 1952 } 1953 } else { 1954 if (lo_lim != 0x80 && lo_lim != 0x81) { 1955 lims->sel_critmin = (int8_t)lo_lim; 1956 *props |= PROP_CRITMIN; 1957 } 1958 1959 if (hi_lim != 0x7f) { 1960 lims->sel_critmax = (int8_t)hi_lim; 1961 *props |= PROP_CRITMAX; 1962 } 1963 } 1964 1965 /* Convert temp limits to microKelvin */ 1966 lims->sel_critmin *= 1000000; 1967 lims->sel_critmin += 273150000; 1968 lims->sel_critmax *= 1000000; 1969 lims->sel_critmax += 273150000; 1970 } 1971 1972 static void 1973 dbcool_get_volt_limits(struct dbcool_softc *sc, int idx, 1974 sysmon_envsys_lim_t *lims, uint32_t *props) 1975 { 1976 struct reg_list *reg = sc->sc_regs[idx]; 1977 int64_t limit; 1978 int nom; 1979 1980 nom = nominal_voltages[sc->sc_dc.dc_chip->table[idx].nom_volt_index]; 1981 if (nom < 0) 1982 nom = dbcool_supply_voltage(sc); 1983 nom *= 1000000; /* scale for microvolts */ 1984 1985 limit = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->lo_lim_reg); 1986 if (limit != 0x00 && limit != 0xff) { 1987 limit *= nom; 1988 limit /= 0xc0; 1989 lims->sel_critmin = limit; 1990 *props |= PROP_CRITMIN; 1991 } 1992 limit = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->hi_lim_reg); 1993 if (limit != 0x00 && limit != 0xff) { 1994 limit *= nom; 1995 limit /= 0xc0; 1996 lims->sel_critmax = limit; 1997 *props |= PROP_CRITMAX; 1998 } 1999 } 2000 2001 static void 2002 dbcool_get_fan_limits(struct dbcool_softc *sc, int idx, 2003 sysmon_envsys_lim_t *lims, uint32_t *props) 2004 { 2005 struct reg_list *reg = sc->sc_regs[idx]; 2006 int32_t limit; 2007 2008 limit = dbcool_read_rpm(sc, reg->lo_lim_reg); 2009 if (limit) { 2010 lims->sel_critmin = limit; 2011 *props |= PROP_CRITMIN; 2012 } 2013 } 2014 2015 /* 2016 * Update sensor limits in the chip registers 2017 */ 2018 static void 2019 dbcool_set_limits(struct sysmon_envsys *sme, envsys_data_t *edata, 2020 sysmon_envsys_lim_t *limits, uint32_t *props) 2021 { 2022 int index = edata->sensor; 2023 struct dbcool_softc *sc = sme->sme_cookie; 2024 2025 if (limits == NULL) { 2026 limits = &sc->sc_deflims[index]; 2027 props = &sc->sc_defprops[index]; 2028 } 2029 switch (edata->units) { 2030 case ENVSYS_STEMP: 2031 dbcool_set_temp_limits(sc, index, limits, props); 2032 break; 2033 case ENVSYS_SVOLTS_DC: 2034 dbcool_set_volt_limits(sc, index, limits, props); 2035 break; 2036 case ENVSYS_SFANRPM: 2037 dbcool_set_fan_limits(sc, index, limits, props); 2038 2039 /* FALLTHROUGH */ 2040 default: 2041 break; 2042 } 2043 *props &= ~PROP_DRIVER_LIMITS; 2044 } 2045 2046 static void 2047 dbcool_set_temp_limits(struct dbcool_softc *sc, int idx, 2048 sysmon_envsys_lim_t *lims, uint32_t *props) 2049 { 2050 struct reg_list *reg = sc->sc_regs[idx]; 2051 int32_t limit; 2052 2053 if (*props & PROP_CRITMIN) { 2054 limit = lims->sel_critmin - 273150000; 2055 limit /= 1000000; 2056 if (sc->sc_temp_offset) { 2057 limit += sc->sc_temp_offset; 2058 if (limit < 0) 2059 limit = 0; 2060 else if (limit > 255) 2061 limit = 255; 2062 } else { 2063 if (limit < -127) 2064 limit = -127; 2065 else if (limit > 127) 2066 limit = 127; 2067 } 2068 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, 2069 (uint8_t)limit); 2070 } else if (*props & PROP_DRIVER_LIMITS) { 2071 if (sc->sc_temp_offset) 2072 limit = 0x00; 2073 else 2074 limit = 0x80; 2075 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, 2076 (uint8_t)limit); 2077 } 2078 2079 if (*props & PROP_CRITMAX) { 2080 limit = lims->sel_critmax - 273150000; 2081 limit /= 1000000; 2082 if (sc->sc_temp_offset) { 2083 limit += sc->sc_temp_offset; 2084 if (limit < 0) 2085 limit = 0; 2086 else if (limit > 255) 2087 limit = 255; 2088 } else { 2089 if (limit < -127) 2090 limit = -127; 2091 else if (limit > 127) 2092 limit = 127; 2093 } 2094 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg, 2095 (uint8_t)limit); 2096 } else if (*props & PROP_DRIVER_LIMITS) { 2097 if (sc->sc_temp_offset) 2098 limit = 0xff; 2099 else 2100 limit = 0x7f; 2101 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg, 2102 (uint8_t)limit); 2103 } 2104 } 2105 2106 static void 2107 dbcool_set_volt_limits(struct dbcool_softc *sc, int idx, 2108 sysmon_envsys_lim_t *lims, uint32_t *props) 2109 { 2110 struct reg_list *reg = sc->sc_regs[idx]; 2111 int64_t limit; 2112 int nom; 2113 2114 nom = nominal_voltages[sc->sc_dc.dc_chip->table[idx].nom_volt_index]; 2115 if (nom < 0) 2116 nom = dbcool_supply_voltage(sc); 2117 nom *= 1000000; /* scale for microvolts */ 2118 2119 if (*props & PROP_CRITMIN) { 2120 limit = lims->sel_critmin; 2121 limit *= 0xc0; 2122 limit /= nom; 2123 if (limit > 0xff) 2124 limit = 0xff; 2125 else if (limit < 0) 2126 limit = 0; 2127 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, limit); 2128 } else if (*props & PROP_DRIVER_LIMITS) 2129 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, 0); 2130 2131 if (*props & PROP_CRITMAX) { 2132 limit = lims->sel_critmax; 2133 limit *= 0xc0; 2134 limit /= nom; 2135 if (limit > 0xff) 2136 limit = 0xff; 2137 else if (limit < 0) 2138 limit = 0; 2139 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg, limit); 2140 } else if (*props & PROP_DRIVER_LIMITS) 2141 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg, 0xff); 2142 } 2143 2144 static void 2145 dbcool_set_fan_limits(struct dbcool_softc *sc, int idx, 2146 sysmon_envsys_lim_t *lims, uint32_t *props) 2147 { 2148 struct reg_list *reg = sc->sc_regs[idx]; 2149 int32_t limit, dividend; 2150 2151 if (*props & PROP_CRITMIN) { 2152 limit = lims->sel_critmin; 2153 if (limit == 0) 2154 limit = 0xffff; 2155 else { 2156 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 2157 dividend = 11250 * 60; 2158 else 2159 dividend = 90000 * 60; 2160 limit = limit / dividend; 2161 if (limit > 0xffff) 2162 limit = 0xffff; 2163 } 2164 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, 2165 limit & 0xff); 2166 limit >>= 8; 2167 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg + 1, 2168 limit & 0xff); 2169 } else if (*props & PROP_DRIVER_LIMITS) { 2170 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, 0xff); 2171 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg + 1, 0xff); 2172 } 2173 } 2174 2175 MODULE(MODULE_CLASS_DRIVER, dbcool, "iic"); 2176 2177 #ifdef _MODULE 2178 #include "ioconf.c" 2179 #endif 2180 2181 static int 2182 dbcool_modcmd(modcmd_t cmd, void *opaque) 2183 { 2184 int error = 0; 2185 #ifdef _MODULE 2186 static struct sysctllog *dbcool_sysctl_clog; 2187 #endif 2188 2189 switch (cmd) { 2190 case MODULE_CMD_INIT: 2191 #ifdef _MODULE 2192 error = config_init_component(cfdriver_ioconf_dbcool, 2193 cfattach_ioconf_dbcool, cfdata_ioconf_dbcool); 2194 sysctl_dbcoolsetup(&dbcool_sysctl_clog); 2195 #endif 2196 return error; 2197 case MODULE_CMD_FINI: 2198 #ifdef _MODULE 2199 error = config_fini_component(cfdriver_ioconf_dbcool, 2200 cfattach_ioconf_dbcool, cfdata_ioconf_dbcool); 2201 sysctl_teardown(&dbcool_sysctl_clog); 2202 #endif 2203 return error; 2204 default: 2205 return ENOTTY; 2206 } 2207 } 2208
Indexes created Thu Sep 25 06:09:39 GMT 2025