dbcool.c revision 1.43
1 /* $NetBSD: dbcool.c,v 1.43 2015/04/23 23:23:00 pgoyette Exp $ */ 2 3 /*- 4 * Copyright (c) 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Goyette 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * a driver for the dbCool(tm) family of environmental controllers 34 * 35 * Data sheets for the various supported chips are available at 36 * 37 * http://www.onsemi.com/pub/Collateral/ADM1027-D.PDF 38 * http://www.onsemi.com/pub/Collateral/ADM1030-D.PDF 39 * http://www.onsemi.com/pub/Collateral/ADT7463-D.PDF 40 * http://www.onsemi.com/pub/Collateral/ADT7466.PDF 41 * http://www.onsemi.com/pub/Collateral/ADT7467-D.PDF 42 * http://www.onsemi.com/pub/Collateral/ADT7468-D.PDF 43 * http://www.onsemi.com/pub/Collateral/ADT7473-D.PDF 44 * http://www.onsemi.com/pub/Collateral/ADT7475-D.PDF 45 * http://www.onsemi.com/pub/Collateral/ADT7476-D.PDF 46 * http://www.onsemi.com/pub/Collateral/ADT7490-D.PDF 47 * http://www.smsc.com/media/Downloads_Public/Data_Sheets/6d103s.pdf 48 * 49 * (URLs are correct as of October 5, 2008) 50 */ 51 52 #include <sys/cdefs.h> 53 __KERNEL_RCSID(0, "$NetBSD: dbcool.c,v 1.43 2015/04/23 23:23:00 pgoyette Exp $"); 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/kernel.h> 58 #include <sys/device.h> 59 #include <sys/malloc.h> 60 #include <sys/sysctl.h> 61 #include <sys/module.h> 62 63 #include <dev/i2c/dbcool_var.h> 64 #include <dev/i2c/dbcool_reg.h> 65 66 /* Config interface */ 67 static int dbcool_match(device_t, cfdata_t, void *); 68 static void dbcool_attach(device_t, device_t, void *); 69 static int dbcool_detach(device_t, int); 70 71 /* Device attributes */ 72 static int dbcool_supply_voltage(struct dbcool_softc *); 73 static bool dbcool_islocked(struct dbcool_softc *); 74 75 /* Sensor read functions */ 76 static void dbcool_refresh(struct sysmon_envsys *, envsys_data_t *); 77 static int dbcool_read_rpm(struct dbcool_softc *, uint8_t); 78 static int dbcool_read_temp(struct dbcool_softc *, uint8_t, bool); 79 static int dbcool_read_volt(struct dbcool_softc *, uint8_t, int, bool); 80 81 /* Sensor get/set limit functions */ 82 static void dbcool_get_limits(struct sysmon_envsys *, envsys_data_t *, 83 sysmon_envsys_lim_t *, uint32_t *); 84 static void dbcool_get_temp_limits(struct dbcool_softc *, int, 85 sysmon_envsys_lim_t *, uint32_t *); 86 static void dbcool_get_volt_limits(struct dbcool_softc *, int, 87 sysmon_envsys_lim_t *, uint32_t *); 88 static void dbcool_get_fan_limits(struct dbcool_softc *, int, 89 sysmon_envsys_lim_t *, uint32_t *); 90 91 static void dbcool_set_limits(struct sysmon_envsys *, envsys_data_t *, 92 sysmon_envsys_lim_t *, uint32_t *); 93 static void dbcool_set_temp_limits(struct dbcool_softc *, int, 94 sysmon_envsys_lim_t *, uint32_t *); 95 static void dbcool_set_volt_limits(struct dbcool_softc *, int, 96 sysmon_envsys_lim_t *, uint32_t *); 97 static void dbcool_set_fan_limits(struct dbcool_softc *, int, 98 sysmon_envsys_lim_t *, uint32_t *); 99 100 /* SYSCTL Helpers */ 101 SYSCTL_SETUP_PROTO(sysctl_dbcoolsetup); 102 static int sysctl_dbcool_temp(SYSCTLFN_PROTO); 103 static int sysctl_adm1030_temp(SYSCTLFN_PROTO); 104 static int sysctl_adm1030_trange(SYSCTLFN_PROTO); 105 static int sysctl_dbcool_duty(SYSCTLFN_PROTO); 106 static int sysctl_dbcool_behavior(SYSCTLFN_PROTO); 107 static int sysctl_dbcool_slope(SYSCTLFN_PROTO); 108 static int sysctl_dbcool_thyst(SYSCTLFN_PROTO); 109 110 /* Set-up subroutines */ 111 static void dbcool_setup_controllers(struct dbcool_softc *); 112 static int dbcool_setup_sensors(struct dbcool_softc *); 113 static int dbcool_attach_sensor(struct dbcool_softc *, int); 114 static int dbcool_attach_temp_control(struct dbcool_softc *, int, 115 struct chip_id *); 116 117 #ifdef DBCOOL_DEBUG 118 static int sysctl_dbcool_reg_select(SYSCTLFN_PROTO); 119 static int sysctl_dbcool_reg_access(SYSCTLFN_PROTO); 120 #endif /* DBCOOL_DEBUG */ 121 122 /* 123 * Descriptions for SYSCTL entries 124 */ 125 struct dbc_sysctl_info { 126 const char *name; 127 const char *desc; 128 bool lockable; 129 int (*helper)(SYSCTLFN_PROTO); 130 }; 131 132 static struct dbc_sysctl_info dbc_sysctl_table[] = { 133 /* 134 * The first several entries must remain in the same order as the 135 * corresponding entries in enum dbc_pwm_params 136 */ 137 { "behavior", "operating behavior and temp selector", 138 true, sysctl_dbcool_behavior }, 139 { "min_duty", "minimum fan controller PWM duty cycle", 140 true, sysctl_dbcool_duty }, 141 { "max_duty", "maximum fan controller PWM duty cycle", 142 true, sysctl_dbcool_duty }, 143 { "cur_duty", "current fan controller PWM duty cycle", 144 false, sysctl_dbcool_duty }, 145 146 /* 147 * The rest of these should be in the order in which they 148 * are to be stored in the sysctl tree; the table index is 149 * used as the high-order bits of the sysctl_num to maintain 150 * the sequence. 151 * 152 * If you rearrange the order of these items, be sure to 153 * update the sysctl_index in the XXX_sensor_table[] for 154 * the various chips! 155 */ 156 { "Trange", "temp slope/range to reach 100% duty cycle", 157 true, sysctl_dbcool_slope }, 158 { "Tmin", "temp at which to start fan controller", 159 true, sysctl_dbcool_temp }, 160 { "Ttherm", "temp at which THERM is asserted", 161 true, sysctl_dbcool_temp }, 162 { "Thyst", "temp hysteresis for stopping fan controller", 163 true, sysctl_dbcool_thyst }, 164 { "Tmin", "temp at which to start fan controller", 165 true, sysctl_adm1030_temp }, 166 { "Trange", "temp slope/range to reach 100% duty cycle", 167 true, sysctl_adm1030_trange }, 168 }; 169 170 static const char *dbc_sensor_names[] = { 171 "l_temp", "r1_temp", "r2_temp", "Vccp", "Vcc", "fan1", 172 "fan2", "fan3", "fan4", "AIN1", "AIN2", "V2dot5", 173 "V5", "V12", "Vtt", "Imon", "VID" 174 }; 175 176 /* 177 * Following table derived from product data-sheets 178 */ 179 static int64_t nominal_voltages[] = { 180 -1, /* Vcc can be either 3.3 or 5.0V 181 at 3/4 scale */ 182 2249939, /* Vccp 2.25V 3/4 scale */ 183 2497436, /* 2.5VIN 2.5V 3/4 scale */ 184 5002466, /* 5VIN 5V 3/4 scale */ 185 12000000, /* 12VIN 12V 3/4 scale */ 186 1690809, /* Vtt, Imon 2.25V full scale */ 187 1689600, /* AIN1, AIN2 2.25V full scale */ 188 0 189 }; 190 191 /* 192 * Sensor-type, { val-reg, hilim-reg, lolim-reg}, name-idx, sysctl-table-idx, 193 * nom-voltage-index 194 */ 195 struct dbcool_sensor ADT7490_sensor_table[] = { 196 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 197 DBCOOL_LOCAL_HIGHLIM, 198 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 199 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 200 DBCOOL_REMOTE1_HIGHLIM, 201 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 202 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 203 DBCOOL_REMOTE2_HIGHLIM, 204 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 205 { DBC_VOLT, { DBCOOL_VCCP, 206 DBCOOL_VCCP_HIGHLIM, 207 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 208 { DBC_VOLT, { DBCOOL_VCC, 209 DBCOOL_VCC_HIGHLIM, 210 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 211 { DBC_VOLT, { DBCOOL_25VIN, 212 DBCOOL_25VIN_HIGHLIM, 213 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 }, 214 { DBC_VOLT, { DBCOOL_5VIN, 215 DBCOOL_5VIN_HIGHLIM, 216 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 }, 217 { DBC_VOLT, { DBCOOL_12VIN, 218 DBCOOL_12VIN_HIGHLIM, 219 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 }, 220 { DBC_VOLT, { DBCOOL_VTT, 221 DBCOOL_VTT_HIGHLIM, 222 DBCOOL_VTT_LOWLIM }, 14, 0, 5 }, 223 { DBC_VOLT, { DBCOOL_IMON, 224 DBCOOL_IMON_HIGHLIM, 225 DBCOOL_IMON_LOWLIM }, 15, 0, 5 }, 226 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 227 DBCOOL_NO_REG, 228 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 229 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 230 DBCOOL_NO_REG, 231 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 232 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 233 DBCOOL_NO_REG, 234 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 235 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 236 DBCOOL_NO_REG, 237 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 238 { DBC_VID, { DBCOOL_VID_REG, 239 DBCOOL_NO_REG, 240 DBCOOL_NO_REG }, 16, 0, 0 }, 241 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 242 DBCOOL_NO_REG, 243 DBCOOL_NO_REG }, 0, 5, 0 }, 244 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 245 DBCOOL_NO_REG, 246 DBCOOL_NO_REG }, 0, 6, 0 }, 247 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 248 DBCOOL_NO_REG, 249 DBCOOL_NO_REG }, 0, 7, 0 }, 250 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 251 DBCOOL_NO_REG, 252 DBCOOL_NO_REG }, 1, 5, 0 }, 253 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 254 DBCOOL_NO_REG, 255 DBCOOL_NO_REG }, 1, 6, 0 }, 256 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 257 DBCOOL_NO_REG, 258 DBCOOL_NO_REG }, 1, 7, 0 }, 259 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 260 DBCOOL_NO_REG, 261 DBCOOL_NO_REG }, 2, 5, 0 }, 262 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 263 DBCOOL_NO_REG, 264 DBCOOL_NO_REG }, 2, 6, 0 }, 265 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 266 DBCOOL_NO_REG, 267 DBCOOL_NO_REG }, 2, 7, 0 }, 268 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 269 }; 270 271 struct dbcool_sensor ADT7476_sensor_table[] = { 272 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 273 DBCOOL_LOCAL_HIGHLIM, 274 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 275 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 276 DBCOOL_REMOTE1_HIGHLIM, 277 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 278 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 279 DBCOOL_REMOTE2_HIGHLIM, 280 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 281 { DBC_VOLT, { DBCOOL_VCCP, 282 DBCOOL_VCCP_HIGHLIM, 283 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 284 { DBC_VOLT, { DBCOOL_VCC, 285 DBCOOL_VCC_HIGHLIM, 286 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 287 { DBC_VOLT, { DBCOOL_25VIN, 288 DBCOOL_25VIN_HIGHLIM, 289 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 }, 290 { DBC_VOLT, { DBCOOL_5VIN, 291 DBCOOL_5VIN_HIGHLIM, 292 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 }, 293 { DBC_VOLT, { DBCOOL_12VIN, 294 DBCOOL_12VIN_HIGHLIM, 295 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 }, 296 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 297 DBCOOL_NO_REG, 298 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 299 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 300 DBCOOL_NO_REG, 301 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 302 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 303 DBCOOL_NO_REG, 304 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 305 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 306 DBCOOL_NO_REG, 307 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 308 { DBC_VID, { DBCOOL_VID_REG, 309 DBCOOL_NO_REG, 310 DBCOOL_NO_REG }, 16, 0, 0 }, 311 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 312 DBCOOL_NO_REG, 313 DBCOOL_NO_REG }, 0, 5, 0 }, 314 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 315 DBCOOL_NO_REG, 316 DBCOOL_NO_REG }, 0, 6, 0 }, 317 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 318 DBCOOL_NO_REG, 319 DBCOOL_NO_REG }, 0, 7, 0 }, 320 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 321 DBCOOL_NO_REG, 322 DBCOOL_NO_REG }, 1, 5, 0 }, 323 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 324 DBCOOL_NO_REG, 325 DBCOOL_NO_REG }, 1, 6, 0 }, 326 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 327 DBCOOL_NO_REG, 328 DBCOOL_NO_REG }, 1, 7, 0 }, 329 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 330 DBCOOL_NO_REG, 331 DBCOOL_NO_REG }, 2, 5, 0 }, 332 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 333 DBCOOL_NO_REG, 334 DBCOOL_NO_REG }, 2, 6, 0 }, 335 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 336 DBCOOL_NO_REG, 337 DBCOOL_NO_REG }, 2, 7, 0 }, 338 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 339 }; 340 341 struct dbcool_sensor ADT7475_sensor_table[] = { 342 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 343 DBCOOL_LOCAL_HIGHLIM, 344 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 345 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 346 DBCOOL_REMOTE1_HIGHLIM, 347 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 348 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 349 DBCOOL_REMOTE2_HIGHLIM, 350 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 351 { DBC_VOLT, { DBCOOL_VCCP, 352 DBCOOL_VCCP_HIGHLIM, 353 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 354 { DBC_VOLT, { DBCOOL_VCC, 355 DBCOOL_VCC_HIGHLIM, 356 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 357 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 358 DBCOOL_NO_REG, 359 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 360 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 361 DBCOOL_NO_REG, 362 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 363 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 364 DBCOOL_NO_REG, 365 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 366 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 367 DBCOOL_NO_REG, 368 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 369 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 370 DBCOOL_NO_REG, 371 DBCOOL_NO_REG }, 0, 5, 0 }, 372 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 373 DBCOOL_NO_REG, 374 DBCOOL_NO_REG }, 0, 6, 0 }, 375 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 376 DBCOOL_NO_REG, 377 DBCOOL_NO_REG }, 0, 7, 0 }, 378 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 379 DBCOOL_NO_REG, 380 DBCOOL_NO_REG }, 1, 5, 0 }, 381 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 382 DBCOOL_NO_REG, 383 DBCOOL_NO_REG }, 1, 6, 0 }, 384 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 385 DBCOOL_NO_REG, 386 DBCOOL_NO_REG }, 1, 7, 0 }, 387 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 388 DBCOOL_NO_REG, 389 DBCOOL_NO_REG }, 2, 5, 0 }, 390 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 391 DBCOOL_NO_REG, 392 DBCOOL_NO_REG }, 2, 6, 0 }, 393 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 394 DBCOOL_NO_REG, 395 DBCOOL_NO_REG }, 2, 7, 0 }, 396 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 397 }; 398 399 /* 400 * The registers of dbcool_power_control must be in the same order as 401 * in enum dbc_pwm_params 402 */ 403 struct dbcool_power_control ADT7475_power_table[] = { 404 { { DBCOOL_PWM1_CTL, DBCOOL_PWM1_MINDUTY, 405 DBCOOL_PWM1_MAXDUTY, DBCOOL_PWM1_CURDUTY }, 406 "fan_control_1" }, 407 { { DBCOOL_PWM2_CTL, DBCOOL_PWM2_MINDUTY, 408 DBCOOL_PWM2_MAXDUTY, DBCOOL_PWM2_CURDUTY }, 409 "fan_control_2" }, 410 { { DBCOOL_PWM3_CTL, DBCOOL_PWM3_MINDUTY, 411 DBCOOL_PWM3_MAXDUTY, DBCOOL_PWM3_CURDUTY }, 412 "fan_control_3" }, 413 { { 0, 0, 0, 0 }, NULL } 414 }; 415 416 struct dbcool_sensor ADT7466_sensor_table[] = { 417 { DBC_TEMP, { DBCOOL_ADT7466_LCL_TEMP_MSB, 418 DBCOOL_ADT7466_LCL_TEMP_HILIM, 419 DBCOOL_ADT7466_LCL_TEMP_LOLIM }, 0, 0, 0 }, 420 { DBC_TEMP, { DBCOOL_ADT7466_REM_TEMP_MSB, 421 DBCOOL_ADT7466_REM_TEMP_HILIM, 422 DBCOOL_ADT7466_REM_TEMP_LOLIM }, 1, 0, 0 }, 423 { DBC_VOLT, { DBCOOL_ADT7466_VCC, 424 DBCOOL_ADT7466_VCC_HILIM, 425 DBCOOL_ADT7466_VCC_LOLIM }, 4, 0, 0 }, 426 { DBC_VOLT, { DBCOOL_ADT7466_AIN1, 427 DBCOOL_ADT7466_AIN1_HILIM, 428 DBCOOL_ADT7466_AIN1_LOLIM }, 9, 0, 6 }, 429 { DBC_VOLT, { DBCOOL_ADT7466_AIN2, 430 DBCOOL_ADT7466_AIN2_HILIM, 431 DBCOOL_ADT7466_AIN2_LOLIM }, 10, 0, 6 }, 432 { DBC_FAN, { DBCOOL_ADT7466_FANA_LSB, 433 DBCOOL_NO_REG, 434 DBCOOL_ADT7466_FANA_LOLIM_LSB }, 5, 0, 0 }, 435 { DBC_FAN, { DBCOOL_ADT7466_FANB_LSB, 436 DBCOOL_NO_REG, 437 DBCOOL_ADT7466_FANB_LOLIM_LSB }, 6, 0, 0 }, 438 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 439 }; 440 441 struct dbcool_sensor ADM1027_sensor_table[] = { 442 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 443 DBCOOL_LOCAL_HIGHLIM, 444 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 445 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 446 DBCOOL_REMOTE1_HIGHLIM, 447 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 448 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 449 DBCOOL_REMOTE2_HIGHLIM, 450 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 451 { DBC_VOLT, { DBCOOL_VCCP, 452 DBCOOL_VCCP_HIGHLIM, 453 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 454 { DBC_VOLT, { DBCOOL_VCC, 455 DBCOOL_VCC_HIGHLIM, 456 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 457 { DBC_VOLT, { DBCOOL_25VIN, 458 DBCOOL_25VIN_HIGHLIM, 459 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 }, 460 { DBC_VOLT, { DBCOOL_5VIN, 461 DBCOOL_5VIN_HIGHLIM, 462 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 }, 463 { DBC_VOLT, { DBCOOL_12VIN, 464 DBCOOL_12VIN_HIGHLIM, 465 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 }, 466 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 467 DBCOOL_NO_REG, 468 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 469 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 470 DBCOOL_NO_REG, 471 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 472 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 473 DBCOOL_NO_REG, 474 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 475 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 476 DBCOOL_NO_REG, 477 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 478 { DBC_VID, { DBCOOL_VID_REG, 479 DBCOOL_NO_REG, 480 DBCOOL_NO_REG }, 16, 0, 0 }, 481 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 482 DBCOOL_NO_REG, 483 DBCOOL_NO_REG }, 0, 5, 0 }, 484 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 485 DBCOOL_NO_REG, 486 DBCOOL_NO_REG }, 0, 6, 0 }, 487 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 488 DBCOOL_NO_REG, 489 DBCOOL_NO_REG }, 0, 7, 0 }, 490 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 491 DBCOOL_NO_REG, 492 DBCOOL_NO_REG }, 1, 5, 0 }, 493 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 494 DBCOOL_NO_REG, 495 DBCOOL_NO_REG }, 1, 6, 0 }, 496 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 497 DBCOOL_NO_REG, 498 DBCOOL_NO_REG }, 1, 7, 0 }, 499 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 500 DBCOOL_NO_REG, 501 DBCOOL_NO_REG }, 2, 5, 0 }, 502 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 503 DBCOOL_NO_REG, 504 DBCOOL_NO_REG }, 2, 6, 0 }, 505 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 506 DBCOOL_NO_REG, 507 DBCOOL_NO_REG }, 2, 7, 0 }, 508 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 509 }; 510 511 struct dbcool_sensor ADM1030_sensor_table[] = { 512 { DBC_TEMP, { DBCOOL_ADM1030_L_TEMP, 513 DBCOOL_ADM1030_L_HI_LIM, 514 DBCOOL_ADM1030_L_LO_LIM }, 0, 0, 0 }, 515 { DBC_TEMP, { DBCOOL_ADM1030_R_TEMP, 516 DBCOOL_ADM1030_R_HI_LIM, 517 DBCOOL_ADM1030_R_LO_LIM }, 1, 0, 0 }, 518 { DBC_FAN, { DBCOOL_ADM1030_FAN_TACH, 519 DBCOOL_NO_REG, 520 DBCOOL_ADM1030_FAN_LO_LIM }, 5, 0, 0 }, 521 { DBC_CTL, { DBCOOL_ADM1030_L_TMIN, 522 DBCOOL_NO_REG, 523 DBCOOL_NO_REG }, 0, 8, 0 }, 524 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH, 525 DBCOOL_NO_REG, 526 DBCOOL_NO_REG }, 0, 9, 0 }, 527 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH, 528 DBCOOL_NO_REG, 529 DBCOOL_NO_REG }, 0, 6, 0 }, 530 { DBC_CTL, { DBCOOL_ADM1030_R_TMIN, 531 DBCOOL_NO_REG, 532 DBCOOL_NO_REG }, 1, 8, 0 }, 533 { DBC_CTL, { DBCOOL_ADM1030_R_TTHRESH, 534 DBCOOL_NO_REG, 535 DBCOOL_NO_REG }, 1, 9, 0 }, 536 { DBC_CTL, { DBCOOL_ADM1030_R_TTHRESH, 537 DBCOOL_NO_REG, 538 DBCOOL_NO_REG }, 1, 6, 0 }, 539 { DBC_EOF, {0, 0, 0 }, 0, 0, 0 } 540 }; 541 542 struct dbcool_power_control ADM1030_power_table[] = { 543 { { DBCOOL_ADM1030_CFG1, DBCOOL_NO_REG, DBCOOL_NO_REG, 544 DBCOOL_ADM1030_FAN_SPEED_CFG }, 545 "fan_control_1" }, 546 { { 0, 0, 0, 0 }, NULL } 547 }; 548 549 struct dbcool_sensor ADM1031_sensor_table[] = { 550 { DBC_TEMP, { DBCOOL_ADM1030_L_TEMP, 551 DBCOOL_ADM1030_L_HI_LIM, 552 DBCOOL_ADM1030_L_LO_LIM }, 0, 0, 0 }, 553 { DBC_TEMP, { DBCOOL_ADM1030_R_TEMP, 554 DBCOOL_ADM1030_R_HI_LIM, 555 DBCOOL_ADM1030_R_LO_LIM }, 1, 0, 0 }, 556 { DBC_TEMP, { DBCOOL_ADM1031_R2_TEMP, 557 DBCOOL_ADM1031_R2_HI_LIM, 558 DBCOOL_ADM1031_R2_LO_LIM }, 2, 0, 0 }, 559 { DBC_FAN, { DBCOOL_ADM1030_FAN_TACH, 560 DBCOOL_NO_REG, 561 DBCOOL_ADM1030_FAN_LO_LIM }, 5, 0, 0 }, 562 { DBC_FAN, { DBCOOL_ADM1031_FAN2_TACH, 563 DBCOOL_NO_REG, 564 DBCOOL_ADM1031_FAN2_LO_LIM }, 6, 0, 0 }, 565 { DBC_CTL, { DBCOOL_ADM1030_L_TMIN, 566 DBCOOL_NO_REG, 567 DBCOOL_NO_REG }, 0, 8, 0 }, 568 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH, 569 DBCOOL_NO_REG, 570 DBCOOL_NO_REG }, 0, 9, 0 }, 571 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH, 572 DBCOOL_NO_REG, 573 DBCOOL_NO_REG }, 0, 6, 0 }, 574 { DBC_CTL, { DBCOOL_ADM1030_R_TMIN, 575 DBCOOL_NO_REG, 576 DBCOOL_NO_REG }, 1, 8, 0 }, 577 { DBC_CTL, { DBCOOL_ADM1030_R_TTHRESH, 578 DBCOOL_NO_REG, 579 DBCOOL_NO_REG }, 1, 9, 0 }, 580 { DBC_CTL, { DBCOOL_ADM1030_R_TTHRESH, 581 DBCOOL_NO_REG, 582 DBCOOL_NO_REG }, 1, 6, 0 }, 583 { DBC_CTL, { DBCOOL_ADM1031_R2_TMIN, 584 DBCOOL_NO_REG, 585 DBCOOL_NO_REG }, 2, 8, 0 }, 586 { DBC_CTL, { DBCOOL_ADM1031_R2_TTHRESH, 587 DBCOOL_NO_REG, 588 DBCOOL_NO_REG }, 2, 9, 0 }, 589 { DBC_CTL, { DBCOOL_ADM1031_R2_TTHRESH, 590 DBCOOL_NO_REG, 591 DBCOOL_NO_REG }, 2, 6, 0 }, 592 { DBC_EOF, {0, 0, 0 }, 0, 0, 0 } 593 }; 594 595 struct dbcool_power_control ADM1031_power_table[] = { 596 { { DBCOOL_ADM1030_CFG1, DBCOOL_NO_REG, DBCOOL_NO_REG, 597 DBCOOL_ADM1030_FAN_SPEED_CFG }, 598 "fan_control_1" }, 599 { { DBCOOL_ADM1030_CFG1, DBCOOL_NO_REG, DBCOOL_NO_REG, 600 DBCOOL_ADM1030_FAN_SPEED_CFG }, 601 "fan_control_2" }, 602 { { 0, 0, 0, 0 }, NULL } 603 }; 604 605 struct dbcool_sensor EMC6D103S_sensor_table[] = { 606 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 607 DBCOOL_LOCAL_HIGHLIM, 608 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 609 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 610 DBCOOL_REMOTE1_HIGHLIM, 611 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 612 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 613 DBCOOL_REMOTE2_HIGHLIM, 614 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 615 { DBC_VOLT, { DBCOOL_VCCP, 616 DBCOOL_VCCP_HIGHLIM, 617 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 618 { DBC_VOLT, { DBCOOL_VCC, 619 DBCOOL_VCC_HIGHLIM, 620 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 621 { DBC_VOLT, { DBCOOL_25VIN, 622 DBCOOL_25VIN_HIGHLIM, 623 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 }, 624 { DBC_VOLT, { DBCOOL_5VIN, 625 DBCOOL_5VIN_HIGHLIM, 626 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 }, 627 { DBC_VOLT, { DBCOOL_12VIN, 628 DBCOOL_12VIN_HIGHLIM, 629 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 }, 630 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 631 DBCOOL_NO_REG, 632 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 633 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 634 DBCOOL_NO_REG, 635 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 636 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 637 DBCOOL_NO_REG, 638 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 639 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 640 DBCOOL_NO_REG, 641 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 642 { DBC_VID, { DBCOOL_VID_REG, 643 DBCOOL_NO_REG, 644 DBCOOL_NO_REG }, 16, 0, 0 }, 645 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 646 DBCOOL_NO_REG, 647 DBCOOL_NO_REG }, 0, 5, 0 }, 648 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 649 DBCOOL_NO_REG, 650 DBCOOL_NO_REG }, 0, 6, 0 }, 651 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 652 DBCOOL_NO_REG, 653 DBCOOL_NO_REG }, 1, 5, 0 }, 654 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 655 DBCOOL_NO_REG, 656 DBCOOL_NO_REG }, 1, 6, 0 }, 657 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 658 DBCOOL_NO_REG, 659 DBCOOL_NO_REG }, 2, 5, 0 }, 660 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 661 DBCOOL_NO_REG, 662 DBCOOL_NO_REG }, 2, 6, 0 }, 663 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 664 }; 665 666 struct chip_id chip_table[] = { 667 { DBCOOL_COMPANYID, ADT7490_DEVICEID, ADT7490_REV_ID, 668 ADT7490_sensor_table, ADT7475_power_table, 669 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_PECI, 670 90000 * 60, "ADT7490" }, 671 { DBCOOL_COMPANYID, ADT7476_DEVICEID, 0xff, 672 ADT7476_sensor_table, ADT7475_power_table, 673 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY, 674 90000 * 60, "ADT7476" }, 675 { DBCOOL_COMPANYID, ADT7475_DEVICEID, 0xff, 676 ADT7475_sensor_table, ADT7475_power_table, 677 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_SHDN, 678 90000 * 60, "ADT7475" }, 679 { DBCOOL_COMPANYID, ADT7473_DEVICEID, ADT7473_REV_ID1, 680 ADT7475_sensor_table, ADT7475_power_table, 681 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_SHDN, 682 90000 * 60, "ADT7460/ADT7463" }, 683 { DBCOOL_COMPANYID, ADT7473_DEVICEID, ADT7473_REV_ID2, 684 ADT7475_sensor_table, ADT7475_power_table, 685 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_SHDN, 686 90000 * 60, "ADT7463-1" }, 687 { DBCOOL_COMPANYID, ADT7468_DEVICEID, 0xff, 688 ADT7476_sensor_table, ADT7475_power_table, 689 DBCFLAG_TEMPOFFSET | DBCFLAG_MULTI_VCC | DBCFLAG_HAS_MAXDUTY | 690 DBCFLAG_4BIT_VER | DBCFLAG_HAS_SHDN, 691 90000 * 60, "ADT7467/ADT7468" }, 692 { DBCOOL_COMPANYID, ADT7466_DEVICEID, 0xff, 693 ADT7466_sensor_table, NULL, 694 DBCFLAG_ADT7466 | DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_SHDN, 695 82000 * 60, "ADT7466" }, 696 { DBCOOL_COMPANYID, ADT7463_DEVICEID, ADT7463_REV_ID1, 697 ADM1027_sensor_table, ADT7475_power_table, 698 DBCFLAG_MULTI_VCC | DBCFLAG_4BIT_VER | DBCFLAG_HAS_SHDN, 699 90000 * 60, "ADT7463" }, 700 { DBCOOL_COMPANYID, ADT7463_DEVICEID, ADT7463_REV_ID2, 701 ADM1027_sensor_table, ADT7475_power_table, 702 DBCFLAG_MULTI_VCC | DBCFLAG_4BIT_VER | DBCFLAG_HAS_SHDN | 703 DBCFLAG_HAS_VID_SEL, 704 90000 * 60, "ADT7463" }, 705 { DBCOOL_COMPANYID, ADM1027_DEVICEID, ADM1027_REV_ID, 706 ADM1027_sensor_table, ADT7475_power_table, 707 DBCFLAG_MULTI_VCC | DBCFLAG_4BIT_VER, 708 90000 * 60, "ADM1027" }, 709 { DBCOOL_COMPANYID, ADM1030_DEVICEID, 0xff, 710 ADM1030_sensor_table, ADM1030_power_table, 711 DBCFLAG_ADM1030 | DBCFLAG_NO_READBYTE, 712 11250 * 60, "ADM1030" }, 713 { DBCOOL_COMPANYID, ADM1031_DEVICEID, 0xff, 714 ADM1031_sensor_table, ADM1030_power_table, 715 DBCFLAG_ADM1030 | DBCFLAG_NO_READBYTE, 716 11250 * 60, "ADM1031" }, 717 { SMSC_COMPANYID, EMC6D103S_DEVICEID, EMC6D103S_REV_ID, 718 EMC6D103S_sensor_table, ADT7475_power_table, 719 DBCFLAG_4BIT_VER, 720 90000 * 60, "EMC6D103S" }, 721 { 0, 0, 0, NULL, NULL, 0, 0, NULL } 722 }; 723 724 static const char *behavior[] = { 725 "remote1", "local", "remote2", "full-speed", 726 "disabled", "local+remote2","all-temps", "manual" 727 }; 728 729 static char dbcool_cur_behav[16]; 730 731 CFATTACH_DECL_NEW(dbcool, sizeof(struct dbcool_softc), 732 dbcool_match, dbcool_attach, dbcool_detach, NULL); 733 734 int 735 dbcool_match(device_t parent, cfdata_t cf, void *aux) 736 { 737 struct i2c_attach_args *ia = aux; 738 struct dbcool_chipset dc; 739 dc.dc_tag = ia->ia_tag; 740 dc.dc_addr = ia->ia_addr; 741 dc.dc_chip = NULL; 742 dc.dc_readreg = dbcool_readreg; 743 dc.dc_writereg = dbcool_writereg; 744 745 /* no probing if we attach to iic, but verify chip id and address */ 746 if ((ia->ia_addr & DBCOOL_ADDRMASK) != DBCOOL_ADDR) 747 return 0; 748 if (dbcool_chip_ident(&dc) >= 0) 749 return 1; 750 751 return 0; 752 } 753 754 void 755 dbcool_attach(device_t parent, device_t self, void *aux) 756 { 757 struct dbcool_softc *sc = device_private(self); 758 struct i2c_attach_args *args = aux; 759 uint8_t ver; 760 761 sc->sc_dc.dc_addr = args->ia_addr; 762 sc->sc_dc.dc_tag = args->ia_tag; 763 sc->sc_dc.dc_chip = NULL; 764 sc->sc_dc.dc_readreg = dbcool_readreg; 765 sc->sc_dc.dc_writereg = dbcool_writereg; 766 (void)dbcool_chip_ident(&sc->sc_dc); 767 sc->sc_dev = self; 768 769 aprint_naive("\n"); 770 aprint_normal("\n"); 771 772 ver = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_REVISION_REG); 773 if (sc->sc_dc.dc_chip->flags & DBCFLAG_4BIT_VER) 774 if (sc->sc_dc.dc_chip->company == SMSC_COMPANYID) 775 { 776 aprint_normal_dev(self, "SMSC %s Controller " 777 "(rev 0x%02x, stepping 0x%02x)\n", sc->sc_dc.dc_chip->name, 778 ver >> 4, ver & 0x0f); 779 } else { 780 aprint_normal_dev(self, "%s dBCool(tm) Controller " 781 "(rev 0x%02x, stepping 0x%02x)\n", sc->sc_dc.dc_chip->name, 782 ver >> 4, ver & 0x0f); 783 } 784 else 785 aprint_normal_dev(self, "%s dBCool(tm) Controller " 786 "(rev 0x%04x)\n", sc->sc_dc.dc_chip->name, ver); 787 788 sc->sc_sysctl_log = NULL; 789 790 #ifdef _MODULE 791 sysctl_dbcoolsetup(&sc->sc_sysctl_log); 792 #endif 793 794 dbcool_setup(self); 795 796 if (!pmf_device_register(self, dbcool_pmf_suspend, dbcool_pmf_resume)) 797 aprint_error_dev(self, "couldn't establish power handler\n"); 798 } 799 800 static int 801 dbcool_detach(device_t self, int flags) 802 { 803 struct dbcool_softc *sc = device_private(self); 804 805 pmf_device_deregister(self); 806 807 sysmon_envsys_unregister(sc->sc_sme); 808 809 sysctl_teardown(&sc->sc_sysctl_log); 810 811 sc->sc_sme = NULL; 812 return 0; 813 } 814 815 /* On suspend, we save the state of the SHDN bit, then set it */ 816 bool dbcool_pmf_suspend(device_t dev, const pmf_qual_t *qual) 817 { 818 struct dbcool_softc *sc = device_private(dev); 819 uint8_t reg, bit, cfg; 820 821 if ((sc->sc_dc.dc_chip->flags & DBCFLAG_HAS_SHDN) == 0) 822 return true; 823 824 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) { 825 reg = DBCOOL_ADT7466_CONFIG2; 826 bit = DBCOOL_ADT7466_CFG2_SHDN; 827 } else { 828 reg = DBCOOL_CONFIG2_REG; 829 bit = DBCOOL_CFG2_SHDN; 830 } 831 cfg = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 832 sc->sc_suspend = cfg & bit; 833 cfg |= bit; 834 sc->sc_dc.dc_writereg(&sc->sc_dc, reg, cfg); 835 836 return true; 837 } 838 839 /* On resume, we restore the previous state of the SHDN bit (which 840 we saved in sc_suspend) */ 841 bool dbcool_pmf_resume(device_t dev, const pmf_qual_t *qual) 842 { 843 struct dbcool_softc *sc = device_private(dev); 844 uint8_t reg, cfg; 845 846 if ((sc->sc_dc.dc_chip->flags & DBCFLAG_HAS_SHDN) == 0) 847 return true; 848 849 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) { 850 reg = DBCOOL_ADT7466_CONFIG2; 851 } else { 852 reg = DBCOOL_CONFIG2_REG; 853 } 854 cfg = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 855 cfg &= ~sc->sc_suspend; 856 sc->sc_dc.dc_writereg(&sc->sc_dc, reg, cfg); 857 858 return true; 859 860 } 861 862 uint8_t 863 dbcool_readreg(struct dbcool_chipset *dc, uint8_t reg) 864 { 865 uint8_t data = 0; 866 867 if (iic_acquire_bus(dc->dc_tag, 0) != 0) 868 return data; 869 870 if (dc->dc_chip == NULL || dc->dc_chip->flags & DBCFLAG_NO_READBYTE) { 871 /* ADM1027 doesn't support i2c read_byte protocol */ 872 if (iic_smbus_send_byte(dc->dc_tag, dc->dc_addr, reg, 0) != 0) 873 goto bad; 874 (void)iic_smbus_receive_byte(dc->dc_tag, dc->dc_addr, &data, 0); 875 } else 876 (void)iic_smbus_read_byte(dc->dc_tag, dc->dc_addr, reg, &data, 877 0); 878 879 bad: 880 iic_release_bus(dc->dc_tag, 0); 881 return data; 882 } 883 884 void 885 dbcool_writereg(struct dbcool_chipset *dc, uint8_t reg, uint8_t val) 886 { 887 if (iic_acquire_bus(dc->dc_tag, 0) != 0) 888 return; 889 890 (void)iic_smbus_write_byte(dc->dc_tag, dc->dc_addr, reg, val, 0); 891 892 iic_release_bus(dc->dc_tag, 0); 893 } 894 895 static bool 896 dbcool_islocked(struct dbcool_softc *sc) 897 { 898 uint8_t cfg_reg; 899 900 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 901 return 0; 902 903 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) 904 cfg_reg = DBCOOL_ADT7466_CONFIG1; 905 else 906 cfg_reg = DBCOOL_CONFIG1_REG; 907 908 if (sc->sc_dc.dc_readreg(&sc->sc_dc, cfg_reg) & DBCOOL_CFG1_LOCK) 909 return 1; 910 else 911 return 0; 912 } 913 914 static int 915 dbcool_read_temp(struct dbcool_softc *sc, uint8_t reg, bool extres) 916 { 917 uint8_t t1, t2, t3, val, ext = 0; 918 int temp; 919 920 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) { 921 /* 922 * ADT7466 temps are in strange location 923 */ 924 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADT7466_CONFIG1); 925 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 926 if (extres) 927 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, reg + 1); 928 } else if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) { 929 /* 930 * ADM1030 temps are in their own special place, too 931 */ 932 if (extres) { 933 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_TEMP_EXTRES); 934 if (reg == DBCOOL_ADM1030_L_TEMP) 935 ext >>= 6; 936 else if (reg == DBCOOL_ADM1031_R2_TEMP) 937 ext >>= 4; 938 else 939 ext >>= 1; 940 ext &= 0x03; 941 } 942 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 943 } else if (extres) { 944 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES2_REG); 945 946 /* Read all msb regs to unlatch them */ 947 t1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_12VIN); 948 t1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_REMOTE1_TEMP); 949 t2 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_REMOTE2_TEMP); 950 t3 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_LOCAL_TEMP); 951 switch (reg) { 952 case DBCOOL_REMOTE1_TEMP: 953 val = t1; 954 ext >>= 2; 955 break; 956 case DBCOOL_LOCAL_TEMP: 957 val = t3; 958 ext >>= 4; 959 break; 960 case DBCOOL_REMOTE2_TEMP: 961 val = t2; 962 ext >>= 6; 963 break; 964 default: 965 val = 0; 966 break; 967 } 968 ext &= 0x03; 969 } 970 else 971 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 972 973 /* Check for invalid temp values */ 974 if ((sc->sc_temp_offset == 0 && val == 0x80) || 975 (sc->sc_temp_offset != 0 && val == 0)) 976 return 0; 977 978 /* If using offset mode, adjust, else treat as signed */ 979 if (sc->sc_temp_offset) { 980 temp = val; 981 temp -= sc->sc_temp_offset; 982 } else 983 temp = (int8_t)val; 984 985 /* Convert degC to uK and include extended precision bits */ 986 temp *= 1000000; 987 temp += 250000 * (int)ext; 988 temp += 273150000U; 989 990 return temp; 991 } 992 993 static int 994 dbcool_read_rpm(struct dbcool_softc *sc, uint8_t reg) 995 { 996 int rpm; 997 uint8_t rpm_lo, rpm_hi; 998 999 rpm_lo = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 1000 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 1001 rpm_hi = (rpm_lo == 0xff)?0xff:0x0; 1002 else 1003 rpm_hi = sc->sc_dc.dc_readreg(&sc->sc_dc, reg + 1); 1004 1005 rpm = (rpm_hi << 8) | rpm_lo; 1006 if (rpm == 0xffff) 1007 return 0; /* 0xffff indicates stalled/failed fan */ 1008 1009 /* don't divide by zero */ 1010 return (rpm == 0)? 0 : (sc->sc_dc.dc_chip->rpm_dividend / rpm); 1011 } 1012 1013 /* Provide chip's supply voltage, in microvolts */ 1014 static int 1015 dbcool_supply_voltage(struct dbcool_softc *sc) 1016 { 1017 if (sc->sc_dc.dc_chip->flags & DBCFLAG_MULTI_VCC) { 1018 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_CONFIG1_REG) & DBCOOL_CFG1_Vcc) 1019 return 5002500; 1020 else 1021 return 3300000; 1022 } else if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) { 1023 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADT7466_CONFIG1) & 1024 DBCOOL_ADT7466_CFG1_Vcc) 1025 return 5000000; 1026 else 1027 return 3300000; 1028 } else 1029 return 3300000; 1030 } 1031 1032 /* 1033 * Nominal voltages are calculated in microvolts 1034 */ 1035 static int 1036 dbcool_read_volt(struct dbcool_softc *sc, uint8_t reg, int nom_idx, bool extres) 1037 { 1038 uint8_t ext = 0, v1, v2, v3, v4, val; 1039 int64_t ret; 1040 int64_t nom; 1041 1042 nom = nominal_voltages[nom_idx]; 1043 if (nom < 0) 1044 nom = sc->sc_supply_voltage; 1045 1046 /* ADT7466 voltages are in strange locations with only 8-bits */ 1047 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) 1048 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 1049 else 1050 /* 1051 * It's a "normal" dbCool chip - check for regs that 1052 * share extended resolution bits since we have to 1053 * read all the MSB registers to unlatch them. 1054 */ 1055 if (!extres) 1056 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 1057 else if (reg == DBCOOL_12VIN) { 1058 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES2_REG) & 0x03; 1059 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 1060 (void)dbcool_read_temp(sc, DBCOOL_LOCAL_TEMP, true); 1061 } else if (reg == DBCOOL_VTT || reg == DBCOOL_IMON) { 1062 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES_VTT_IMON); 1063 v1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_IMON); 1064 v2 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VTT); 1065 if (reg == DBCOOL_IMON) { 1066 val = v1; 1067 ext >>= 6; 1068 } else 1069 val = v2; 1070 ext >>= 4; 1071 ext &= 0x0f; 1072 } else { 1073 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES1_REG); 1074 v1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_25VIN); 1075 v2 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VCCP); 1076 v3 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VCC); 1077 v4 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_5VIN); 1078 1079 switch (reg) { 1080 case DBCOOL_25VIN: 1081 val = v1; 1082 break; 1083 case DBCOOL_VCCP: 1084 val = v2; 1085 ext >>= 2; 1086 break; 1087 case DBCOOL_VCC: 1088 val = v3; 1089 ext >>= 4; 1090 break; 1091 case DBCOOL_5VIN: 1092 val = v4; 1093 ext >>= 6; 1094 break; 1095 default: 1096 val = nom = 0; 1097 } 1098 ext &= 0x03; 1099 } 1100 1101 /* 1102 * Scale the nominal value by the 10-bit fraction 1103 * 1104 * Returned value is in microvolts. 1105 */ 1106 ret = val; 1107 ret <<= 2; 1108 ret |= ext; 1109 ret = (ret * nom) / 0x300; 1110 1111 return ret; 1112 } 1113 1114 static int 1115 sysctl_dbcool_temp(SYSCTLFN_ARGS) 1116 { 1117 struct sysctlnode node; 1118 struct dbcool_softc *sc; 1119 int reg, error; 1120 uint8_t chipreg; 1121 uint8_t newreg; 1122 1123 node = *rnode; 1124 sc = (struct dbcool_softc *)node.sysctl_data; 1125 chipreg = node.sysctl_num & 0xff; 1126 1127 if (sc->sc_temp_offset) { 1128 reg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1129 reg -= sc->sc_temp_offset; 1130 } else 1131 reg = (int8_t)sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1132 1133 node.sysctl_data = ® 1134 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1135 1136 if (error || newp == NULL) 1137 return error; 1138 1139 /* We were asked to update the value - sanity check before writing */ 1140 if (*(int *)node.sysctl_data < -64 || 1141 *(int *)node.sysctl_data > 127 + sc->sc_temp_offset) 1142 return EINVAL; 1143 1144 newreg = *(int *)node.sysctl_data; 1145 newreg += sc->sc_temp_offset; 1146 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1147 return 0; 1148 } 1149 1150 static int 1151 sysctl_adm1030_temp(SYSCTLFN_ARGS) 1152 { 1153 struct sysctlnode node; 1154 struct dbcool_softc *sc; 1155 int reg, error; 1156 uint8_t chipreg, oldreg, newreg; 1157 1158 node = *rnode; 1159 sc = (struct dbcool_softc *)node.sysctl_data; 1160 chipreg = node.sysctl_num & 0xff; 1161 1162 oldreg = (int8_t)sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1163 reg = (oldreg >> 1) & ~0x03; 1164 1165 node.sysctl_data = ® 1166 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1167 1168 if (error || newp == NULL) 1169 return error; 1170 1171 /* We were asked to update the value - sanity check before writing */ 1172 if (*(int *)node.sysctl_data < 0 || *(int *)node.sysctl_data > 127) 1173 return EINVAL; 1174 1175 newreg = *(int *)node.sysctl_data; 1176 newreg &= ~0x03; 1177 newreg <<= 1; 1178 newreg |= (oldreg & 0x07); 1179 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1180 return 0; 1181 } 1182 1183 static int 1184 sysctl_adm1030_trange(SYSCTLFN_ARGS) 1185 { 1186 struct sysctlnode node; 1187 struct dbcool_softc *sc; 1188 int reg, error, newval; 1189 uint8_t chipreg, oldreg, newreg; 1190 1191 node = *rnode; 1192 sc = (struct dbcool_softc *)node.sysctl_data; 1193 chipreg = node.sysctl_num & 0xff; 1194 1195 oldreg = (int8_t)sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1196 reg = oldreg & 0x07; 1197 1198 node.sysctl_data = ® 1199 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1200 1201 if (error || newp == NULL) 1202 return error; 1203 1204 /* We were asked to update the value - sanity check before writing */ 1205 newval = *(int *)node.sysctl_data; 1206 1207 if (newval == 5) 1208 newreg = 0; 1209 else if (newval == 10) 1210 newreg = 1; 1211 else if (newval == 20) 1212 newreg = 2; 1213 else if (newval == 40) 1214 newreg = 3; 1215 else if (newval == 80) 1216 newreg = 4; 1217 else 1218 return EINVAL; 1219 1220 newreg |= (oldreg & ~0x07); 1221 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1222 return 0; 1223 } 1224 1225 static int 1226 sysctl_dbcool_duty(SYSCTLFN_ARGS) 1227 { 1228 struct sysctlnode node; 1229 struct dbcool_softc *sc; 1230 int reg, error; 1231 uint8_t chipreg, oldreg, newreg; 1232 1233 node = *rnode; 1234 sc = (struct dbcool_softc *)node.sysctl_data; 1235 chipreg = node.sysctl_num & 0xff; 1236 1237 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1238 reg = (uint32_t)oldreg; 1239 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 1240 reg = ((reg & 0x0f) * 100) / 15; 1241 else 1242 reg = (reg * 100) / 255; 1243 node.sysctl_data = ® 1244 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1245 1246 if (error || newp == NULL) 1247 return error; 1248 1249 /* We were asked to update the value - sanity check before writing */ 1250 if (*(int *)node.sysctl_data < 0 || *(int *)node.sysctl_data > 100) 1251 return EINVAL; 1252 1253 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) { 1254 newreg = *(uint8_t *)(node.sysctl_data) * 15 / 100; 1255 newreg |= oldreg & 0xf0; 1256 } else 1257 newreg = *(uint8_t *)(node.sysctl_data) * 255 / 100; 1258 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1259 return 0; 1260 } 1261 1262 static int 1263 sysctl_dbcool_behavior(SYSCTLFN_ARGS) 1264 { 1265 struct sysctlnode node; 1266 struct dbcool_softc *sc; 1267 int i, reg, error; 1268 uint8_t chipreg, oldreg, newreg; 1269 1270 node = *rnode; 1271 sc = (struct dbcool_softc *)node.sysctl_data; 1272 chipreg = node.sysctl_num & 0xff; 1273 1274 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1275 1276 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) { 1277 if ((sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_CFG2) & 1) == 0) 1278 reg = 4; 1279 else if ((oldreg & 0x80) == 0) 1280 reg = 7; 1281 else if ((oldreg & 0x60) == 0) 1282 reg = 4; 1283 else 1284 reg = 6; 1285 } else 1286 reg = (oldreg >> 5) & 0x07; 1287 1288 strlcpy(dbcool_cur_behav, behavior[reg], sizeof(dbcool_cur_behav)); 1289 node.sysctl_data = dbcool_cur_behav; 1290 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1291 1292 if (error || newp == NULL) 1293 return error; 1294 1295 /* We were asked to update the value - convert string to value */ 1296 newreg = __arraycount(behavior); 1297 for (i = 0; i < __arraycount(behavior); i++) 1298 if (strcmp(node.sysctl_data, behavior[i]) == 0) 1299 break; 1300 if (i >= __arraycount(behavior)) 1301 return EINVAL; 1302 1303 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) { 1304 /* 1305 * ADM1030 splits fan controller behavior across two 1306 * registers. We also do not support Auto-Filter mode 1307 * nor do we support Manual-RPM-feedback. 1308 */ 1309 if (newreg == 4) { 1310 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_CFG2); 1311 oldreg &= ~0x01; 1312 sc->sc_dc.dc_writereg(&sc->sc_dc, DBCOOL_ADM1030_CFG2, oldreg); 1313 } else { 1314 if (newreg == 0) 1315 newreg = 4; 1316 else if (newreg == 6) 1317 newreg = 7; 1318 else if (newreg == 7) 1319 newreg = 0; 1320 else 1321 return EINVAL; 1322 newreg <<= 5; 1323 newreg |= (oldreg & 0x1f); 1324 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1325 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_CFG2) | 1; 1326 sc->sc_dc.dc_writereg(&sc->sc_dc, DBCOOL_ADM1030_CFG2, oldreg); 1327 } 1328 } else { 1329 newreg = (sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg) & 0x1f) | (i << 5); 1330 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1331 } 1332 return 0; 1333 } 1334 1335 static int 1336 sysctl_dbcool_slope(SYSCTLFN_ARGS) 1337 { 1338 struct sysctlnode node; 1339 struct dbcool_softc *sc; 1340 int reg, error; 1341 uint8_t chipreg; 1342 uint8_t newreg; 1343 1344 node = *rnode; 1345 sc = (struct dbcool_softc *)node.sysctl_data; 1346 chipreg = node.sysctl_num & 0xff; 1347 1348 reg = (sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg) >> 4) & 0x0f; 1349 node.sysctl_data = ® 1350 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1351 1352 if (error || newp == NULL) 1353 return error; 1354 1355 /* We were asked to update the value - sanity check before writing */ 1356 if (*(int *)node.sysctl_data < 0 || *(int *)node.sysctl_data > 0x0f) 1357 return EINVAL; 1358 1359 newreg = (sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg) & 0x0f) | 1360 (*(int *)node.sysctl_data << 4); 1361 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1362 return 0; 1363 } 1364 1365 static int 1366 sysctl_dbcool_thyst(SYSCTLFN_ARGS) 1367 { 1368 struct sysctlnode node; 1369 struct dbcool_softc *sc; 1370 int reg, error; 1371 uint8_t chipreg; 1372 uint8_t newreg, newhyst; 1373 1374 node = *rnode; 1375 sc = (struct dbcool_softc *)node.sysctl_data; 1376 chipreg = node.sysctl_num & 0x7f; 1377 1378 /* retrieve 4-bit value */ 1379 newreg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1380 if ((node.sysctl_num & 0x80) == 0) 1381 reg = newreg >> 4; 1382 else 1383 reg = newreg; 1384 reg = reg & 0x0f; 1385 1386 node.sysctl_data = ® 1387 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1388 1389 if (error || newp == NULL) 1390 return error; 1391 1392 /* We were asked to update the value - sanity check before writing */ 1393 newhyst = *(int *)node.sysctl_data; 1394 if (newhyst > 0x0f) 1395 return EINVAL; 1396 1397 /* Insert new value into field and update register */ 1398 if ((node.sysctl_num & 0x80) == 0) { 1399 newreg &= 0x0f; 1400 newreg |= (newhyst << 4); 1401 } else { 1402 newreg &= 0xf0; 1403 newreg |= newhyst; 1404 } 1405 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1406 return 0; 1407 } 1408 1409 #ifdef DBCOOL_DEBUG 1410 1411 /* 1412 * These routines can be used for debugging. reg_select is used to 1413 * select any arbitrary register in the device. reg_access is used 1414 * to read (and optionally update) the selected register. 1415 * 1416 * No attempt is made to validate the data passed. If you use these 1417 * routines, you are assumed to know what you're doing! 1418 * 1419 * Caveat user 1420 */ 1421 static int 1422 sysctl_dbcool_reg_select(SYSCTLFN_ARGS) 1423 { 1424 struct sysctlnode node; 1425 struct dbcool_softc *sc; 1426 int reg, error; 1427 1428 node = *rnode; 1429 sc = (struct dbcool_softc *)node.sysctl_data; 1430 1431 reg = sc->sc_user_reg; 1432 node.sysctl_data = ® 1433 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1434 1435 if (error || newp == NULL) 1436 return error; 1437 1438 sc->sc_user_reg = *(int *)node.sysctl_data; 1439 return 0; 1440 } 1441 1442 static int 1443 sysctl_dbcool_reg_access(SYSCTLFN_ARGS) 1444 { 1445 struct sysctlnode node; 1446 struct dbcool_softc *sc; 1447 int reg, error; 1448 uint8_t chipreg; 1449 uint8_t newreg; 1450 1451 node = *rnode; 1452 sc = (struct dbcool_softc *)node.sysctl_data; 1453 chipreg = sc->sc_user_reg; 1454 1455 reg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1456 node.sysctl_data = ® 1457 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1458 1459 if (error || newp == NULL) 1460 return error; 1461 1462 newreg = *(int *)node.sysctl_data; 1463 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1464 return 0; 1465 } 1466 #endif /* DBCOOL_DEBUG */ 1467 1468 /* 1469 * Encode an index number and register number for use as a sysctl_num 1470 * so we can select the correct device register later. 1471 */ 1472 #define DBC_PWM_SYSCTL(seq, reg) ((seq << 8) | reg) 1473 1474 void 1475 dbcool_setup(device_t self) 1476 { 1477 struct dbcool_softc *sc = device_private(self); 1478 const struct sysctlnode *me = NULL; 1479 #ifdef DBCOOL_DEBUG 1480 struct sysctlnode *node = NULL; 1481 #endif 1482 uint8_t cfg_val, cfg_reg; 1483 int ret, error; 1484 1485 /* 1486 * Some chips are capable of reporting an extended temperature range 1487 * by default. On these models, config register 5 bit 0 can be set 1488 * to 1 for compatability with other chips that report 2s complement. 1489 */ 1490 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) { 1491 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADT7466_CONFIG1) & 0x80) 1492 sc->sc_temp_offset = 64; 1493 else 1494 sc->sc_temp_offset = 0; 1495 } else if (sc->sc_dc.dc_chip->flags & DBCFLAG_TEMPOFFSET) { 1496 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_CONFIG5_REG) & 1497 DBCOOL_CFG5_TWOSCOMP) 1498 sc->sc_temp_offset = 0; 1499 else 1500 sc->sc_temp_offset = 64; 1501 } else 1502 sc->sc_temp_offset = 0; 1503 1504 /* Determine Vcc for this chip */ 1505 sc->sc_supply_voltage = dbcool_supply_voltage(sc); 1506 1507 ret = sysctl_createv(&sc->sc_sysctl_log, 0, NULL, &me, 1508 CTLFLAG_READWRITE, 1509 CTLTYPE_NODE, device_xname(self), NULL, 1510 NULL, 0, NULL, 0, 1511 CTL_HW, CTL_CREATE, CTL_EOL); 1512 if (ret == 0) 1513 sc->sc_root_sysctl_num = me->sysctl_num; 1514 else 1515 sc->sc_root_sysctl_num = 0; 1516 1517 aprint_debug_dev(self, 1518 "Supply voltage %"PRId64".%06"PRId64"V, %s temp range\n", 1519 sc->sc_supply_voltage / 1000000, 1520 sc->sc_supply_voltage % 1000000, 1521 sc->sc_temp_offset ? "extended" : "normal"); 1522 1523 /* Create the sensors for this device */ 1524 sc->sc_sme = sysmon_envsys_create(); 1525 if (dbcool_setup_sensors(sc)) 1526 goto out; 1527 1528 if (sc->sc_root_sysctl_num != 0) { 1529 /* If supported, create sysctl tree for fan PWM controllers */ 1530 if (sc->sc_dc.dc_chip->power != NULL) 1531 dbcool_setup_controllers(sc); 1532 1533 #ifdef DBCOOL_DEBUG 1534 ret = sysctl_createv(&sc->sc_sysctl_log, 0, NULL, 1535 (void *)&node, 1536 CTLFLAG_READWRITE, CTLTYPE_INT, "reg_select", NULL, 1537 sysctl_dbcool_reg_select, 1538 0, (void *)sc, sizeof(int), 1539 CTL_HW, me->sysctl_num, CTL_CREATE, CTL_EOL); 1540 if (node != NULL) 1541 node->sysctl_data = sc; 1542 1543 ret = sysctl_createv(&sc->sc_sysctl_log, 0, NULL, 1544 (void *)&node, 1545 CTLFLAG_READWRITE, CTLTYPE_INT, "reg_access", NULL, 1546 sysctl_dbcool_reg_access, 1547 0, (void *)sc, sizeof(int), 1548 CTL_HW, me->sysctl_num, CTL_CREATE, CTL_EOL); 1549 if (node != NULL) 1550 node->sysctl_data = sc; 1551 #endif /* DBCOOL_DEBUG */ 1552 } 1553 1554 /* 1555 * Read and rewrite config register to activate device 1556 */ 1557 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 1558 cfg_reg = DBCOOL_ADM1030_CFG1; 1559 else if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) 1560 cfg_reg = DBCOOL_ADT7466_CONFIG1; 1561 else 1562 cfg_reg = DBCOOL_CONFIG1_REG; 1563 cfg_val = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_CONFIG1_REG); 1564 if ((cfg_val & DBCOOL_CFG1_START) == 0) { 1565 cfg_val |= DBCOOL_CFG1_START; 1566 sc->sc_dc.dc_writereg(&sc->sc_dc, cfg_reg, cfg_val); 1567 } 1568 if (dbcool_islocked(sc)) 1569 aprint_normal_dev(self, "configuration locked\n"); 1570 1571 sc->sc_sme->sme_name = device_xname(self); 1572 sc->sc_sme->sme_cookie = sc; 1573 sc->sc_sme->sme_refresh = dbcool_refresh; 1574 sc->sc_sme->sme_set_limits = dbcool_set_limits; 1575 sc->sc_sme->sme_get_limits = dbcool_get_limits; 1576 1577 if ((error = sysmon_envsys_register(sc->sc_sme)) != 0) { 1578 aprint_error_dev(self, 1579 "unable to register with sysmon (%d)\n", error); 1580 goto out; 1581 } 1582 1583 return; 1584 1585 out: 1586 sysmon_envsys_destroy(sc->sc_sme); 1587 } 1588 1589 static int 1590 dbcool_setup_sensors(struct dbcool_softc *sc) 1591 { 1592 int i; 1593 int error = 0; 1594 uint8_t vid_reg, vid_val; 1595 struct chip_id *chip = sc->sc_dc.dc_chip; 1596 1597 for (i=0; chip->table[i].type != DBC_EOF; i++) { 1598 if (i < DBCOOL_MAXSENSORS) 1599 sc->sc_sysctl_num[i] = -1; 1600 else if (chip->table[i].type != DBC_CTL) { 1601 aprint_normal_dev(sc->sc_dev, "chip table too big!\n"); 1602 break; 1603 } 1604 switch (chip->table[i].type) { 1605 case DBC_TEMP: 1606 sc->sc_sensor[i].units = ENVSYS_STEMP; 1607 sc->sc_sensor[i].state = ENVSYS_SINVALID; 1608 sc->sc_sensor[i].flags |= ENVSYS_FMONLIMITS; 1609 sc->sc_sensor[i].flags |= ENVSYS_FHAS_ENTROPY; 1610 error = dbcool_attach_sensor(sc, i); 1611 break; 1612 case DBC_VOLT: 1613 /* 1614 * If 12V-In pin has been reconfigured as 6th bit 1615 * of VID code, don't create a 12V-In sensor 1616 */ 1617 if ((chip->flags & DBCFLAG_HAS_VID_SEL) && 1618 (chip->table[i].reg.val_reg == DBCOOL_12VIN) && 1619 (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VID_REG) & 1620 0x80)) 1621 break; 1622 1623 sc->sc_sensor[i].units = ENVSYS_SVOLTS_DC; 1624 sc->sc_sensor[i].state = ENVSYS_SINVALID; 1625 sc->sc_sensor[i].flags |= ENVSYS_FMONLIMITS; 1626 sc->sc_sensor[i].flags |= ENVSYS_FHAS_ENTROPY; 1627 error = dbcool_attach_sensor(sc, i); 1628 break; 1629 case DBC_FAN: 1630 sc->sc_sensor[i].units = ENVSYS_SFANRPM; 1631 sc->sc_sensor[i].state = ENVSYS_SINVALID; 1632 sc->sc_sensor[i].flags |= ENVSYS_FMONLIMITS; 1633 sc->sc_sensor[i].flags |= ENVSYS_FHAS_ENTROPY; 1634 error = dbcool_attach_sensor(sc, i); 1635 break; 1636 case DBC_VID: 1637 sc->sc_sensor[i].units = ENVSYS_INTEGER; 1638 sc->sc_sensor[i].state = ENVSYS_SINVALID; 1639 sc->sc_sensor[i].flags |= ENVSYS_FMONNOTSUPP; 1640 1641 /* retrieve 5- or 6-bit value */ 1642 vid_reg = chip->table[i].reg.val_reg; 1643 vid_val = sc->sc_dc.dc_readreg(&sc->sc_dc, vid_reg); 1644 if (chip->flags & DBCFLAG_HAS_VID_SEL) 1645 vid_val &= 0x3f; 1646 else 1647 vid_val &= 0x1f; 1648 sc->sc_sensor[i].value_cur = vid_val; 1649 1650 error = dbcool_attach_sensor(sc, i); 1651 break; 1652 case DBC_CTL: 1653 error = dbcool_attach_temp_control(sc, i, chip); 1654 if (error) { 1655 aprint_error_dev(sc->sc_dev, 1656 "attach index %d failed %d\n", 1657 i, error); 1658 error = 0; 1659 } 1660 break; 1661 default: 1662 aprint_error_dev(sc->sc_dev, 1663 "sensor_table index %d has bad type %d\n", 1664 i, chip->table[i].type); 1665 break; 1666 } 1667 if (error) 1668 break; 1669 } 1670 return error; 1671 } 1672 1673 static int 1674 dbcool_attach_sensor(struct dbcool_softc *sc, int idx) 1675 { 1676 int name_index; 1677 int error = 0; 1678 1679 name_index = sc->sc_dc.dc_chip->table[idx].name_index; 1680 strlcpy(sc->sc_sensor[idx].desc, dbc_sensor_names[name_index], 1681 sizeof(sc->sc_sensor[idx].desc)); 1682 sc->sc_regs[idx] = &sc->sc_dc.dc_chip->table[idx].reg; 1683 sc->sc_nom_volt[idx] = sc->sc_dc.dc_chip->table[idx].nom_volt_index; 1684 1685 error = sysmon_envsys_sensor_attach(sc->sc_sme, &sc->sc_sensor[idx]); 1686 return error; 1687 } 1688 1689 static int 1690 dbcool_attach_temp_control(struct dbcool_softc *sc, int idx, 1691 struct chip_id *chip) 1692 { 1693 const struct sysctlnode *me2 = NULL, *node; 1694 int j, ret, sysctl_index, rw_flag; 1695 uint8_t sysctl_reg; 1696 char name[SYSCTL_NAMELEN]; 1697 1698 /* Search for the corresponding temp sensor */ 1699 for (j = 0; j < idx; j++) { 1700 if (j >= DBCOOL_MAXSENSORS || chip->table[j].type != DBC_TEMP) 1701 continue; 1702 if (chip->table[j].name_index == chip->table[idx].name_index) 1703 break; 1704 } 1705 if (j >= idx) /* Temp sensor not found */ 1706 return ENOENT; 1707 1708 /* create sysctl node for the sensor if not one already there */ 1709 if (sc->sc_sysctl_num[j] == -1) { 1710 ret = sysctl_createv(&sc->sc_sysctl_log, 0, NULL, &me2, 1711 CTLFLAG_READWRITE, 1712 CTLTYPE_NODE, sc->sc_sensor[j].desc, NULL, 1713 NULL, 0, NULL, 0, 1714 CTL_HW, sc->sc_root_sysctl_num, CTL_CREATE, 1715 CTL_EOL); 1716 if (me2 != NULL) 1717 sc->sc_sysctl_num[j] = me2->sysctl_num; 1718 else 1719 return ret; 1720 } 1721 /* add sysctl leaf node for this control variable */ 1722 sysctl_index = chip->table[idx].sysctl_index; 1723 sysctl_reg = chip->table[idx].reg.val_reg; 1724 strlcpy(name, dbc_sysctl_table[sysctl_index].name, sizeof(name)); 1725 if (dbc_sysctl_table[sysctl_index].lockable && dbcool_islocked(sc)) 1726 rw_flag = CTLFLAG_READONLY | CTLFLAG_OWNDESC; 1727 else 1728 rw_flag = CTLFLAG_READWRITE | CTLFLAG_OWNDESC; 1729 ret = sysctl_createv(&sc->sc_sysctl_log, 0, NULL, &node, rw_flag, 1730 CTLTYPE_INT, name, 1731 SYSCTL_DESCR(dbc_sysctl_table[sysctl_index].desc), 1732 dbc_sysctl_table[sysctl_index].helper, 1733 0, (void *)sc, sizeof(int), 1734 CTL_HW, sc->sc_root_sysctl_num, 1735 sc->sc_sysctl_num[j], 1736 DBC_PWM_SYSCTL(idx, sysctl_reg), CTL_EOL); 1737 1738 return ret; 1739 } 1740 1741 static void 1742 dbcool_setup_controllers(struct dbcool_softc *sc) 1743 { 1744 int i, j, rw_flag; 1745 uint8_t sysctl_reg; 1746 struct chip_id *chip = sc->sc_dc.dc_chip; 1747 const struct sysctlnode *me2 = NULL; 1748 const struct sysctlnode *node = NULL; 1749 char name[SYSCTL_NAMELEN]; 1750 1751 for (i = 0; chip->power[i].desc != NULL; i++) { 1752 snprintf(name, sizeof(name), "fan_ctl_%d", i); 1753 sysctl_createv(&sc->sc_sysctl_log, 0, NULL, &me2, 1754 CTLFLAG_READWRITE | CTLFLAG_OWNDESC, 1755 CTLTYPE_NODE, name, NULL, 1756 NULL, 0, NULL, 0, 1757 CTL_HW, sc->sc_root_sysctl_num, CTL_CREATE, CTL_EOL); 1758 1759 for (j = DBC_PWM_BEHAVIOR; j < DBC_PWM_LAST_PARAM; j++) { 1760 if (j == DBC_PWM_MAX_DUTY && 1761 (chip->flags & DBCFLAG_HAS_MAXDUTY) == 0) 1762 continue; 1763 sysctl_reg = chip->power[i].power_regs[j]; 1764 if (sysctl_reg == DBCOOL_NO_REG) 1765 continue; 1766 strlcpy(name, dbc_sysctl_table[j].name, sizeof(name)); 1767 if (dbc_sysctl_table[j].lockable && dbcool_islocked(sc)) 1768 rw_flag = CTLFLAG_READONLY | CTLFLAG_OWNDESC; 1769 else 1770 rw_flag = CTLFLAG_READWRITE | CTLFLAG_OWNDESC; 1771 (sysctl_createv)(&sc->sc_sysctl_log, 0, NULL, 1772 &node, rw_flag, 1773 (j == DBC_PWM_BEHAVIOR)? 1774 CTLTYPE_STRING:CTLTYPE_INT, 1775 name, 1776 SYSCTL_DESCR(dbc_sysctl_table[j].desc), 1777 dbc_sysctl_table[j].helper, 1778 0, sc, 1779 ( j == DBC_PWM_BEHAVIOR)? 1780 sizeof(dbcool_cur_behav): sizeof(int), 1781 CTL_HW, sc->sc_root_sysctl_num, me2->sysctl_num, 1782 DBC_PWM_SYSCTL(j, sysctl_reg), CTL_EOL); 1783 } 1784 } 1785 } 1786 1787 static void 1788 dbcool_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 1789 { 1790 struct dbcool_softc *sc=sme->sme_cookie; 1791 int i, nom_volt_idx, cur; 1792 struct reg_list *reg; 1793 1794 i = edata->sensor; 1795 reg = sc->sc_regs[i]; 1796 1797 edata->state = ENVSYS_SVALID; 1798 switch (edata->units) 1799 { 1800 case ENVSYS_STEMP: 1801 cur = dbcool_read_temp(sc, reg->val_reg, true); 1802 break; 1803 case ENVSYS_SVOLTS_DC: 1804 nom_volt_idx = sc->sc_nom_volt[i]; 1805 cur = dbcool_read_volt(sc, reg->val_reg, nom_volt_idx, 1806 true); 1807 break; 1808 case ENVSYS_SFANRPM: 1809 cur = dbcool_read_rpm(sc, reg->val_reg); 1810 break; 1811 case ENVSYS_INTEGER: 1812 return; 1813 default: 1814 edata->state = ENVSYS_SINVALID; 1815 return; 1816 } 1817 1818 if (cur == 0 && (edata->units != ENVSYS_SFANRPM)) 1819 edata->state = ENVSYS_SINVALID; 1820 1821 /* 1822 * If fan is "stalled" but has no low limit, treat 1823 * it as though the fan is not installed. 1824 */ 1825 else if (edata->units == ENVSYS_SFANRPM && cur == 0 && 1826 !(edata->upropset & (PROP_CRITMIN | PROP_WARNMIN))) 1827 edata->state = ENVSYS_SINVALID; 1828 1829 edata->value_cur = cur; 1830 } 1831 1832 int 1833 dbcool_chip_ident(struct dbcool_chipset *dc) 1834 { 1835 /* verify this is a supported dbCool chip */ 1836 uint8_t c_id, d_id, r_id; 1837 int i; 1838 1839 c_id = dc->dc_readreg(dc, DBCOOL_COMPANYID_REG); 1840 d_id = dc->dc_readreg(dc, DBCOOL_DEVICEID_REG); 1841 r_id = dc->dc_readreg(dc, DBCOOL_REVISION_REG); 1842 1843 /* The EMC6D103S only supports read_byte and since dc->dc_chip is 1844 * NULL when we call dc->dc_readreg above we use 1845 * send_byte/receive_byte which doesn't work. 1846 * 1847 * So if we only get 0's back then try again with dc->dc_chip 1848 * set to the EMC6D103S_DEVICEID and which doesn't have 1849 * DBCFLAG_NO_READBYTE set so read_byte will be used 1850 */ 1851 if ((c_id == 0) && (d_id == 0) && (r_id == 0)) { 1852 for (i = 0; chip_table[i].company != 0; i++) 1853 if ((SMSC_COMPANYID == chip_table[i].company) && 1854 (EMC6D103S_DEVICEID == chip_table[i].device)) { 1855 dc->dc_chip = &chip_table[i]; 1856 break; 1857 } 1858 c_id = dc->dc_readreg(dc, DBCOOL_COMPANYID_REG); 1859 d_id = dc->dc_readreg(dc, DBCOOL_DEVICEID_REG); 1860 r_id = dc->dc_readreg(dc, DBCOOL_REVISION_REG); 1861 } 1862 1863 for (i = 0; chip_table[i].company != 0; i++) 1864 if ((c_id == chip_table[i].company) && 1865 (d_id == chip_table[i].device || 1866 chip_table[i].device == 0xff) && 1867 (r_id == chip_table[i].rev || 1868 chip_table[i].rev == 0xff)) { 1869 dc->dc_chip = &chip_table[i]; 1870 return i; 1871 } 1872 1873 aprint_verbose("dbcool_chip_ident: addr 0x%02x c_id 0x%02x d_id 0x%02x" 1874 " r_id 0x%02x: No match.\n", dc->dc_addr, c_id, d_id, 1875 r_id); 1876 1877 return -1; 1878 } 1879 1880 /* 1881 * Retrieve sensor limits from the chip registers 1882 */ 1883 static void 1884 dbcool_get_limits(struct sysmon_envsys *sme, envsys_data_t *edata, 1885 sysmon_envsys_lim_t *limits, uint32_t *props) 1886 { 1887 int index = edata->sensor; 1888 struct dbcool_softc *sc = sme->sme_cookie; 1889 1890 *props &= ~(PROP_CRITMIN | PROP_CRITMAX); 1891 switch (edata->units) { 1892 case ENVSYS_STEMP: 1893 dbcool_get_temp_limits(sc, index, limits, props); 1894 break; 1895 case ENVSYS_SVOLTS_DC: 1896 dbcool_get_volt_limits(sc, index, limits, props); 1897 break; 1898 case ENVSYS_SFANRPM: 1899 dbcool_get_fan_limits(sc, index, limits, props); 1900 1901 /* FALLTHROUGH */ 1902 default: 1903 break; 1904 } 1905 *props &= ~PROP_DRIVER_LIMITS; 1906 1907 /* If both limits provided, make sure they're sane */ 1908 if ((*props & PROP_CRITMIN) && 1909 (*props & PROP_CRITMAX) && 1910 (limits->sel_critmin >= limits->sel_critmax)) 1911 *props &= ~(PROP_CRITMIN | PROP_CRITMAX); 1912 1913 /* 1914 * If this is the first time through, save these values 1915 * in case user overrides them and then requests a reset. 1916 */ 1917 if (sc->sc_defprops[index] == 0) { 1918 sc->sc_defprops[index] = *props | PROP_DRIVER_LIMITS; 1919 sc->sc_deflims[index] = *limits; 1920 } 1921 } 1922 1923 static void 1924 dbcool_get_temp_limits(struct dbcool_softc *sc, int idx, 1925 sysmon_envsys_lim_t *lims, uint32_t *props) 1926 { 1927 struct reg_list *reg = sc->sc_regs[idx]; 1928 uint8_t lo_lim, hi_lim; 1929 1930 lo_lim = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->lo_lim_reg); 1931 hi_lim = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->hi_lim_reg); 1932 1933 if (sc->sc_temp_offset) { 1934 if (lo_lim > 0x01) { 1935 lims->sel_critmin = lo_lim - sc->sc_temp_offset; 1936 *props |= PROP_CRITMIN; 1937 } 1938 if (hi_lim != 0xff) { 1939 lims->sel_critmax = hi_lim - sc->sc_temp_offset; 1940 *props |= PROP_CRITMAX; 1941 } 1942 } else { 1943 if (lo_lim != 0x80 && lo_lim != 0x81) { 1944 lims->sel_critmin = (int8_t)lo_lim; 1945 *props |= PROP_CRITMIN; 1946 } 1947 1948 if (hi_lim != 0x7f) { 1949 lims->sel_critmax = (int8_t)hi_lim; 1950 *props |= PROP_CRITMAX; 1951 } 1952 } 1953 1954 /* Convert temp limits to microKelvin */ 1955 lims->sel_critmin *= 1000000; 1956 lims->sel_critmin += 273150000; 1957 lims->sel_critmax *= 1000000; 1958 lims->sel_critmax += 273150000; 1959 } 1960 1961 static void 1962 dbcool_get_volt_limits(struct dbcool_softc *sc, int idx, 1963 sysmon_envsys_lim_t *lims, uint32_t *props) 1964 { 1965 struct reg_list *reg = sc->sc_regs[idx]; 1966 int64_t limit; 1967 int nom; 1968 1969 nom = nominal_voltages[sc->sc_dc.dc_chip->table[idx].nom_volt_index]; 1970 if (nom < 0) 1971 nom = dbcool_supply_voltage(sc); 1972 nom *= 1000000; /* scale for microvolts */ 1973 1974 limit = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->lo_lim_reg); 1975 if (limit != 0x00 && limit != 0xff) { 1976 limit *= nom; 1977 limit /= 0xc0; 1978 lims->sel_critmin = limit; 1979 *props |= PROP_CRITMIN; 1980 } 1981 limit = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->hi_lim_reg); 1982 if (limit != 0x00 && limit != 0xff) { 1983 limit *= nom; 1984 limit /= 0xc0; 1985 lims->sel_critmax = limit; 1986 *props |= PROP_CRITMAX; 1987 } 1988 } 1989 1990 static void 1991 dbcool_get_fan_limits(struct dbcool_softc *sc, int idx, 1992 sysmon_envsys_lim_t *lims, uint32_t *props) 1993 { 1994 struct reg_list *reg = sc->sc_regs[idx]; 1995 int32_t limit; 1996 1997 limit = dbcool_read_rpm(sc, reg->lo_lim_reg); 1998 if (limit) { 1999 lims->sel_critmin = limit; 2000 *props |= PROP_CRITMIN; 2001 } 2002 } 2003 2004 /* 2005 * Update sensor limits in the chip registers 2006 */ 2007 static void 2008 dbcool_set_limits(struct sysmon_envsys *sme, envsys_data_t *edata, 2009 sysmon_envsys_lim_t *limits, uint32_t *props) 2010 { 2011 int index = edata->sensor; 2012 struct dbcool_softc *sc = sme->sme_cookie; 2013 2014 if (limits == NULL) { 2015 limits = &sc->sc_deflims[index]; 2016 props = &sc->sc_defprops[index]; 2017 } 2018 switch (edata->units) { 2019 case ENVSYS_STEMP: 2020 dbcool_set_temp_limits(sc, index, limits, props); 2021 break; 2022 case ENVSYS_SVOLTS_DC: 2023 dbcool_set_volt_limits(sc, index, limits, props); 2024 break; 2025 case ENVSYS_SFANRPM: 2026 dbcool_set_fan_limits(sc, index, limits, props); 2027 2028 /* FALLTHROUGH */ 2029 default: 2030 break; 2031 } 2032 *props &= ~PROP_DRIVER_LIMITS; 2033 } 2034 2035 static void 2036 dbcool_set_temp_limits(struct dbcool_softc *sc, int idx, 2037 sysmon_envsys_lim_t *lims, uint32_t *props) 2038 { 2039 struct reg_list *reg = sc->sc_regs[idx]; 2040 int32_t limit; 2041 2042 if (*props & PROP_CRITMIN) { 2043 limit = lims->sel_critmin - 273150000; 2044 limit /= 1000000; 2045 if (sc->sc_temp_offset) { 2046 limit += sc->sc_temp_offset; 2047 if (limit < 0) 2048 limit = 0; 2049 else if (limit > 255) 2050 limit = 255; 2051 } else { 2052 if (limit < -127) 2053 limit = -127; 2054 else if (limit > 127) 2055 limit = 127; 2056 } 2057 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, 2058 (uint8_t)limit); 2059 } else if (*props & PROP_DRIVER_LIMITS) { 2060 if (sc->sc_temp_offset) 2061 limit = 0x00; 2062 else 2063 limit = 0x80; 2064 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, 2065 (uint8_t)limit); 2066 } 2067 2068 if (*props & PROP_CRITMAX) { 2069 limit = lims->sel_critmax - 273150000; 2070 limit /= 1000000; 2071 if (sc->sc_temp_offset) { 2072 limit += sc->sc_temp_offset; 2073 if (limit < 0) 2074 limit = 0; 2075 else if (limit > 255) 2076 limit = 255; 2077 } else { 2078 if (limit < -127) 2079 limit = -127; 2080 else if (limit > 127) 2081 limit = 127; 2082 } 2083 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg, 2084 (uint8_t)limit); 2085 } else if (*props & PROP_DRIVER_LIMITS) { 2086 if (sc->sc_temp_offset) 2087 limit = 0xff; 2088 else 2089 limit = 0x7f; 2090 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg, 2091 (uint8_t)limit); 2092 } 2093 } 2094 2095 static void 2096 dbcool_set_volt_limits(struct dbcool_softc *sc, int idx, 2097 sysmon_envsys_lim_t *lims, uint32_t *props) 2098 { 2099 struct reg_list *reg = sc->sc_regs[idx]; 2100 int64_t limit; 2101 int nom; 2102 2103 nom = nominal_voltages[sc->sc_dc.dc_chip->table[idx].nom_volt_index]; 2104 if (nom < 0) 2105 nom = dbcool_supply_voltage(sc); 2106 nom *= 1000000; /* scale for microvolts */ 2107 2108 if (*props & PROP_CRITMIN) { 2109 limit = lims->sel_critmin; 2110 limit *= 0xc0; 2111 limit /= nom; 2112 if (limit > 0xff) 2113 limit = 0xff; 2114 else if (limit < 0) 2115 limit = 0; 2116 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, limit); 2117 } else if (*props & PROP_DRIVER_LIMITS) 2118 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, 0); 2119 2120 if (*props & PROP_CRITMAX) { 2121 limit = lims->sel_critmax; 2122 limit *= 0xc0; 2123 limit /= nom; 2124 if (limit > 0xff) 2125 limit = 0xff; 2126 else if (limit < 0) 2127 limit = 0; 2128 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg, limit); 2129 } else if (*props & PROP_DRIVER_LIMITS) 2130 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg, 0xff); 2131 } 2132 2133 static void 2134 dbcool_set_fan_limits(struct dbcool_softc *sc, int idx, 2135 sysmon_envsys_lim_t *lims, uint32_t *props) 2136 { 2137 struct reg_list *reg = sc->sc_regs[idx]; 2138 int32_t limit, dividend; 2139 2140 if (*props & PROP_CRITMIN) { 2141 limit = lims->sel_critmin; 2142 if (limit == 0) 2143 limit = 0xffff; 2144 else { 2145 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 2146 dividend = 11250 * 60; 2147 else 2148 dividend = 90000 * 60; 2149 limit = limit / dividend; 2150 if (limit > 0xffff) 2151 limit = 0xffff; 2152 } 2153 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, 2154 limit & 0xff); 2155 limit >>= 8; 2156 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg + 1, 2157 limit & 0xff); 2158 } else if (*props & PROP_DRIVER_LIMITS) { 2159 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, 0xff); 2160 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg + 1, 0xff); 2161 } 2162 } 2163 2164 MODULE(MODULE_CLASS_DRIVER, dbcool, "i2cexec,sysmon_envsys"); 2165 2166 #ifdef _MODULE 2167 #include "ioconf.c" 2168 #endif 2169 2170 static int 2171 dbcool_modcmd(modcmd_t cmd, void *opaque) 2172 { 2173 int error = 0; 2174 #ifdef _MODULE 2175 static struct sysctllog *dbcool_sysctl_clog; 2176 #endif 2177 2178 switch (cmd) { 2179 case MODULE_CMD_INIT: 2180 #ifdef _MODULE 2181 error = config_init_component(cfdriver_ioconf_dbcool, 2182 cfattach_ioconf_dbcool, cfdata_ioconf_dbcool); 2183 sysctl_dbcoolsetup(&dbcool_sysctl_clog); 2184 #endif 2185 return error; 2186 case MODULE_CMD_FINI: 2187 #ifdef _MODULE 2188 error = config_fini_component(cfdriver_ioconf_dbcool, 2189 cfattach_ioconf_dbcool, cfdata_ioconf_dbcool); 2190 sysctl_teardown(&dbcool_sysctl_clog); 2191 #endif 2192 return error; 2193 default: 2194 return ENOTTY; 2195 } 2196 } 2197
Indexes created Fri Sep 26 08:10:20 GMT 2025