dbcool.c revision 1.50
1 /* $NetBSD: dbcool.c,v 1.50 2018/06/18 17:07:07 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Goyette 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * a driver for the dbCool(tm) family of environmental controllers 34 * 35 * Data sheets for the various supported chips are available at 36 * 37 * http://www.onsemi.com/pub/Collateral/ADM1027-D.PDF 38 * http://www.onsemi.com/pub/Collateral/ADM1030-D.PDF 39 * http://www.onsemi.com/pub/Collateral/ADT7463-D.PDF 40 * http://www.onsemi.com/pub/Collateral/ADT7466.PDF 41 * http://www.onsemi.com/pub/Collateral/ADT7467-D.PDF 42 * http://www.onsemi.com/pub/Collateral/ADT7468-D.PDF 43 * http://www.onsemi.com/pub/Collateral/ADT7473-D.PDF 44 * http://www.onsemi.com/pub/Collateral/ADT7475-D.PDF 45 * http://www.onsemi.com/pub/Collateral/ADT7476-D.PDF 46 * http://www.onsemi.com/pub/Collateral/ADT7490-D.PDF 47 * http://www.smsc.com/media/Downloads_Public/Data_Sheets/6d103s.pdf 48 * 49 * (URLs are correct as of October 5, 2008) 50 */ 51 52 #include <sys/cdefs.h> 53 __KERNEL_RCSID(0, "$NetBSD: dbcool.c,v 1.50 2018/06/18 17:07:07 thorpej Exp $"); 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/kernel.h> 58 #include <sys/device.h> 59 #include <sys/malloc.h> 60 #include <sys/sysctl.h> 61 #include <sys/module.h> 62 63 #include <dev/i2c/dbcool_var.h> 64 #include <dev/i2c/dbcool_reg.h> 65 66 /* Config interface */ 67 static int dbcool_match(device_t, cfdata_t, void *); 68 static void dbcool_attach(device_t, device_t, void *); 69 static int dbcool_detach(device_t, int); 70 71 /* Device attributes */ 72 static int dbcool_supply_voltage(struct dbcool_softc *); 73 static bool dbcool_islocked(struct dbcool_softc *); 74 75 /* Sensor read functions */ 76 static void dbcool_refresh(struct sysmon_envsys *, envsys_data_t *); 77 static int dbcool_read_rpm(struct dbcool_softc *, uint8_t); 78 static int dbcool_read_temp(struct dbcool_softc *, uint8_t, bool); 79 static int dbcool_read_volt(struct dbcool_softc *, uint8_t, int, bool); 80 81 /* Sensor get/set limit functions */ 82 static void dbcool_get_limits(struct sysmon_envsys *, envsys_data_t *, 83 sysmon_envsys_lim_t *, uint32_t *); 84 static void dbcool_get_temp_limits(struct dbcool_softc *, int, 85 sysmon_envsys_lim_t *, uint32_t *); 86 static void dbcool_get_volt_limits(struct dbcool_softc *, int, 87 sysmon_envsys_lim_t *, uint32_t *); 88 static void dbcool_get_fan_limits(struct dbcool_softc *, int, 89 sysmon_envsys_lim_t *, uint32_t *); 90 91 static void dbcool_set_limits(struct sysmon_envsys *, envsys_data_t *, 92 sysmon_envsys_lim_t *, uint32_t *); 93 static void dbcool_set_temp_limits(struct dbcool_softc *, int, 94 sysmon_envsys_lim_t *, uint32_t *); 95 static void dbcool_set_volt_limits(struct dbcool_softc *, int, 96 sysmon_envsys_lim_t *, uint32_t *); 97 static void dbcool_set_fan_limits(struct dbcool_softc *, int, 98 sysmon_envsys_lim_t *, uint32_t *); 99 100 /* SYSCTL Helpers */ 101 SYSCTL_SETUP_PROTO(sysctl_dbcoolsetup); 102 static int sysctl_dbcool_temp(SYSCTLFN_PROTO); 103 static int sysctl_adm1030_temp(SYSCTLFN_PROTO); 104 static int sysctl_adm1030_trange(SYSCTLFN_PROTO); 105 static int sysctl_dbcool_duty(SYSCTLFN_PROTO); 106 static int sysctl_dbcool_behavior(SYSCTLFN_PROTO); 107 static int sysctl_dbcool_slope(SYSCTLFN_PROTO); 108 static int sysctl_dbcool_thyst(SYSCTLFN_PROTO); 109 110 /* Set-up subroutines */ 111 static void dbcool_setup_controllers(struct dbcool_softc *); 112 static int dbcool_setup_sensors(struct dbcool_softc *); 113 static int dbcool_attach_sensor(struct dbcool_softc *, int); 114 static int dbcool_attach_temp_control(struct dbcool_softc *, int, 115 struct chip_id *); 116 117 #ifdef DBCOOL_DEBUG 118 static int sysctl_dbcool_reg_select(SYSCTLFN_PROTO); 119 static int sysctl_dbcool_reg_access(SYSCTLFN_PROTO); 120 #endif /* DBCOOL_DEBUG */ 121 122 /* 123 * Descriptions for SYSCTL entries 124 */ 125 struct dbc_sysctl_info { 126 const char *name; 127 const char *desc; 128 bool lockable; 129 int (*helper)(SYSCTLFN_PROTO); 130 }; 131 132 static struct dbc_sysctl_info dbc_sysctl_table[] = { 133 /* 134 * The first several entries must remain in the same order as the 135 * corresponding entries in enum dbc_pwm_params 136 */ 137 { "behavior", "operating behavior and temp selector", 138 true, sysctl_dbcool_behavior }, 139 { "min_duty", "minimum fan controller PWM duty cycle", 140 true, sysctl_dbcool_duty }, 141 { "max_duty", "maximum fan controller PWM duty cycle", 142 true, sysctl_dbcool_duty }, 143 { "cur_duty", "current fan controller PWM duty cycle", 144 false, sysctl_dbcool_duty }, 145 146 /* 147 * The rest of these should be in the order in which they 148 * are to be stored in the sysctl tree; the table index is 149 * used as the high-order bits of the sysctl_num to maintain 150 * the sequence. 151 * 152 * If you rearrange the order of these items, be sure to 153 * update the sysctl_index in the XXX_sensor_table[] for 154 * the various chips! 155 */ 156 { "Trange", "temp slope/range to reach 100% duty cycle", 157 true, sysctl_dbcool_slope }, 158 { "Tmin", "temp at which to start fan controller", 159 true, sysctl_dbcool_temp }, 160 { "Ttherm", "temp at which THERM is asserted", 161 true, sysctl_dbcool_temp }, 162 { "Thyst", "temp hysteresis for stopping fan controller", 163 true, sysctl_dbcool_thyst }, 164 { "Tmin", "temp at which to start fan controller", 165 true, sysctl_adm1030_temp }, 166 { "Trange", "temp slope/range to reach 100% duty cycle", 167 true, sysctl_adm1030_trange }, 168 }; 169 170 static const char *dbc_sensor_names[] = { 171 "l_temp", "r1_temp", "r2_temp", "Vccp", "Vcc", "fan1", 172 "fan2", "fan3", "fan4", "AIN1", "AIN2", "V2dot5", 173 "V5", "V12", "Vtt", "Imon", "VID" 174 }; 175 176 /* 177 * Following table derived from product data-sheets 178 */ 179 static int64_t nominal_voltages[] = { 180 -1, /* Vcc can be either 3.3 or 5.0V 181 at 3/4 scale */ 182 2249939, /* Vccp 2.25V 3/4 scale */ 183 2497436, /* 2.5VIN 2.5V 3/4 scale */ 184 5002466, /* 5VIN 5V 3/4 scale */ 185 12000000, /* 12VIN 12V 3/4 scale */ 186 1690809, /* Vtt, Imon 2.25V full scale */ 187 1689600, /* AIN1, AIN2 2.25V full scale */ 188 0 189 }; 190 191 /* 192 * Sensor-type, { val-reg, hilim-reg, lolim-reg}, name-idx, sysctl-table-idx, 193 * nom-voltage-index 194 */ 195 struct dbcool_sensor ADT7490_sensor_table[] = { 196 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 197 DBCOOL_LOCAL_HIGHLIM, 198 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 199 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 200 DBCOOL_REMOTE1_HIGHLIM, 201 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 202 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 203 DBCOOL_REMOTE2_HIGHLIM, 204 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 205 { DBC_VOLT, { DBCOOL_VCCP, 206 DBCOOL_VCCP_HIGHLIM, 207 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 208 { DBC_VOLT, { DBCOOL_VCC, 209 DBCOOL_VCC_HIGHLIM, 210 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 211 { DBC_VOLT, { DBCOOL_25VIN, 212 DBCOOL_25VIN_HIGHLIM, 213 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 }, 214 { DBC_VOLT, { DBCOOL_5VIN, 215 DBCOOL_5VIN_HIGHLIM, 216 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 }, 217 { DBC_VOLT, { DBCOOL_12VIN, 218 DBCOOL_12VIN_HIGHLIM, 219 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 }, 220 { DBC_VOLT, { DBCOOL_VTT, 221 DBCOOL_VTT_HIGHLIM, 222 DBCOOL_VTT_LOWLIM }, 14, 0, 5 }, 223 { DBC_VOLT, { DBCOOL_IMON, 224 DBCOOL_IMON_HIGHLIM, 225 DBCOOL_IMON_LOWLIM }, 15, 0, 5 }, 226 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 227 DBCOOL_NO_REG, 228 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 229 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 230 DBCOOL_NO_REG, 231 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 232 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 233 DBCOOL_NO_REG, 234 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 235 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 236 DBCOOL_NO_REG, 237 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 238 { DBC_VID, { DBCOOL_VID_REG, 239 DBCOOL_NO_REG, 240 DBCOOL_NO_REG }, 16, 0, 0 }, 241 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 242 DBCOOL_NO_REG, 243 DBCOOL_NO_REG }, 0, 5, 0 }, 244 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 245 DBCOOL_NO_REG, 246 DBCOOL_NO_REG }, 0, 6, 0 }, 247 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 248 DBCOOL_NO_REG, 249 DBCOOL_NO_REG }, 0, 7, 0 }, 250 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 251 DBCOOL_NO_REG, 252 DBCOOL_NO_REG }, 1, 5, 0 }, 253 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 254 DBCOOL_NO_REG, 255 DBCOOL_NO_REG }, 1, 6, 0 }, 256 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 257 DBCOOL_NO_REG, 258 DBCOOL_NO_REG }, 1, 7, 0 }, 259 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 260 DBCOOL_NO_REG, 261 DBCOOL_NO_REG }, 2, 5, 0 }, 262 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 263 DBCOOL_NO_REG, 264 DBCOOL_NO_REG }, 2, 6, 0 }, 265 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 266 DBCOOL_NO_REG, 267 DBCOOL_NO_REG }, 2, 7, 0 }, 268 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 269 }; 270 271 struct dbcool_sensor ADT7476_sensor_table[] = { 272 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 273 DBCOOL_LOCAL_HIGHLIM, 274 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 275 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 276 DBCOOL_REMOTE1_HIGHLIM, 277 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 278 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 279 DBCOOL_REMOTE2_HIGHLIM, 280 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 281 { DBC_VOLT, { DBCOOL_VCCP, 282 DBCOOL_VCCP_HIGHLIM, 283 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 284 { DBC_VOLT, { DBCOOL_VCC, 285 DBCOOL_VCC_HIGHLIM, 286 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 287 { DBC_VOLT, { DBCOOL_25VIN, 288 DBCOOL_25VIN_HIGHLIM, 289 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 }, 290 { DBC_VOLT, { DBCOOL_5VIN, 291 DBCOOL_5VIN_HIGHLIM, 292 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 }, 293 { DBC_VOLT, { DBCOOL_12VIN, 294 DBCOOL_12VIN_HIGHLIM, 295 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 }, 296 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 297 DBCOOL_NO_REG, 298 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 299 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 300 DBCOOL_NO_REG, 301 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 302 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 303 DBCOOL_NO_REG, 304 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 305 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 306 DBCOOL_NO_REG, 307 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 308 { DBC_VID, { DBCOOL_VID_REG, 309 DBCOOL_NO_REG, 310 DBCOOL_NO_REG }, 16, 0, 0 }, 311 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 312 DBCOOL_NO_REG, 313 DBCOOL_NO_REG }, 0, 5, 0 }, 314 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 315 DBCOOL_NO_REG, 316 DBCOOL_NO_REG }, 0, 6, 0 }, 317 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 318 DBCOOL_NO_REG, 319 DBCOOL_NO_REG }, 0, 7, 0 }, 320 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 321 DBCOOL_NO_REG, 322 DBCOOL_NO_REG }, 1, 5, 0 }, 323 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 324 DBCOOL_NO_REG, 325 DBCOOL_NO_REG }, 1, 6, 0 }, 326 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 327 DBCOOL_NO_REG, 328 DBCOOL_NO_REG }, 1, 7, 0 }, 329 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 330 DBCOOL_NO_REG, 331 DBCOOL_NO_REG }, 2, 5, 0 }, 332 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 333 DBCOOL_NO_REG, 334 DBCOOL_NO_REG }, 2, 6, 0 }, 335 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 336 DBCOOL_NO_REG, 337 DBCOOL_NO_REG }, 2, 7, 0 }, 338 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 339 }; 340 341 struct dbcool_sensor ADT7475_sensor_table[] = { 342 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 343 DBCOOL_LOCAL_HIGHLIM, 344 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 345 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 346 DBCOOL_REMOTE1_HIGHLIM, 347 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 348 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 349 DBCOOL_REMOTE2_HIGHLIM, 350 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 351 { DBC_VOLT, { DBCOOL_VCCP, 352 DBCOOL_VCCP_HIGHLIM, 353 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 354 { DBC_VOLT, { DBCOOL_VCC, 355 DBCOOL_VCC_HIGHLIM, 356 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 357 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 358 DBCOOL_NO_REG, 359 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 360 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 361 DBCOOL_NO_REG, 362 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 363 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 364 DBCOOL_NO_REG, 365 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 366 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 367 DBCOOL_NO_REG, 368 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 369 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 370 DBCOOL_NO_REG, 371 DBCOOL_NO_REG }, 0, 5, 0 }, 372 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 373 DBCOOL_NO_REG, 374 DBCOOL_NO_REG }, 0, 6, 0 }, 375 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 376 DBCOOL_NO_REG, 377 DBCOOL_NO_REG }, 0, 7, 0 }, 378 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 379 DBCOOL_NO_REG, 380 DBCOOL_NO_REG }, 1, 5, 0 }, 381 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 382 DBCOOL_NO_REG, 383 DBCOOL_NO_REG }, 1, 6, 0 }, 384 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 385 DBCOOL_NO_REG, 386 DBCOOL_NO_REG }, 1, 7, 0 }, 387 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 388 DBCOOL_NO_REG, 389 DBCOOL_NO_REG }, 2, 5, 0 }, 390 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 391 DBCOOL_NO_REG, 392 DBCOOL_NO_REG }, 2, 6, 0 }, 393 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 394 DBCOOL_NO_REG, 395 DBCOOL_NO_REG }, 2, 7, 0 }, 396 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 397 }; 398 399 /* 400 * The registers of dbcool_power_control must be in the same order as 401 * in enum dbc_pwm_params 402 */ 403 struct dbcool_power_control ADT7475_power_table[] = { 404 { { DBCOOL_PWM1_CTL, DBCOOL_PWM1_MINDUTY, 405 DBCOOL_PWM1_MAXDUTY, DBCOOL_PWM1_CURDUTY }, 406 "fan_control_1" }, 407 { { DBCOOL_PWM2_CTL, DBCOOL_PWM2_MINDUTY, 408 DBCOOL_PWM2_MAXDUTY, DBCOOL_PWM2_CURDUTY }, 409 "fan_control_2" }, 410 { { DBCOOL_PWM3_CTL, DBCOOL_PWM3_MINDUTY, 411 DBCOOL_PWM3_MAXDUTY, DBCOOL_PWM3_CURDUTY }, 412 "fan_control_3" }, 413 { { 0, 0, 0, 0 }, NULL } 414 }; 415 416 struct dbcool_sensor ADT7466_sensor_table[] = { 417 { DBC_TEMP, { DBCOOL_ADT7466_LCL_TEMP_MSB, 418 DBCOOL_ADT7466_LCL_TEMP_HILIM, 419 DBCOOL_ADT7466_LCL_TEMP_LOLIM }, 0, 0, 0 }, 420 { DBC_TEMP, { DBCOOL_ADT7466_REM_TEMP_MSB, 421 DBCOOL_ADT7466_REM_TEMP_HILIM, 422 DBCOOL_ADT7466_REM_TEMP_LOLIM }, 1, 0, 0 }, 423 { DBC_VOLT, { DBCOOL_ADT7466_VCC, 424 DBCOOL_ADT7466_VCC_HILIM, 425 DBCOOL_ADT7466_VCC_LOLIM }, 4, 0, 0 }, 426 { DBC_VOLT, { DBCOOL_ADT7466_AIN1, 427 DBCOOL_ADT7466_AIN1_HILIM, 428 DBCOOL_ADT7466_AIN1_LOLIM }, 9, 0, 6 }, 429 { DBC_VOLT, { DBCOOL_ADT7466_AIN2, 430 DBCOOL_ADT7466_AIN2_HILIM, 431 DBCOOL_ADT7466_AIN2_LOLIM }, 10, 0, 6 }, 432 { DBC_FAN, { DBCOOL_ADT7466_FANA_LSB, 433 DBCOOL_NO_REG, 434 DBCOOL_ADT7466_FANA_LOLIM_LSB }, 5, 0, 0 }, 435 { DBC_FAN, { DBCOOL_ADT7466_FANB_LSB, 436 DBCOOL_NO_REG, 437 DBCOOL_ADT7466_FANB_LOLIM_LSB }, 6, 0, 0 }, 438 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 439 }; 440 441 struct dbcool_sensor ADM1027_sensor_table[] = { 442 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 443 DBCOOL_LOCAL_HIGHLIM, 444 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 445 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 446 DBCOOL_REMOTE1_HIGHLIM, 447 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 448 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 449 DBCOOL_REMOTE2_HIGHLIM, 450 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 451 { DBC_VOLT, { DBCOOL_VCCP, 452 DBCOOL_VCCP_HIGHLIM, 453 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 454 { DBC_VOLT, { DBCOOL_VCC, 455 DBCOOL_VCC_HIGHLIM, 456 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 457 { DBC_VOLT, { DBCOOL_25VIN, 458 DBCOOL_25VIN_HIGHLIM, 459 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 }, 460 { DBC_VOLT, { DBCOOL_5VIN, 461 DBCOOL_5VIN_HIGHLIM, 462 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 }, 463 { DBC_VOLT, { DBCOOL_12VIN, 464 DBCOOL_12VIN_HIGHLIM, 465 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 }, 466 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 467 DBCOOL_NO_REG, 468 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 469 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 470 DBCOOL_NO_REG, 471 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 472 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 473 DBCOOL_NO_REG, 474 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 475 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 476 DBCOOL_NO_REG, 477 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 478 { DBC_VID, { DBCOOL_VID_REG, 479 DBCOOL_NO_REG, 480 DBCOOL_NO_REG }, 16, 0, 0 }, 481 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 482 DBCOOL_NO_REG, 483 DBCOOL_NO_REG }, 0, 5, 0 }, 484 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 485 DBCOOL_NO_REG, 486 DBCOOL_NO_REG }, 0, 6, 0 }, 487 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 488 DBCOOL_NO_REG, 489 DBCOOL_NO_REG }, 0, 7, 0 }, 490 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 491 DBCOOL_NO_REG, 492 DBCOOL_NO_REG }, 1, 5, 0 }, 493 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 494 DBCOOL_NO_REG, 495 DBCOOL_NO_REG }, 1, 6, 0 }, 496 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 497 DBCOOL_NO_REG, 498 DBCOOL_NO_REG }, 1, 7, 0 }, 499 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 500 DBCOOL_NO_REG, 501 DBCOOL_NO_REG }, 2, 5, 0 }, 502 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 503 DBCOOL_NO_REG, 504 DBCOOL_NO_REG }, 2, 6, 0 }, 505 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 506 DBCOOL_NO_REG, 507 DBCOOL_NO_REG }, 2, 7, 0 }, 508 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 509 }; 510 511 struct dbcool_sensor ADM1030_sensor_table[] = { 512 { DBC_TEMP, { DBCOOL_ADM1030_L_TEMP, 513 DBCOOL_ADM1030_L_HI_LIM, 514 DBCOOL_ADM1030_L_LO_LIM }, 0, 0, 0 }, 515 { DBC_TEMP, { DBCOOL_ADM1030_R_TEMP, 516 DBCOOL_ADM1030_R_HI_LIM, 517 DBCOOL_ADM1030_R_LO_LIM }, 1, 0, 0 }, 518 { DBC_FAN, { DBCOOL_ADM1030_FAN_TACH, 519 DBCOOL_NO_REG, 520 DBCOOL_ADM1030_FAN_LO_LIM }, 5, 0, 0 }, 521 { DBC_CTL, { DBCOOL_ADM1030_L_TMIN, 522 DBCOOL_NO_REG, 523 DBCOOL_NO_REG }, 0, 8, 0 }, 524 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH, 525 DBCOOL_NO_REG, 526 DBCOOL_NO_REG }, 0, 9, 0 }, 527 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH, 528 DBCOOL_NO_REG, 529 DBCOOL_NO_REG }, 0, 6, 0 }, 530 { DBC_CTL, { DBCOOL_ADM1030_R_TMIN, 531 DBCOOL_NO_REG, 532 DBCOOL_NO_REG }, 1, 8, 0 }, 533 { DBC_CTL, { DBCOOL_ADM1030_R_TTHRESH, 534 DBCOOL_NO_REG, 535 DBCOOL_NO_REG }, 1, 9, 0 }, 536 { DBC_CTL, { DBCOOL_ADM1030_R_TTHRESH, 537 DBCOOL_NO_REG, 538 DBCOOL_NO_REG }, 1, 6, 0 }, 539 { DBC_EOF, {0, 0, 0 }, 0, 0, 0 } 540 }; 541 542 struct dbcool_power_control ADM1030_power_table[] = { 543 { { DBCOOL_ADM1030_CFG1, DBCOOL_NO_REG, DBCOOL_NO_REG, 544 DBCOOL_ADM1030_FAN_SPEED_CFG }, 545 "fan_control_1" }, 546 { { 0, 0, 0, 0 }, NULL } 547 }; 548 549 struct dbcool_sensor ADM1031_sensor_table[] = { 550 { DBC_TEMP, { DBCOOL_ADM1030_L_TEMP, 551 DBCOOL_ADM1030_L_HI_LIM, 552 DBCOOL_ADM1030_L_LO_LIM }, 0, 0, 0 }, 553 { DBC_TEMP, { DBCOOL_ADM1030_R_TEMP, 554 DBCOOL_ADM1030_R_HI_LIM, 555 DBCOOL_ADM1030_R_LO_LIM }, 1, 0, 0 }, 556 { DBC_TEMP, { DBCOOL_ADM1031_R2_TEMP, 557 DBCOOL_ADM1031_R2_HI_LIM, 558 DBCOOL_ADM1031_R2_LO_LIM }, 2, 0, 0 }, 559 { DBC_FAN, { DBCOOL_ADM1030_FAN_TACH, 560 DBCOOL_NO_REG, 561 DBCOOL_ADM1030_FAN_LO_LIM }, 5, 0, 0 }, 562 { DBC_FAN, { DBCOOL_ADM1031_FAN2_TACH, 563 DBCOOL_NO_REG, 564 DBCOOL_ADM1031_FAN2_LO_LIM }, 6, 0, 0 }, 565 { DBC_CTL, { DBCOOL_ADM1030_L_TMIN, 566 DBCOOL_NO_REG, 567 DBCOOL_NO_REG }, 0, 8, 0 }, 568 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH, 569 DBCOOL_NO_REG, 570 DBCOOL_NO_REG }, 0, 9, 0 }, 571 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH, 572 DBCOOL_NO_REG, 573 DBCOOL_NO_REG }, 0, 6, 0 }, 574 { DBC_CTL, { DBCOOL_ADM1030_R_TMIN, 575 DBCOOL_NO_REG, 576 DBCOOL_NO_REG }, 1, 8, 0 }, 577 { DBC_CTL, { DBCOOL_ADM1030_R_TTHRESH, 578 DBCOOL_NO_REG, 579 DBCOOL_NO_REG }, 1, 9, 0 }, 580 { DBC_CTL, { DBCOOL_ADM1030_R_TTHRESH, 581 DBCOOL_NO_REG, 582 DBCOOL_NO_REG }, 1, 6, 0 }, 583 { DBC_CTL, { DBCOOL_ADM1031_R2_TMIN, 584 DBCOOL_NO_REG, 585 DBCOOL_NO_REG }, 2, 8, 0 }, 586 { DBC_CTL, { DBCOOL_ADM1031_R2_TTHRESH, 587 DBCOOL_NO_REG, 588 DBCOOL_NO_REG }, 2, 9, 0 }, 589 { DBC_CTL, { DBCOOL_ADM1031_R2_TTHRESH, 590 DBCOOL_NO_REG, 591 DBCOOL_NO_REG }, 2, 6, 0 }, 592 { DBC_EOF, {0, 0, 0 }, 0, 0, 0 } 593 }; 594 595 struct dbcool_power_control ADM1031_power_table[] = { 596 { { DBCOOL_ADM1030_CFG1, DBCOOL_NO_REG, DBCOOL_NO_REG, 597 DBCOOL_ADM1030_FAN_SPEED_CFG }, 598 "fan_control_1" }, 599 { { DBCOOL_ADM1030_CFG1, DBCOOL_NO_REG, DBCOOL_NO_REG, 600 DBCOOL_ADM1030_FAN_SPEED_CFG }, 601 "fan_control_2" }, 602 { { 0, 0, 0, 0 }, NULL } 603 }; 604 605 struct dbcool_sensor EMC6D103S_sensor_table[] = { 606 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 607 DBCOOL_LOCAL_HIGHLIM, 608 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 609 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 610 DBCOOL_REMOTE1_HIGHLIM, 611 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 612 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 613 DBCOOL_REMOTE2_HIGHLIM, 614 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 615 { DBC_VOLT, { DBCOOL_VCCP, 616 DBCOOL_VCCP_HIGHLIM, 617 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 618 { DBC_VOLT, { DBCOOL_VCC, 619 DBCOOL_VCC_HIGHLIM, 620 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 621 { DBC_VOLT, { DBCOOL_25VIN, 622 DBCOOL_25VIN_HIGHLIM, 623 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 }, 624 { DBC_VOLT, { DBCOOL_5VIN, 625 DBCOOL_5VIN_HIGHLIM, 626 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 }, 627 { DBC_VOLT, { DBCOOL_12VIN, 628 DBCOOL_12VIN_HIGHLIM, 629 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 }, 630 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 631 DBCOOL_NO_REG, 632 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 633 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 634 DBCOOL_NO_REG, 635 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 636 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 637 DBCOOL_NO_REG, 638 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 639 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 640 DBCOOL_NO_REG, 641 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 642 { DBC_VID, { DBCOOL_VID_REG, 643 DBCOOL_NO_REG, 644 DBCOOL_NO_REG }, 16, 0, 0 }, 645 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 646 DBCOOL_NO_REG, 647 DBCOOL_NO_REG }, 0, 5, 0 }, 648 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 649 DBCOOL_NO_REG, 650 DBCOOL_NO_REG }, 0, 6, 0 }, 651 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 652 DBCOOL_NO_REG, 653 DBCOOL_NO_REG }, 1, 5, 0 }, 654 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 655 DBCOOL_NO_REG, 656 DBCOOL_NO_REG }, 1, 6, 0 }, 657 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 658 DBCOOL_NO_REG, 659 DBCOOL_NO_REG }, 2, 5, 0 }, 660 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 661 DBCOOL_NO_REG, 662 DBCOOL_NO_REG }, 2, 6, 0 }, 663 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 664 }; 665 666 struct chip_id chip_table[] = { 667 { DBCOOL_COMPANYID, ADT7490_DEVICEID, ADT7490_REV_ID, 668 ADT7490_sensor_table, ADT7475_power_table, 669 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_PECI, 670 90000 * 60, "ADT7490" }, 671 { DBCOOL_COMPANYID, ADT7476_DEVICEID, 0xff, 672 ADT7476_sensor_table, ADT7475_power_table, 673 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY, 674 90000 * 60, "ADT7476" }, 675 { DBCOOL_COMPANYID, ADT7475_DEVICEID, 0xff, 676 ADT7475_sensor_table, ADT7475_power_table, 677 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_SHDN, 678 90000 * 60, "ADT7475" }, 679 { DBCOOL_COMPANYID, ADT7473_DEVICEID, ADT7473_REV_ID1, 680 ADT7475_sensor_table, ADT7475_power_table, 681 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_SHDN, 682 90000 * 60, "ADT7460/ADT7463" }, 683 { DBCOOL_COMPANYID, ADT7473_DEVICEID, ADT7473_REV_ID2, 684 ADT7475_sensor_table, ADT7475_power_table, 685 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_SHDN, 686 90000 * 60, "ADT7463-1" }, 687 { DBCOOL_COMPANYID, ADT7468_DEVICEID, 0xff, 688 ADT7476_sensor_table, ADT7475_power_table, 689 DBCFLAG_TEMPOFFSET | DBCFLAG_MULTI_VCC | DBCFLAG_HAS_MAXDUTY | 690 DBCFLAG_4BIT_VER | DBCFLAG_HAS_SHDN, 691 90000 * 60, "ADT7467/ADT7468" }, 692 { DBCOOL_COMPANYID, ADT7466_DEVICEID, 0xff, 693 ADT7466_sensor_table, NULL, 694 DBCFLAG_ADT7466 | DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_SHDN, 695 82000 * 60, "ADT7466" }, 696 { DBCOOL_COMPANYID, ADT7463_DEVICEID, ADT7463_REV_ID1, 697 ADM1027_sensor_table, ADT7475_power_table, 698 DBCFLAG_MULTI_VCC | DBCFLAG_4BIT_VER | DBCFLAG_HAS_SHDN, 699 90000 * 60, "ADT7463" }, 700 { DBCOOL_COMPANYID, ADT7463_DEVICEID, ADT7463_REV_ID2, 701 ADM1027_sensor_table, ADT7475_power_table, 702 DBCFLAG_MULTI_VCC | DBCFLAG_4BIT_VER | DBCFLAG_HAS_SHDN | 703 DBCFLAG_HAS_VID_SEL, 704 90000 * 60, "ADT7463" }, 705 { DBCOOL_COMPANYID, ADM1027_DEVICEID, ADM1027_REV_ID, 706 ADM1027_sensor_table, ADT7475_power_table, 707 DBCFLAG_MULTI_VCC | DBCFLAG_4BIT_VER, 708 90000 * 60, "ADM1027" }, 709 { DBCOOL_COMPANYID, ADM1030_DEVICEID, 0xff, 710 ADM1030_sensor_table, ADM1030_power_table, 711 DBCFLAG_ADM1030 | DBCFLAG_NO_READBYTE, 712 11250 * 60, "ADM1030" }, 713 { DBCOOL_COMPANYID, ADM1031_DEVICEID, 0xff, 714 ADM1031_sensor_table, ADM1030_power_table, 715 DBCFLAG_ADM1030 | DBCFLAG_NO_READBYTE, 716 11250 * 60, "ADM1031" }, 717 { SMSC_COMPANYID, EMC6D103S_DEVICEID, EMC6D103S_REV_ID, 718 EMC6D103S_sensor_table, ADT7475_power_table, 719 DBCFLAG_4BIT_VER, 720 90000 * 60, "EMC6D103S" }, 721 { 0, 0, 0, NULL, NULL, 0, 0, NULL } 722 }; 723 724 static const char *behavior[] = { 725 "remote1", "local", "remote2", "full-speed", 726 "disabled", "local+remote2","all-temps", "manual" 727 }; 728 729 static char dbcool_cur_behav[16]; 730 731 CFATTACH_DECL_NEW(dbcool, sizeof(struct dbcool_softc), 732 dbcool_match, dbcool_attach, dbcool_detach, NULL); 733 734 static const char * dbcool_compats[] = { 735 "i2c-adm1031", 736 "adt7467", 737 "adt7460", 738 "adm1030", 739 NULL 740 }; 741 742 static const struct device_compatible_entry dbcool_compat_data[] = { 743 DEVICE_COMPAT_ENTRY(dbcool_compats), 744 DEVICE_COMPAT_TERMINATOR 745 }; 746 747 int 748 dbcool_match(device_t parent, cfdata_t cf, void *aux) 749 { 750 struct i2c_attach_args *ia = aux; 751 struct dbcool_chipset dc; 752 dc.dc_tag = ia->ia_tag; 753 dc.dc_addr = ia->ia_addr; 754 dc.dc_chip = NULL; 755 dc.dc_readreg = dbcool_readreg; 756 dc.dc_writereg = dbcool_writereg; 757 int match_result; 758 759 if (iic_use_direct_match(ia, cf, dbcool_compat_data, &match_result)) 760 return match_result; 761 762 if ((ia->ia_addr & DBCOOL_ADDRMASK) != DBCOOL_ADDR) 763 return 0; 764 if (dbcool_chip_ident(&dc) >= 0) 765 return I2C_MATCH_ADDRESS_AND_PROBE; 766 767 return 0; 768 } 769 770 void 771 dbcool_attach(device_t parent, device_t self, void *aux) 772 { 773 struct dbcool_softc *sc = device_private(self); 774 struct i2c_attach_args *args = aux; 775 uint8_t ver; 776 777 sc->sc_dc.dc_addr = args->ia_addr; 778 sc->sc_dc.dc_tag = args->ia_tag; 779 sc->sc_dc.dc_chip = NULL; 780 sc->sc_dc.dc_readreg = dbcool_readreg; 781 sc->sc_dc.dc_writereg = dbcool_writereg; 782 (void)dbcool_chip_ident(&sc->sc_dc); 783 sc->sc_dev = self; 784 785 aprint_naive("\n"); 786 aprint_normal("\n"); 787 788 ver = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_REVISION_REG); 789 if (sc->sc_dc.dc_chip->flags & DBCFLAG_4BIT_VER) 790 if (sc->sc_dc.dc_chip->company == SMSC_COMPANYID) 791 { 792 aprint_normal_dev(self, "SMSC %s Controller " 793 "(rev 0x%02x, stepping 0x%02x)\n", 794 sc->sc_dc.dc_chip->name, ver >> 4, ver & 0x0f); 795 } else { 796 aprint_normal_dev(self, "%s dBCool(tm) Controller " 797 "(rev 0x%02x, stepping 0x%02x)\n", 798 sc->sc_dc.dc_chip->name, ver >> 4, ver & 0x0f); 799 } 800 else 801 aprint_normal_dev(self, "%s dBCool(tm) Controller " 802 "(rev 0x%04x)\n", sc->sc_dc.dc_chip->name, ver); 803 804 sc->sc_sysctl_log = NULL; 805 806 #ifdef _MODULE 807 sysctl_dbcoolsetup(&sc->sc_sysctl_log); 808 #endif 809 810 dbcool_setup(self); 811 812 if (!pmf_device_register(self, dbcool_pmf_suspend, dbcool_pmf_resume)) 813 aprint_error_dev(self, "couldn't establish power handler\n"); 814 } 815 816 static int 817 dbcool_detach(device_t self, int flags) 818 { 819 struct dbcool_softc *sc = device_private(self); 820 821 pmf_device_deregister(self); 822 823 sysmon_envsys_unregister(sc->sc_sme); 824 825 sysctl_teardown(&sc->sc_sysctl_log); 826 827 sc->sc_sme = NULL; 828 return 0; 829 } 830 831 /* On suspend, we save the state of the SHDN bit, then set it */ 832 bool dbcool_pmf_suspend(device_t dev, const pmf_qual_t *qual) 833 { 834 struct dbcool_softc *sc = device_private(dev); 835 uint8_t reg, bit, cfg; 836 837 if ((sc->sc_dc.dc_chip->flags & DBCFLAG_HAS_SHDN) == 0) 838 return true; 839 840 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) { 841 reg = DBCOOL_ADT7466_CONFIG2; 842 bit = DBCOOL_ADT7466_CFG2_SHDN; 843 } else { 844 reg = DBCOOL_CONFIG2_REG; 845 bit = DBCOOL_CFG2_SHDN; 846 } 847 cfg = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 848 sc->sc_suspend = cfg & bit; 849 cfg |= bit; 850 sc->sc_dc.dc_writereg(&sc->sc_dc, reg, cfg); 851 852 return true; 853 } 854 855 /* On resume, we restore the previous state of the SHDN bit (which 856 we saved in sc_suspend) */ 857 bool dbcool_pmf_resume(device_t dev, const pmf_qual_t *qual) 858 { 859 struct dbcool_softc *sc = device_private(dev); 860 uint8_t reg, cfg; 861 862 if ((sc->sc_dc.dc_chip->flags & DBCFLAG_HAS_SHDN) == 0) 863 return true; 864 865 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) { 866 reg = DBCOOL_ADT7466_CONFIG2; 867 } else { 868 reg = DBCOOL_CONFIG2_REG; 869 } 870 cfg = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 871 cfg &= ~sc->sc_suspend; 872 sc->sc_dc.dc_writereg(&sc->sc_dc, reg, cfg); 873 874 return true; 875 876 } 877 878 uint8_t 879 dbcool_readreg(struct dbcool_chipset *dc, uint8_t reg) 880 { 881 uint8_t data = 0; 882 883 if (iic_acquire_bus(dc->dc_tag, 0) != 0) 884 return data; 885 886 if (dc->dc_chip == NULL || dc->dc_chip->flags & DBCFLAG_NO_READBYTE) { 887 /* ADM1027 doesn't support i2c read_byte protocol */ 888 if (iic_smbus_send_byte(dc->dc_tag, dc->dc_addr, reg, 0) != 0) 889 goto bad; 890 (void)iic_smbus_receive_byte(dc->dc_tag, dc->dc_addr, &data, 0); 891 } else 892 (void)iic_smbus_read_byte(dc->dc_tag, dc->dc_addr, reg, &data, 893 0); 894 895 bad: 896 iic_release_bus(dc->dc_tag, 0); 897 return data; 898 } 899 900 void 901 dbcool_writereg(struct dbcool_chipset *dc, uint8_t reg, uint8_t val) 902 { 903 if (iic_acquire_bus(dc->dc_tag, 0) != 0) 904 return; 905 906 (void)iic_smbus_write_byte(dc->dc_tag, dc->dc_addr, reg, val, 0); 907 908 iic_release_bus(dc->dc_tag, 0); 909 } 910 911 static bool 912 dbcool_islocked(struct dbcool_softc *sc) 913 { 914 uint8_t cfg_reg; 915 916 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 917 return 0; 918 919 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) 920 cfg_reg = DBCOOL_ADT7466_CONFIG1; 921 else 922 cfg_reg = DBCOOL_CONFIG1_REG; 923 924 if (sc->sc_dc.dc_readreg(&sc->sc_dc, cfg_reg) & DBCOOL_CFG1_LOCK) 925 return 1; 926 else 927 return 0; 928 } 929 930 static int 931 dbcool_read_temp(struct dbcool_softc *sc, uint8_t reg, bool extres) 932 { 933 uint8_t t1, t2, t3, val, ext = 0; 934 int temp; 935 936 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) { 937 /* 938 * ADT7466 temps are in strange location 939 */ 940 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADT7466_CONFIG1); 941 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 942 if (extres) 943 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, reg + 1); 944 } else if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) { 945 /* 946 * ADM1030 temps are in their own special place, too 947 */ 948 if (extres) { 949 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_TEMP_EXTRES); 950 if (reg == DBCOOL_ADM1030_L_TEMP) 951 ext >>= 6; 952 else if (reg == DBCOOL_ADM1031_R2_TEMP) 953 ext >>= 4; 954 else 955 ext >>= 1; 956 ext &= 0x03; 957 } 958 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 959 } else if (extres) { 960 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES2_REG); 961 962 /* Read all msb regs to unlatch them */ 963 t1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_12VIN); 964 t1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_REMOTE1_TEMP); 965 t2 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_REMOTE2_TEMP); 966 t3 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_LOCAL_TEMP); 967 switch (reg) { 968 case DBCOOL_REMOTE1_TEMP: 969 val = t1; 970 ext >>= 2; 971 break; 972 case DBCOOL_LOCAL_TEMP: 973 val = t3; 974 ext >>= 4; 975 break; 976 case DBCOOL_REMOTE2_TEMP: 977 val = t2; 978 ext >>= 6; 979 break; 980 default: 981 val = 0; 982 break; 983 } 984 ext &= 0x03; 985 } 986 else 987 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 988 989 /* Check for invalid temp values */ 990 if ((sc->sc_temp_offset == 0 && val == 0x80) || 991 (sc->sc_temp_offset != 0 && val == 0)) 992 return 0; 993 994 /* If using offset mode, adjust, else treat as signed */ 995 if (sc->sc_temp_offset) { 996 temp = val; 997 temp -= sc->sc_temp_offset; 998 } else 999 temp = (int8_t)val; 1000 1001 /* Convert degC to uK and include extended precision bits */ 1002 temp *= 1000000; 1003 temp += 250000 * (int)ext; 1004 temp += 273150000U; 1005 1006 return temp; 1007 } 1008 1009 static int 1010 dbcool_read_rpm(struct dbcool_softc *sc, uint8_t reg) 1011 { 1012 int rpm; 1013 uint8_t rpm_lo, rpm_hi; 1014 1015 rpm_lo = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 1016 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 1017 rpm_hi = (rpm_lo == 0xff)?0xff:0x0; 1018 else 1019 rpm_hi = sc->sc_dc.dc_readreg(&sc->sc_dc, reg + 1); 1020 1021 rpm = (rpm_hi << 8) | rpm_lo; 1022 if (rpm == 0xffff) 1023 return 0; /* 0xffff indicates stalled/failed fan */ 1024 1025 /* don't divide by zero */ 1026 return (rpm == 0)? 0 : (sc->sc_dc.dc_chip->rpm_dividend / rpm); 1027 } 1028 1029 /* Provide chip's supply voltage, in microvolts */ 1030 static int 1031 dbcool_supply_voltage(struct dbcool_softc *sc) 1032 { 1033 if (sc->sc_dc.dc_chip->flags & DBCFLAG_MULTI_VCC) { 1034 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_CONFIG1_REG) & DBCOOL_CFG1_Vcc) 1035 return 5002500; 1036 else 1037 return 3300000; 1038 } else if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) { 1039 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADT7466_CONFIG1) & 1040 DBCOOL_ADT7466_CFG1_Vcc) 1041 return 5000000; 1042 else 1043 return 3300000; 1044 } else 1045 return 3300000; 1046 } 1047 1048 /* 1049 * Nominal voltages are calculated in microvolts 1050 */ 1051 static int 1052 dbcool_read_volt(struct dbcool_softc *sc, uint8_t reg, int nom_idx, bool extres) 1053 { 1054 uint8_t ext = 0, v1, v2, v3, v4, val; 1055 int64_t ret; 1056 int64_t nom; 1057 1058 nom = nominal_voltages[nom_idx]; 1059 if (nom < 0) 1060 nom = sc->sc_supply_voltage; 1061 1062 /* ADT7466 voltages are in strange locations with only 8-bits */ 1063 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) 1064 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 1065 else 1066 /* 1067 * It's a "normal" dbCool chip - check for regs that 1068 * share extended resolution bits since we have to 1069 * read all the MSB registers to unlatch them. 1070 */ 1071 if (!extres) 1072 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 1073 else if (reg == DBCOOL_12VIN) { 1074 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES2_REG) & 0x03; 1075 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 1076 (void)dbcool_read_temp(sc, DBCOOL_LOCAL_TEMP, true); 1077 } else if (reg == DBCOOL_VTT || reg == DBCOOL_IMON) { 1078 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES_VTT_IMON); 1079 v1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_IMON); 1080 v2 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VTT); 1081 if (reg == DBCOOL_IMON) { 1082 val = v1; 1083 ext >>= 6; 1084 } else { 1085 val = v2; 1086 ext >>= 4; 1087 } 1088 ext &= 0x0f; 1089 } else { 1090 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES1_REG); 1091 v1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_25VIN); 1092 v2 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VCCP); 1093 v3 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VCC); 1094 v4 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_5VIN); 1095 1096 switch (reg) { 1097 case DBCOOL_25VIN: 1098 val = v1; 1099 break; 1100 case DBCOOL_VCCP: 1101 val = v2; 1102 ext >>= 2; 1103 break; 1104 case DBCOOL_VCC: 1105 val = v3; 1106 ext >>= 4; 1107 break; 1108 case DBCOOL_5VIN: 1109 val = v4; 1110 ext >>= 6; 1111 break; 1112 default: 1113 val = nom = 0; 1114 } 1115 ext &= 0x03; 1116 } 1117 1118 /* 1119 * Scale the nominal value by the 10-bit fraction 1120 * 1121 * Returned value is in microvolts. 1122 */ 1123 ret = val; 1124 ret <<= 2; 1125 ret |= ext; 1126 ret = (ret * nom) / 0x300; 1127 1128 return ret; 1129 } 1130 1131 static int 1132 sysctl_dbcool_temp(SYSCTLFN_ARGS) 1133 { 1134 struct sysctlnode node; 1135 struct dbcool_softc *sc; 1136 int reg, error; 1137 uint8_t chipreg; 1138 uint8_t newreg; 1139 1140 node = *rnode; 1141 sc = (struct dbcool_softc *)node.sysctl_data; 1142 chipreg = node.sysctl_num & 0xff; 1143 1144 if (sc->sc_temp_offset) { 1145 reg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1146 reg -= sc->sc_temp_offset; 1147 } else 1148 reg = (int8_t)sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1149 1150 node.sysctl_data = ® 1151 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1152 1153 if (error || newp == NULL) 1154 return error; 1155 1156 /* We were asked to update the value - sanity check before writing */ 1157 if (*(int *)node.sysctl_data < -64 || 1158 *(int *)node.sysctl_data > 127 + sc->sc_temp_offset) 1159 return EINVAL; 1160 1161 newreg = *(int *)node.sysctl_data; 1162 newreg += sc->sc_temp_offset; 1163 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1164 return 0; 1165 } 1166 1167 static int 1168 sysctl_adm1030_temp(SYSCTLFN_ARGS) 1169 { 1170 struct sysctlnode node; 1171 struct dbcool_softc *sc; 1172 int reg, error; 1173 uint8_t chipreg, oldreg, newreg; 1174 1175 node = *rnode; 1176 sc = (struct dbcool_softc *)node.sysctl_data; 1177 chipreg = node.sysctl_num & 0xff; 1178 1179 oldreg = (int8_t)sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1180 reg = (oldreg >> 1) & ~0x03; 1181 1182 node.sysctl_data = ® 1183 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1184 1185 if (error || newp == NULL) 1186 return error; 1187 1188 /* We were asked to update the value - sanity check before writing */ 1189 if (*(int *)node.sysctl_data < 0 || *(int *)node.sysctl_data > 127) 1190 return EINVAL; 1191 1192 newreg = *(int *)node.sysctl_data; 1193 newreg &= ~0x03; 1194 newreg <<= 1; 1195 newreg |= (oldreg & 0x07); 1196 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1197 return 0; 1198 } 1199 1200 static int 1201 sysctl_adm1030_trange(SYSCTLFN_ARGS) 1202 { 1203 struct sysctlnode node; 1204 struct dbcool_softc *sc; 1205 int reg, error, newval; 1206 uint8_t chipreg, oldreg, newreg; 1207 1208 node = *rnode; 1209 sc = (struct dbcool_softc *)node.sysctl_data; 1210 chipreg = node.sysctl_num & 0xff; 1211 1212 oldreg = (int8_t)sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1213 reg = oldreg & 0x07; 1214 1215 node.sysctl_data = ® 1216 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1217 1218 if (error || newp == NULL) 1219 return error; 1220 1221 /* We were asked to update the value - sanity check before writing */ 1222 newval = *(int *)node.sysctl_data; 1223 1224 if (newval == 5) 1225 newreg = 0; 1226 else if (newval == 10) 1227 newreg = 1; 1228 else if (newval == 20) 1229 newreg = 2; 1230 else if (newval == 40) 1231 newreg = 3; 1232 else if (newval == 80) 1233 newreg = 4; 1234 else 1235 return EINVAL; 1236 1237 newreg |= (oldreg & ~0x07); 1238 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1239 return 0; 1240 } 1241 1242 static int 1243 sysctl_dbcool_duty(SYSCTLFN_ARGS) 1244 { 1245 struct sysctlnode node; 1246 struct dbcool_softc *sc; 1247 int reg, error; 1248 uint8_t chipreg, oldreg, newreg; 1249 1250 node = *rnode; 1251 sc = (struct dbcool_softc *)node.sysctl_data; 1252 chipreg = node.sysctl_num & 0xff; 1253 1254 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1255 reg = (uint32_t)oldreg; 1256 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 1257 reg = ((reg & 0x0f) * 100) / 15; 1258 else 1259 reg = (reg * 100) / 255; 1260 node.sysctl_data = ® 1261 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1262 1263 if (error || newp == NULL) 1264 return error; 1265 1266 /* We were asked to update the value - sanity check before writing */ 1267 if (*(int *)node.sysctl_data < 0 || *(int *)node.sysctl_data > 100) 1268 return EINVAL; 1269 1270 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) { 1271 newreg = *(uint8_t *)(node.sysctl_data) * 15 / 100; 1272 newreg |= oldreg & 0xf0; 1273 } else 1274 newreg = *(uint8_t *)(node.sysctl_data) * 255 / 100; 1275 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1276 return 0; 1277 } 1278 1279 static int 1280 sysctl_dbcool_behavior(SYSCTLFN_ARGS) 1281 { 1282 struct sysctlnode node; 1283 struct dbcool_softc *sc; 1284 int i, reg, error; 1285 uint8_t chipreg, oldreg, newreg; 1286 1287 node = *rnode; 1288 sc = (struct dbcool_softc *)node.sysctl_data; 1289 chipreg = node.sysctl_num & 0xff; 1290 1291 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1292 1293 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) { 1294 if ((sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_CFG2) & 1) == 0) 1295 reg = 4; 1296 else if ((oldreg & 0x80) == 0) 1297 reg = 7; 1298 else if ((oldreg & 0x60) == 0) 1299 reg = 4; 1300 else 1301 reg = 6; 1302 } else 1303 reg = (oldreg >> 5) & 0x07; 1304 1305 strlcpy(dbcool_cur_behav, behavior[reg], sizeof(dbcool_cur_behav)); 1306 node.sysctl_data = dbcool_cur_behav; 1307 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1308 1309 if (error || newp == NULL) 1310 return error; 1311 1312 /* We were asked to update the value - convert string to value */ 1313 newreg = __arraycount(behavior); 1314 for (i = 0; i < __arraycount(behavior); i++) 1315 if (strcmp(node.sysctl_data, behavior[i]) == 0) 1316 break; 1317 if (i >= __arraycount(behavior)) 1318 return EINVAL; 1319 1320 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) { 1321 /* 1322 * ADM1030 splits fan controller behavior across two 1323 * registers. We also do not support Auto-Filter mode 1324 * nor do we support Manual-RPM-feedback. 1325 */ 1326 if (newreg == 4) { 1327 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_CFG2); 1328 oldreg &= ~0x01; 1329 sc->sc_dc.dc_writereg(&sc->sc_dc, DBCOOL_ADM1030_CFG2, oldreg); 1330 } else { 1331 if (newreg == 0) 1332 newreg = 4; 1333 else if (newreg == 6) 1334 newreg = 7; 1335 else if (newreg == 7) 1336 newreg = 0; 1337 else 1338 return EINVAL; 1339 newreg <<= 5; 1340 newreg |= (oldreg & 0x1f); 1341 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1342 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_CFG2) | 1; 1343 sc->sc_dc.dc_writereg(&sc->sc_dc, DBCOOL_ADM1030_CFG2, oldreg); 1344 } 1345 } else { 1346 newreg = (sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg) & 0x1f) | (i << 5); 1347 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1348 } 1349 return 0; 1350 } 1351 1352 static int 1353 sysctl_dbcool_slope(SYSCTLFN_ARGS) 1354 { 1355 struct sysctlnode node; 1356 struct dbcool_softc *sc; 1357 int reg, error; 1358 uint8_t chipreg; 1359 uint8_t newreg; 1360 1361 node = *rnode; 1362 sc = (struct dbcool_softc *)node.sysctl_data; 1363 chipreg = node.sysctl_num & 0xff; 1364 1365 reg = (sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg) >> 4) & 0x0f; 1366 node.sysctl_data = ® 1367 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1368 1369 if (error || newp == NULL) 1370 return error; 1371 1372 /* We were asked to update the value - sanity check before writing */ 1373 if (*(int *)node.sysctl_data < 0 || *(int *)node.sysctl_data > 0x0f) 1374 return EINVAL; 1375 1376 newreg = (sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg) & 0x0f) | 1377 (*(int *)node.sysctl_data << 4); 1378 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1379 return 0; 1380 } 1381 1382 static int 1383 sysctl_dbcool_thyst(SYSCTLFN_ARGS) 1384 { 1385 struct sysctlnode node; 1386 struct dbcool_softc *sc; 1387 int reg, error; 1388 uint8_t chipreg; 1389 uint8_t newreg, newhyst; 1390 1391 node = *rnode; 1392 sc = (struct dbcool_softc *)node.sysctl_data; 1393 chipreg = node.sysctl_num & 0x7f; 1394 1395 /* retrieve 4-bit value */ 1396 newreg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1397 if ((node.sysctl_num & 0x80) == 0) 1398 reg = newreg >> 4; 1399 else 1400 reg = newreg; 1401 reg = reg & 0x0f; 1402 1403 node.sysctl_data = ® 1404 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1405 1406 if (error || newp == NULL) 1407 return error; 1408 1409 /* We were asked to update the value - sanity check before writing */ 1410 newhyst = *(int *)node.sysctl_data; 1411 if (newhyst > 0x0f) 1412 return EINVAL; 1413 1414 /* Insert new value into field and update register */ 1415 if ((node.sysctl_num & 0x80) == 0) { 1416 newreg &= 0x0f; 1417 newreg |= (newhyst << 4); 1418 } else { 1419 newreg &= 0xf0; 1420 newreg |= newhyst; 1421 } 1422 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1423 return 0; 1424 } 1425 1426 #ifdef DBCOOL_DEBUG 1427 1428 /* 1429 * These routines can be used for debugging. reg_select is used to 1430 * select any arbitrary register in the device. reg_access is used 1431 * to read (and optionally update) the selected register. 1432 * 1433 * No attempt is made to validate the data passed. If you use these 1434 * routines, you are assumed to know what you're doing! 1435 * 1436 * Caveat user 1437 */ 1438 static int 1439 sysctl_dbcool_reg_select(SYSCTLFN_ARGS) 1440 { 1441 struct sysctlnode node; 1442 struct dbcool_softc *sc; 1443 int reg, error; 1444 1445 node = *rnode; 1446 sc = (struct dbcool_softc *)node.sysctl_data; 1447 1448 reg = sc->sc_user_reg; 1449 node.sysctl_data = ® 1450 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1451 1452 if (error || newp == NULL) 1453 return error; 1454 1455 sc->sc_user_reg = *(int *)node.sysctl_data; 1456 return 0; 1457 } 1458 1459 static int 1460 sysctl_dbcool_reg_access(SYSCTLFN_ARGS) 1461 { 1462 struct sysctlnode node; 1463 struct dbcool_softc *sc; 1464 int reg, error; 1465 uint8_t chipreg; 1466 uint8_t newreg; 1467 1468 node = *rnode; 1469 sc = (struct dbcool_softc *)node.sysctl_data; 1470 chipreg = sc->sc_user_reg; 1471 1472 reg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1473 node.sysctl_data = ® 1474 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1475 1476 if (error || newp == NULL) 1477 return error; 1478 1479 newreg = *(int *)node.sysctl_data; 1480 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1481 return 0; 1482 } 1483 #endif /* DBCOOL_DEBUG */ 1484 1485 /* 1486 * Encode an index number and register number for use as a sysctl_num 1487 * so we can select the correct device register later. 1488 */ 1489 #define DBC_PWM_SYSCTL(seq, reg) ((seq << 8) | reg) 1490 1491 void 1492 dbcool_setup(device_t self) 1493 { 1494 struct dbcool_softc *sc = device_private(self); 1495 const struct sysctlnode *me = NULL; 1496 #ifdef DBCOOL_DEBUG 1497 struct sysctlnode *node = NULL; 1498 #endif 1499 uint8_t cfg_val, cfg_reg; 1500 int ret, error; 1501 1502 /* 1503 * Some chips are capable of reporting an extended temperature range 1504 * by default. On these models, config register 5 bit 0 can be set 1505 * to 1 for compatability with other chips that report 2s complement. 1506 */ 1507 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) { 1508 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADT7466_CONFIG1) & 0x80) 1509 sc->sc_temp_offset = 64; 1510 else 1511 sc->sc_temp_offset = 0; 1512 } else if (sc->sc_dc.dc_chip->flags & DBCFLAG_TEMPOFFSET) { 1513 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_CONFIG5_REG) & 1514 DBCOOL_CFG5_TWOSCOMP) 1515 sc->sc_temp_offset = 0; 1516 else 1517 sc->sc_temp_offset = 64; 1518 } else 1519 sc->sc_temp_offset = 0; 1520 1521 /* Determine Vcc for this chip */ 1522 sc->sc_supply_voltage = dbcool_supply_voltage(sc); 1523 1524 ret = sysctl_createv(&sc->sc_sysctl_log, 0, NULL, &me, 1525 CTLFLAG_READWRITE, 1526 CTLTYPE_NODE, device_xname(self), NULL, 1527 NULL, 0, NULL, 0, 1528 CTL_HW, CTL_CREATE, CTL_EOL); 1529 if (ret == 0) 1530 sc->sc_root_sysctl_num = me->sysctl_num; 1531 else 1532 sc->sc_root_sysctl_num = 0; 1533 1534 aprint_debug_dev(self, 1535 "Supply voltage %"PRId64".%06"PRId64"V, %s temp range\n", 1536 sc->sc_supply_voltage / 1000000, 1537 sc->sc_supply_voltage % 1000000, 1538 sc->sc_temp_offset ? "extended" : "normal"); 1539 1540 /* Create the sensors for this device */ 1541 sc->sc_sme = sysmon_envsys_create(); 1542 if (dbcool_setup_sensors(sc)) 1543 goto out; 1544 1545 if (sc->sc_root_sysctl_num != 0) { 1546 /* If supported, create sysctl tree for fan PWM controllers */ 1547 if (sc->sc_dc.dc_chip->power != NULL) 1548 dbcool_setup_controllers(sc); 1549 1550 #ifdef DBCOOL_DEBUG 1551 ret = sysctl_createv(&sc->sc_sysctl_log, 0, NULL, 1552 (void *)&node, 1553 CTLFLAG_READWRITE, CTLTYPE_INT, "reg_select", NULL, 1554 sysctl_dbcool_reg_select, 1555 0, (void *)sc, sizeof(int), 1556 CTL_HW, me->sysctl_num, CTL_CREATE, CTL_EOL); 1557 if (node != NULL) 1558 node->sysctl_data = sc; 1559 1560 ret = sysctl_createv(&sc->sc_sysctl_log, 0, NULL, 1561 (void *)&node, 1562 CTLFLAG_READWRITE, CTLTYPE_INT, "reg_access", NULL, 1563 sysctl_dbcool_reg_access, 1564 0, (void *)sc, sizeof(int), 1565 CTL_HW, me->sysctl_num, CTL_CREATE, CTL_EOL); 1566 if (node != NULL) 1567 node->sysctl_data = sc; 1568 #endif /* DBCOOL_DEBUG */ 1569 } 1570 1571 /* 1572 * Read and rewrite config register to activate device 1573 */ 1574 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 1575 cfg_reg = DBCOOL_ADM1030_CFG1; 1576 else if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) 1577 cfg_reg = DBCOOL_ADT7466_CONFIG1; 1578 else 1579 cfg_reg = DBCOOL_CONFIG1_REG; 1580 cfg_val = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_CONFIG1_REG); 1581 if ((cfg_val & DBCOOL_CFG1_START) == 0) { 1582 cfg_val |= DBCOOL_CFG1_START; 1583 sc->sc_dc.dc_writereg(&sc->sc_dc, cfg_reg, cfg_val); 1584 } 1585 if (dbcool_islocked(sc)) 1586 aprint_normal_dev(self, "configuration locked\n"); 1587 1588 sc->sc_sme->sme_name = device_xname(self); 1589 sc->sc_sme->sme_cookie = sc; 1590 sc->sc_sme->sme_refresh = dbcool_refresh; 1591 sc->sc_sme->sme_set_limits = dbcool_set_limits; 1592 sc->sc_sme->sme_get_limits = dbcool_get_limits; 1593 1594 if ((error = sysmon_envsys_register(sc->sc_sme)) != 0) { 1595 aprint_error_dev(self, 1596 "unable to register with sysmon (%d)\n", error); 1597 goto out; 1598 } 1599 1600 return; 1601 1602 out: 1603 sysmon_envsys_destroy(sc->sc_sme); 1604 } 1605 1606 static int 1607 dbcool_setup_sensors(struct dbcool_softc *sc) 1608 { 1609 int i; 1610 int error = 0; 1611 uint8_t vid_reg, vid_val; 1612 struct chip_id *chip = sc->sc_dc.dc_chip; 1613 1614 for (i=0; chip->table[i].type != DBC_EOF; i++) { 1615 if (i < DBCOOL_MAXSENSORS) 1616 sc->sc_sysctl_num[i] = -1; 1617 else if (chip->table[i].type != DBC_CTL) { 1618 aprint_normal_dev(sc->sc_dev, "chip table too big!\n"); 1619 break; 1620 } 1621 switch (chip->table[i].type) { 1622 case DBC_TEMP: 1623 sc->sc_sensor[i].units = ENVSYS_STEMP; 1624 sc->sc_sensor[i].state = ENVSYS_SINVALID; 1625 sc->sc_sensor[i].flags |= ENVSYS_FMONLIMITS; 1626 sc->sc_sensor[i].flags |= ENVSYS_FHAS_ENTROPY; 1627 error = dbcool_attach_sensor(sc, i); 1628 break; 1629 case DBC_VOLT: 1630 /* 1631 * If 12V-In pin has been reconfigured as 6th bit 1632 * of VID code, don't create a 12V-In sensor 1633 */ 1634 if ((chip->flags & DBCFLAG_HAS_VID_SEL) && 1635 (chip->table[i].reg.val_reg == DBCOOL_12VIN) && 1636 (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VID_REG) & 1637 0x80)) 1638 break; 1639 1640 sc->sc_sensor[i].units = ENVSYS_SVOLTS_DC; 1641 sc->sc_sensor[i].state = ENVSYS_SINVALID; 1642 sc->sc_sensor[i].flags |= ENVSYS_FMONLIMITS; 1643 sc->sc_sensor[i].flags |= ENVSYS_FHAS_ENTROPY; 1644 error = dbcool_attach_sensor(sc, i); 1645 break; 1646 case DBC_FAN: 1647 sc->sc_sensor[i].units = ENVSYS_SFANRPM; 1648 sc->sc_sensor[i].state = ENVSYS_SINVALID; 1649 sc->sc_sensor[i].flags |= ENVSYS_FMONLIMITS; 1650 sc->sc_sensor[i].flags |= ENVSYS_FHAS_ENTROPY; 1651 error = dbcool_attach_sensor(sc, i); 1652 break; 1653 case DBC_VID: 1654 sc->sc_sensor[i].units = ENVSYS_INTEGER; 1655 sc->sc_sensor[i].state = ENVSYS_SINVALID; 1656 sc->sc_sensor[i].flags |= ENVSYS_FMONNOTSUPP; 1657 1658 /* retrieve 5- or 6-bit value */ 1659 vid_reg = chip->table[i].reg.val_reg; 1660 vid_val = sc->sc_dc.dc_readreg(&sc->sc_dc, vid_reg); 1661 if (chip->flags & DBCFLAG_HAS_VID_SEL) 1662 vid_val &= 0x3f; 1663 else 1664 vid_val &= 0x1f; 1665 sc->sc_sensor[i].value_cur = vid_val; 1666 1667 error = dbcool_attach_sensor(sc, i); 1668 break; 1669 case DBC_CTL: 1670 error = dbcool_attach_temp_control(sc, i, chip); 1671 if (error) { 1672 aprint_error_dev(sc->sc_dev, 1673 "attach index %d failed %d\n", 1674 i, error); 1675 error = 0; 1676 } 1677 break; 1678 default: 1679 aprint_error_dev(sc->sc_dev, 1680 "sensor_table index %d has bad type %d\n", 1681 i, chip->table[i].type); 1682 break; 1683 } 1684 if (error) 1685 break; 1686 } 1687 return error; 1688 } 1689 1690 static int 1691 dbcool_attach_sensor(struct dbcool_softc *sc, int idx) 1692 { 1693 int name_index; 1694 int error = 0; 1695 1696 name_index = sc->sc_dc.dc_chip->table[idx].name_index; 1697 strlcpy(sc->sc_sensor[idx].desc, dbc_sensor_names[name_index], 1698 sizeof(sc->sc_sensor[idx].desc)); 1699 sc->sc_regs[idx] = &sc->sc_dc.dc_chip->table[idx].reg; 1700 sc->sc_nom_volt[idx] = sc->sc_dc.dc_chip->table[idx].nom_volt_index; 1701 1702 error = sysmon_envsys_sensor_attach(sc->sc_sme, &sc->sc_sensor[idx]); 1703 return error; 1704 } 1705 1706 static int 1707 dbcool_attach_temp_control(struct dbcool_softc *sc, int idx, 1708 struct chip_id *chip) 1709 { 1710 const struct sysctlnode *me2 = NULL, *node; 1711 int j, ret, sysctl_index, rw_flag; 1712 uint8_t sysctl_reg; 1713 char name[SYSCTL_NAMELEN]; 1714 1715 /* Search for the corresponding temp sensor */ 1716 for (j = 0; j < idx; j++) { 1717 if (j >= DBCOOL_MAXSENSORS || chip->table[j].type != DBC_TEMP) 1718 continue; 1719 if (chip->table[j].name_index == chip->table[idx].name_index) 1720 break; 1721 } 1722 if (j >= idx) /* Temp sensor not found */ 1723 return ENOENT; 1724 1725 /* create sysctl node for the sensor if not one already there */ 1726 if (sc->sc_sysctl_num[j] == -1) { 1727 ret = sysctl_createv(&sc->sc_sysctl_log, 0, NULL, &me2, 1728 CTLFLAG_READWRITE, 1729 CTLTYPE_NODE, sc->sc_sensor[j].desc, NULL, 1730 NULL, 0, NULL, 0, 1731 CTL_HW, sc->sc_root_sysctl_num, CTL_CREATE, 1732 CTL_EOL); 1733 if (me2 != NULL) 1734 sc->sc_sysctl_num[j] = me2->sysctl_num; 1735 else 1736 return ret; 1737 } 1738 /* add sysctl leaf node for this control variable */ 1739 sysctl_index = chip->table[idx].sysctl_index; 1740 sysctl_reg = chip->table[idx].reg.val_reg; 1741 strlcpy(name, dbc_sysctl_table[sysctl_index].name, sizeof(name)); 1742 if (dbc_sysctl_table[sysctl_index].lockable && dbcool_islocked(sc)) 1743 rw_flag = CTLFLAG_READONLY | CTLFLAG_OWNDESC; 1744 else 1745 rw_flag = CTLFLAG_READWRITE | CTLFLAG_OWNDESC; 1746 ret = sysctl_createv(&sc->sc_sysctl_log, 0, NULL, &node, rw_flag, 1747 CTLTYPE_INT, name, 1748 SYSCTL_DESCR(dbc_sysctl_table[sysctl_index].desc), 1749 dbc_sysctl_table[sysctl_index].helper, 1750 0, (void *)sc, sizeof(int), 1751 CTL_HW, sc->sc_root_sysctl_num, 1752 sc->sc_sysctl_num[j], 1753 DBC_PWM_SYSCTL(idx, sysctl_reg), CTL_EOL); 1754 1755 return ret; 1756 } 1757 1758 static void 1759 dbcool_setup_controllers(struct dbcool_softc *sc) 1760 { 1761 int i, j, rw_flag; 1762 uint8_t sysctl_reg; 1763 struct chip_id *chip = sc->sc_dc.dc_chip; 1764 const struct sysctlnode *me2 = NULL; 1765 const struct sysctlnode *node = NULL; 1766 char name[SYSCTL_NAMELEN]; 1767 1768 for (i = 0; chip->power[i].desc != NULL; i++) { 1769 snprintf(name, sizeof(name), "fan_ctl_%d", i); 1770 sysctl_createv(&sc->sc_sysctl_log, 0, NULL, &me2, 1771 CTLFLAG_READWRITE | CTLFLAG_OWNDESC, 1772 CTLTYPE_NODE, name, NULL, 1773 NULL, 0, NULL, 0, 1774 CTL_HW, sc->sc_root_sysctl_num, CTL_CREATE, CTL_EOL); 1775 1776 for (j = DBC_PWM_BEHAVIOR; j < DBC_PWM_LAST_PARAM; j++) { 1777 if (j == DBC_PWM_MAX_DUTY && 1778 (chip->flags & DBCFLAG_HAS_MAXDUTY) == 0) 1779 continue; 1780 sysctl_reg = chip->power[i].power_regs[j]; 1781 if (sysctl_reg == DBCOOL_NO_REG) 1782 continue; 1783 strlcpy(name, dbc_sysctl_table[j].name, sizeof(name)); 1784 if (dbc_sysctl_table[j].lockable && dbcool_islocked(sc)) 1785 rw_flag = CTLFLAG_READONLY | CTLFLAG_OWNDESC; 1786 else 1787 rw_flag = CTLFLAG_READWRITE | CTLFLAG_OWNDESC; 1788 (sysctl_createv)(&sc->sc_sysctl_log, 0, NULL, 1789 &node, rw_flag, 1790 (j == DBC_PWM_BEHAVIOR)? 1791 CTLTYPE_STRING:CTLTYPE_INT, 1792 name, 1793 SYSCTL_DESCR(dbc_sysctl_table[j].desc), 1794 dbc_sysctl_table[j].helper, 1795 0, sc, 1796 ( j == DBC_PWM_BEHAVIOR)? 1797 sizeof(dbcool_cur_behav): sizeof(int), 1798 CTL_HW, sc->sc_root_sysctl_num, me2->sysctl_num, 1799 DBC_PWM_SYSCTL(j, sysctl_reg), CTL_EOL); 1800 } 1801 } 1802 } 1803 1804 static void 1805 dbcool_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 1806 { 1807 struct dbcool_softc *sc=sme->sme_cookie; 1808 int i, nom_volt_idx, cur; 1809 struct reg_list *reg; 1810 1811 i = edata->sensor; 1812 reg = sc->sc_regs[i]; 1813 1814 edata->state = ENVSYS_SVALID; 1815 switch (edata->units) 1816 { 1817 case ENVSYS_STEMP: 1818 cur = dbcool_read_temp(sc, reg->val_reg, true); 1819 break; 1820 case ENVSYS_SVOLTS_DC: 1821 nom_volt_idx = sc->sc_nom_volt[i]; 1822 cur = dbcool_read_volt(sc, reg->val_reg, nom_volt_idx, 1823 true); 1824 break; 1825 case ENVSYS_SFANRPM: 1826 cur = dbcool_read_rpm(sc, reg->val_reg); 1827 break; 1828 case ENVSYS_INTEGER: 1829 return; 1830 default: 1831 edata->state = ENVSYS_SINVALID; 1832 return; 1833 } 1834 1835 if (cur == 0 && (edata->units != ENVSYS_SFANRPM)) 1836 edata->state = ENVSYS_SINVALID; 1837 1838 /* 1839 * If fan is "stalled" but has no low limit, treat 1840 * it as though the fan is not installed. 1841 */ 1842 else if (edata->units == ENVSYS_SFANRPM && cur == 0 && 1843 !(edata->upropset & (PROP_CRITMIN | PROP_WARNMIN))) 1844 edata->state = ENVSYS_SINVALID; 1845 1846 edata->value_cur = cur; 1847 } 1848 1849 int 1850 dbcool_chip_ident(struct dbcool_chipset *dc) 1851 { 1852 /* verify this is a supported dbCool chip */ 1853 uint8_t c_id, d_id, r_id; 1854 int i; 1855 1856 c_id = dc->dc_readreg(dc, DBCOOL_COMPANYID_REG); 1857 d_id = dc->dc_readreg(dc, DBCOOL_DEVICEID_REG); 1858 r_id = dc->dc_readreg(dc, DBCOOL_REVISION_REG); 1859 1860 /* The EMC6D103S only supports read_byte and since dc->dc_chip is 1861 * NULL when we call dc->dc_readreg above we use 1862 * send_byte/receive_byte which doesn't work. 1863 * 1864 * So if we only get 0's back then try again with dc->dc_chip 1865 * set to the EMC6D103S_DEVICEID and which doesn't have 1866 * DBCFLAG_NO_READBYTE set so read_byte will be used 1867 */ 1868 if ((c_id == 0) && (d_id == 0) && (r_id == 0)) { 1869 for (i = 0; chip_table[i].company != 0; i++) 1870 if ((SMSC_COMPANYID == chip_table[i].company) && 1871 (EMC6D103S_DEVICEID == chip_table[i].device)) { 1872 dc->dc_chip = &chip_table[i]; 1873 break; 1874 } 1875 c_id = dc->dc_readreg(dc, DBCOOL_COMPANYID_REG); 1876 d_id = dc->dc_readreg(dc, DBCOOL_DEVICEID_REG); 1877 r_id = dc->dc_readreg(dc, DBCOOL_REVISION_REG); 1878 } 1879 1880 for (i = 0; chip_table[i].company != 0; i++) 1881 if ((c_id == chip_table[i].company) && 1882 (d_id == chip_table[i].device || 1883 chip_table[i].device == 0xff) && 1884 (r_id == chip_table[i].rev || 1885 chip_table[i].rev == 0xff)) { 1886 dc->dc_chip = &chip_table[i]; 1887 return i; 1888 } 1889 1890 aprint_verbose("dbcool_chip_ident: addr 0x%02x c_id 0x%02x d_id 0x%02x" 1891 " r_id 0x%02x: No match.\n", dc->dc_addr, c_id, d_id, 1892 r_id); 1893 1894 return -1; 1895 } 1896 1897 /* 1898 * Retrieve sensor limits from the chip registers 1899 */ 1900 static void 1901 dbcool_get_limits(struct sysmon_envsys *sme, envsys_data_t *edata, 1902 sysmon_envsys_lim_t *limits, uint32_t *props) 1903 { 1904 int index = edata->sensor; 1905 struct dbcool_softc *sc = sme->sme_cookie; 1906 1907 *props &= ~(PROP_CRITMIN | PROP_CRITMAX); 1908 switch (edata->units) { 1909 case ENVSYS_STEMP: 1910 dbcool_get_temp_limits(sc, index, limits, props); 1911 break; 1912 case ENVSYS_SVOLTS_DC: 1913 dbcool_get_volt_limits(sc, index, limits, props); 1914 break; 1915 case ENVSYS_SFANRPM: 1916 dbcool_get_fan_limits(sc, index, limits, props); 1917 1918 /* FALLTHROUGH */ 1919 default: 1920 break; 1921 } 1922 *props &= ~PROP_DRIVER_LIMITS; 1923 1924 /* If both limits provided, make sure they're sane */ 1925 if ((*props & PROP_CRITMIN) && 1926 (*props & PROP_CRITMAX) && 1927 (limits->sel_critmin >= limits->sel_critmax)) 1928 *props &= ~(PROP_CRITMIN | PROP_CRITMAX); 1929 1930 /* 1931 * If this is the first time through, save these values 1932 * in case user overrides them and then requests a reset. 1933 */ 1934 if (sc->sc_defprops[index] == 0) { 1935 sc->sc_defprops[index] = *props | PROP_DRIVER_LIMITS; 1936 sc->sc_deflims[index] = *limits; 1937 } 1938 } 1939 1940 static void 1941 dbcool_get_temp_limits(struct dbcool_softc *sc, int idx, 1942 sysmon_envsys_lim_t *lims, uint32_t *props) 1943 { 1944 struct reg_list *reg = sc->sc_regs[idx]; 1945 uint8_t lo_lim, hi_lim; 1946 1947 lo_lim = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->lo_lim_reg); 1948 hi_lim = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->hi_lim_reg); 1949 1950 if (sc->sc_temp_offset) { 1951 if (lo_lim > 0x01) { 1952 lims->sel_critmin = lo_lim - sc->sc_temp_offset; 1953 *props |= PROP_CRITMIN; 1954 } 1955 if (hi_lim != 0xff) { 1956 lims->sel_critmax = hi_lim - sc->sc_temp_offset; 1957 *props |= PROP_CRITMAX; 1958 } 1959 } else { 1960 if (lo_lim != 0x80 && lo_lim != 0x81) { 1961 lims->sel_critmin = (int8_t)lo_lim; 1962 *props |= PROP_CRITMIN; 1963 } 1964 1965 if (hi_lim != 0x7f) { 1966 lims->sel_critmax = (int8_t)hi_lim; 1967 *props |= PROP_CRITMAX; 1968 } 1969 } 1970 1971 /* Convert temp limits to microKelvin */ 1972 lims->sel_critmin *= 1000000; 1973 lims->sel_critmin += 273150000; 1974 lims->sel_critmax *= 1000000; 1975 lims->sel_critmax += 273150000; 1976 } 1977 1978 static void 1979 dbcool_get_volt_limits(struct dbcool_softc *sc, int idx, 1980 sysmon_envsys_lim_t *lims, uint32_t *props) 1981 { 1982 struct reg_list *reg = sc->sc_regs[idx]; 1983 int64_t limit; 1984 int nom; 1985 1986 nom = nominal_voltages[sc->sc_dc.dc_chip->table[idx].nom_volt_index]; 1987 if (nom < 0) 1988 nom = dbcool_supply_voltage(sc); 1989 nom *= 1000000; /* scale for microvolts */ 1990 1991 limit = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->lo_lim_reg); 1992 if (limit != 0x00 && limit != 0xff) { 1993 limit *= nom; 1994 limit /= 0xc0; 1995 lims->sel_critmin = limit; 1996 *props |= PROP_CRITMIN; 1997 } 1998 limit = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->hi_lim_reg); 1999 if (limit != 0x00 && limit != 0xff) { 2000 limit *= nom; 2001 limit /= 0xc0; 2002 lims->sel_critmax = limit; 2003 *props |= PROP_CRITMAX; 2004 } 2005 } 2006 2007 static void 2008 dbcool_get_fan_limits(struct dbcool_softc *sc, int idx, 2009 sysmon_envsys_lim_t *lims, uint32_t *props) 2010 { 2011 struct reg_list *reg = sc->sc_regs[idx]; 2012 int32_t limit; 2013 2014 limit = dbcool_read_rpm(sc, reg->lo_lim_reg); 2015 if (limit) { 2016 lims->sel_critmin = limit; 2017 *props |= PROP_CRITMIN; 2018 } 2019 } 2020 2021 /* 2022 * Update sensor limits in the chip registers 2023 */ 2024 static void 2025 dbcool_set_limits(struct sysmon_envsys *sme, envsys_data_t *edata, 2026 sysmon_envsys_lim_t *limits, uint32_t *props) 2027 { 2028 int index = edata->sensor; 2029 struct dbcool_softc *sc = sme->sme_cookie; 2030 2031 if (limits == NULL) { 2032 limits = &sc->sc_deflims[index]; 2033 props = &sc->sc_defprops[index]; 2034 } 2035 switch (edata->units) { 2036 case ENVSYS_STEMP: 2037 dbcool_set_temp_limits(sc, index, limits, props); 2038 break; 2039 case ENVSYS_SVOLTS_DC: 2040 dbcool_set_volt_limits(sc, index, limits, props); 2041 break; 2042 case ENVSYS_SFANRPM: 2043 dbcool_set_fan_limits(sc, index, limits, props); 2044 2045 /* FALLTHROUGH */ 2046 default: 2047 break; 2048 } 2049 *props &= ~PROP_DRIVER_LIMITS; 2050 } 2051 2052 static void 2053 dbcool_set_temp_limits(struct dbcool_softc *sc, int idx, 2054 sysmon_envsys_lim_t *lims, uint32_t *props) 2055 { 2056 struct reg_list *reg = sc->sc_regs[idx]; 2057 int32_t limit; 2058 2059 if (*props & PROP_CRITMIN) { 2060 limit = lims->sel_critmin - 273150000; 2061 limit /= 1000000; 2062 if (sc->sc_temp_offset) { 2063 limit += sc->sc_temp_offset; 2064 if (limit < 0) 2065 limit = 0; 2066 else if (limit > 255) 2067 limit = 255; 2068 } else { 2069 if (limit < -127) 2070 limit = -127; 2071 else if (limit > 127) 2072 limit = 127; 2073 } 2074 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, 2075 (uint8_t)limit); 2076 } else if (*props & PROP_DRIVER_LIMITS) { 2077 if (sc->sc_temp_offset) 2078 limit = 0x00; 2079 else 2080 limit = 0x80; 2081 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, 2082 (uint8_t)limit); 2083 } 2084 2085 if (*props & PROP_CRITMAX) { 2086 limit = lims->sel_critmax - 273150000; 2087 limit /= 1000000; 2088 if (sc->sc_temp_offset) { 2089 limit += sc->sc_temp_offset; 2090 if (limit < 0) 2091 limit = 0; 2092 else if (limit > 255) 2093 limit = 255; 2094 } else { 2095 if (limit < -127) 2096 limit = -127; 2097 else if (limit > 127) 2098 limit = 127; 2099 } 2100 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg, 2101 (uint8_t)limit); 2102 } else if (*props & PROP_DRIVER_LIMITS) { 2103 if (sc->sc_temp_offset) 2104 limit = 0xff; 2105 else 2106 limit = 0x7f; 2107 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg, 2108 (uint8_t)limit); 2109 } 2110 } 2111 2112 static void 2113 dbcool_set_volt_limits(struct dbcool_softc *sc, int idx, 2114 sysmon_envsys_lim_t *lims, uint32_t *props) 2115 { 2116 struct reg_list *reg = sc->sc_regs[idx]; 2117 int64_t limit; 2118 int nom; 2119 2120 nom = nominal_voltages[sc->sc_dc.dc_chip->table[idx].nom_volt_index]; 2121 if (nom < 0) 2122 nom = dbcool_supply_voltage(sc); 2123 nom *= 1000000; /* scale for microvolts */ 2124 2125 if (*props & PROP_CRITMIN) { 2126 limit = lims->sel_critmin; 2127 limit *= 0xc0; 2128 limit /= nom; 2129 if (limit > 0xff) 2130 limit = 0xff; 2131 else if (limit < 0) 2132 limit = 0; 2133 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, limit); 2134 } else if (*props & PROP_DRIVER_LIMITS) 2135 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, 0); 2136 2137 if (*props & PROP_CRITMAX) { 2138 limit = lims->sel_critmax; 2139 limit *= 0xc0; 2140 limit /= nom; 2141 if (limit > 0xff) 2142 limit = 0xff; 2143 else if (limit < 0) 2144 limit = 0; 2145 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg, limit); 2146 } else if (*props & PROP_DRIVER_LIMITS) 2147 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg, 0xff); 2148 } 2149 2150 static void 2151 dbcool_set_fan_limits(struct dbcool_softc *sc, int idx, 2152 sysmon_envsys_lim_t *lims, uint32_t *props) 2153 { 2154 struct reg_list *reg = sc->sc_regs[idx]; 2155 int32_t limit, dividend; 2156 2157 if (*props & PROP_CRITMIN) { 2158 limit = lims->sel_critmin; 2159 if (limit == 0) 2160 limit = 0xffff; 2161 else { 2162 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 2163 dividend = 11250 * 60; 2164 else 2165 dividend = 90000 * 60; 2166 limit = limit / dividend; 2167 if (limit > 0xffff) 2168 limit = 0xffff; 2169 } 2170 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, 2171 limit & 0xff); 2172 limit >>= 8; 2173 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg + 1, 2174 limit & 0xff); 2175 } else if (*props & PROP_DRIVER_LIMITS) { 2176 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, 0xff); 2177 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg + 1, 0xff); 2178 } 2179 } 2180 2181 MODULE(MODULE_CLASS_DRIVER, dbcool, "i2cexec,sysmon_envsys"); 2182 2183 #ifdef _MODULE 2184 #include "ioconf.c" 2185 #endif 2186 2187 static int 2188 dbcool_modcmd(modcmd_t cmd, void *opaque) 2189 { 2190 int error = 0; 2191 #ifdef _MODULE 2192 static struct sysctllog *dbcool_sysctl_clog; 2193 #endif 2194 2195 switch (cmd) { 2196 case MODULE_CMD_INIT: 2197 #ifdef _MODULE 2198 error = config_init_component(cfdriver_ioconf_dbcool, 2199 cfattach_ioconf_dbcool, cfdata_ioconf_dbcool); 2200 sysctl_dbcoolsetup(&dbcool_sysctl_clog); 2201 #endif 2202 return error; 2203 case MODULE_CMD_FINI: 2204 #ifdef _MODULE 2205 error = config_fini_component(cfdriver_ioconf_dbcool, 2206 cfattach_ioconf_dbcool, cfdata_ioconf_dbcool); 2207 sysctl_teardown(&dbcool_sysctl_clog); 2208 #endif 2209 return error; 2210 default: 2211 return ENOTTY; 2212 } 2213 } 2214
Indexes created Tue Sep 23 22:09:46 GMT 2025