dbcool.c revision 1.60
1 /* $NetBSD: dbcool.c,v 1.60 2021/01/30 01:22:06 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Goyette 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * a driver for the dbCool(tm) family of environmental controllers 34 * 35 * Data sheets for the various supported chips are available at 36 * 37 * http://www.onsemi.com/pub/Collateral/ADM1027-D.PDF 38 * http://www.onsemi.com/pub/Collateral/ADM1030-D.PDF 39 * http://www.onsemi.com/pub/Collateral/ADT7463-D.PDF 40 * http://www.onsemi.com/pub/Collateral/ADT7466.PDF 41 * http://www.onsemi.com/pub/Collateral/ADT7467-D.PDF 42 * http://www.onsemi.com/pub/Collateral/ADT7468-D.PDF 43 * http://www.onsemi.com/pub/Collateral/ADT7473-D.PDF 44 * http://www.onsemi.com/pub/Collateral/ADT7475-D.PDF 45 * http://www.onsemi.com/pub/Collateral/ADT7476-D.PDF 46 * http://www.onsemi.com/pub/Collateral/ADT7490-D.PDF 47 * http://www.smsc.com/media/Downloads_Public/Data_Sheets/6d103s.pdf 48 * 49 * (URLs are correct as of October 5, 2008) 50 */ 51 52 #include <sys/cdefs.h> 53 __KERNEL_RCSID(0, "$NetBSD: dbcool.c,v 1.60 2021/01/30 01:22:06 thorpej Exp $"); 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/kernel.h> 58 #include <sys/device.h> 59 #include <sys/malloc.h> 60 #include <sys/sysctl.h> 61 #include <sys/module.h> 62 63 #include <dev/i2c/dbcool_var.h> 64 #include <dev/i2c/dbcool_reg.h> 65 66 /* Config interface */ 67 static int dbcool_match(device_t, cfdata_t, void *); 68 static void dbcool_attach(device_t, device_t, void *); 69 static int dbcool_detach(device_t, int); 70 71 /* Device attributes */ 72 static int dbcool_supply_voltage(struct dbcool_softc *); 73 static bool dbcool_islocked(struct dbcool_softc *); 74 75 /* Sensor read functions */ 76 static void dbcool_refresh(struct sysmon_envsys *, envsys_data_t *); 77 static int dbcool_read_rpm(struct dbcool_softc *, uint8_t); 78 static int dbcool_read_temp(struct dbcool_softc *, uint8_t, bool); 79 static int dbcool_read_volt(struct dbcool_softc *, uint8_t, int, bool); 80 81 /* Sensor get/set limit functions */ 82 static void dbcool_get_limits(struct sysmon_envsys *, envsys_data_t *, 83 sysmon_envsys_lim_t *, uint32_t *); 84 static void dbcool_get_temp_limits(struct dbcool_softc *, int, 85 sysmon_envsys_lim_t *, uint32_t *); 86 static void dbcool_get_volt_limits(struct dbcool_softc *, int, 87 sysmon_envsys_lim_t *, uint32_t *); 88 static void dbcool_get_fan_limits(struct dbcool_softc *, int, 89 sysmon_envsys_lim_t *, uint32_t *); 90 91 static void dbcool_set_limits(struct sysmon_envsys *, envsys_data_t *, 92 sysmon_envsys_lim_t *, uint32_t *); 93 static void dbcool_set_temp_limits(struct dbcool_softc *, int, 94 sysmon_envsys_lim_t *, uint32_t *); 95 static void dbcool_set_volt_limits(struct dbcool_softc *, int, 96 sysmon_envsys_lim_t *, uint32_t *); 97 static void dbcool_set_fan_limits(struct dbcool_softc *, int, 98 sysmon_envsys_lim_t *, uint32_t *); 99 100 /* SYSCTL Helpers */ 101 SYSCTL_SETUP_PROTO(sysctl_dbcoolsetup); 102 static int sysctl_dbcool_temp(SYSCTLFN_PROTO); 103 static int sysctl_adm1030_temp(SYSCTLFN_PROTO); 104 static int sysctl_adm1030_trange(SYSCTLFN_PROTO); 105 static int sysctl_dbcool_duty(SYSCTLFN_PROTO); 106 static int sysctl_dbcool_behavior(SYSCTLFN_PROTO); 107 static int sysctl_dbcool_slope(SYSCTLFN_PROTO); 108 static int sysctl_dbcool_thyst(SYSCTLFN_PROTO); 109 110 /* Set-up subroutines */ 111 static void dbcool_setup_controllers(struct dbcool_softc *); 112 static int dbcool_setup_sensors(struct dbcool_softc *); 113 static int dbcool_attach_sensor(struct dbcool_softc *, int); 114 static int dbcool_attach_temp_control(struct dbcool_softc *, int, 115 struct chip_id *); 116 117 #ifdef DBCOOL_DEBUG 118 static int sysctl_dbcool_reg_select(SYSCTLFN_PROTO); 119 static int sysctl_dbcool_reg_access(SYSCTLFN_PROTO); 120 #endif /* DBCOOL_DEBUG */ 121 122 /* 123 * Descriptions for SYSCTL entries 124 */ 125 struct dbc_sysctl_info { 126 const char *name; 127 const char *desc; 128 bool lockable; 129 int (*helper)(SYSCTLFN_PROTO); 130 }; 131 132 static struct dbc_sysctl_info dbc_sysctl_table[] = { 133 /* 134 * The first several entries must remain in the same order as the 135 * corresponding entries in enum dbc_pwm_params 136 */ 137 { "behavior", "operating behavior and temp selector", 138 true, sysctl_dbcool_behavior }, 139 { "min_duty", "minimum fan controller PWM duty cycle", 140 true, sysctl_dbcool_duty }, 141 { "max_duty", "maximum fan controller PWM duty cycle", 142 true, sysctl_dbcool_duty }, 143 { "cur_duty", "current fan controller PWM duty cycle", 144 false, sysctl_dbcool_duty }, 145 146 /* 147 * The rest of these should be in the order in which they 148 * are to be stored in the sysctl tree; the table index is 149 * used as the high-order bits of the sysctl_num to maintain 150 * the sequence. 151 * 152 * If you rearrange the order of these items, be sure to 153 * update the sysctl_index in the XXX_sensor_table[] for 154 * the various chips! 155 */ 156 { "Trange", "temp slope/range to reach 100% duty cycle", 157 true, sysctl_dbcool_slope }, 158 { "Tmin", "temp at which to start fan controller", 159 true, sysctl_dbcool_temp }, 160 { "Ttherm", "temp at which THERM is asserted", 161 true, sysctl_dbcool_temp }, 162 { "Thyst", "temp hysteresis for stopping fan controller", 163 true, sysctl_dbcool_thyst }, 164 { "Tmin", "temp at which to start fan controller", 165 true, sysctl_adm1030_temp }, 166 { "Trange", "temp slope/range to reach 100% duty cycle", 167 true, sysctl_adm1030_trange }, 168 }; 169 170 static const char *dbc_sensor_names[] = { 171 "l_temp", "r1_temp", "r2_temp", "Vccp", "Vcc", "fan1", 172 "fan2", "fan3", "fan4", "AIN1", "AIN2", "V2dot5", 173 "V5", "V12", "Vtt", "Imon", "VID" 174 }; 175 176 /* 177 * Following table derived from product data-sheets 178 */ 179 static int64_t nominal_voltages[] = { 180 -1, /* Vcc can be either 3.3 or 5.0V 181 at 3/4 scale */ 182 2249939, /* Vccp 2.25V 3/4 scale */ 183 2497436, /* 2.5VIN 2.5V 3/4 scale */ 184 5002466, /* 5VIN 5V 3/4 scale */ 185 12000000, /* 12VIN 12V 3/4 scale */ 186 1690809, /* Vtt, Imon 2.25V full scale */ 187 1689600, /* AIN1, AIN2 2.25V full scale */ 188 0 189 }; 190 191 /* 192 * Sensor-type, { val-reg, hilim-reg, lolim-reg}, name-idx, sysctl-table-idx, 193 * nom-voltage-index 194 */ 195 struct dbcool_sensor ADT7490_sensor_table[] = { 196 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 197 DBCOOL_LOCAL_HIGHLIM, 198 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 199 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 200 DBCOOL_REMOTE1_HIGHLIM, 201 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 202 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 203 DBCOOL_REMOTE2_HIGHLIM, 204 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 205 { DBC_VOLT, { DBCOOL_VCCP, 206 DBCOOL_VCCP_HIGHLIM, 207 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 208 { DBC_VOLT, { DBCOOL_VCC, 209 DBCOOL_VCC_HIGHLIM, 210 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 211 { DBC_VOLT, { DBCOOL_25VIN, 212 DBCOOL_25VIN_HIGHLIM, 213 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 }, 214 { DBC_VOLT, { DBCOOL_5VIN, 215 DBCOOL_5VIN_HIGHLIM, 216 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 }, 217 { DBC_VOLT, { DBCOOL_12VIN, 218 DBCOOL_12VIN_HIGHLIM, 219 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 }, 220 { DBC_VOLT, { DBCOOL_VTT, 221 DBCOOL_VTT_HIGHLIM, 222 DBCOOL_VTT_LOWLIM }, 14, 0, 5 }, 223 { DBC_VOLT, { DBCOOL_IMON, 224 DBCOOL_IMON_HIGHLIM, 225 DBCOOL_IMON_LOWLIM }, 15, 0, 5 }, 226 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 227 DBCOOL_NO_REG, 228 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 229 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 230 DBCOOL_NO_REG, 231 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 232 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 233 DBCOOL_NO_REG, 234 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 235 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 236 DBCOOL_NO_REG, 237 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 238 { DBC_VID, { DBCOOL_VID_REG, 239 DBCOOL_NO_REG, 240 DBCOOL_NO_REG }, 16, 0, 0 }, 241 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 242 DBCOOL_NO_REG, 243 DBCOOL_NO_REG }, 0, 5, 0 }, 244 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 245 DBCOOL_NO_REG, 246 DBCOOL_NO_REG }, 0, 6, 0 }, 247 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 248 DBCOOL_NO_REG, 249 DBCOOL_NO_REG }, 0, 7, 0 }, 250 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 251 DBCOOL_NO_REG, 252 DBCOOL_NO_REG }, 1, 5, 0 }, 253 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 254 DBCOOL_NO_REG, 255 DBCOOL_NO_REG }, 1, 6, 0 }, 256 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 257 DBCOOL_NO_REG, 258 DBCOOL_NO_REG }, 1, 7, 0 }, 259 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 260 DBCOOL_NO_REG, 261 DBCOOL_NO_REG }, 2, 5, 0 }, 262 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 263 DBCOOL_NO_REG, 264 DBCOOL_NO_REG }, 2, 6, 0 }, 265 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 266 DBCOOL_NO_REG, 267 DBCOOL_NO_REG }, 2, 7, 0 }, 268 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 269 }; 270 271 struct dbcool_sensor ADT7476_sensor_table[] = { 272 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 273 DBCOOL_LOCAL_HIGHLIM, 274 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 275 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 276 DBCOOL_REMOTE1_HIGHLIM, 277 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 278 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 279 DBCOOL_REMOTE2_HIGHLIM, 280 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 281 { DBC_VOLT, { DBCOOL_VCCP, 282 DBCOOL_VCCP_HIGHLIM, 283 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 284 { DBC_VOLT, { DBCOOL_VCC, 285 DBCOOL_VCC_HIGHLIM, 286 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 287 { DBC_VOLT, { DBCOOL_25VIN, 288 DBCOOL_25VIN_HIGHLIM, 289 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 }, 290 { DBC_VOLT, { DBCOOL_5VIN, 291 DBCOOL_5VIN_HIGHLIM, 292 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 }, 293 { DBC_VOLT, { DBCOOL_12VIN, 294 DBCOOL_12VIN_HIGHLIM, 295 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 }, 296 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 297 DBCOOL_NO_REG, 298 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 299 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 300 DBCOOL_NO_REG, 301 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 302 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 303 DBCOOL_NO_REG, 304 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 305 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 306 DBCOOL_NO_REG, 307 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 308 { DBC_VID, { DBCOOL_VID_REG, 309 DBCOOL_NO_REG, 310 DBCOOL_NO_REG }, 16, 0, 0 }, 311 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 312 DBCOOL_NO_REG, 313 DBCOOL_NO_REG }, 0, 5, 0 }, 314 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 315 DBCOOL_NO_REG, 316 DBCOOL_NO_REG }, 0, 6, 0 }, 317 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 318 DBCOOL_NO_REG, 319 DBCOOL_NO_REG }, 0, 7, 0 }, 320 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 321 DBCOOL_NO_REG, 322 DBCOOL_NO_REG }, 1, 5, 0 }, 323 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 324 DBCOOL_NO_REG, 325 DBCOOL_NO_REG }, 1, 6, 0 }, 326 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 327 DBCOOL_NO_REG, 328 DBCOOL_NO_REG }, 1, 7, 0 }, 329 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 330 DBCOOL_NO_REG, 331 DBCOOL_NO_REG }, 2, 5, 0 }, 332 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 333 DBCOOL_NO_REG, 334 DBCOOL_NO_REG }, 2, 6, 0 }, 335 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 336 DBCOOL_NO_REG, 337 DBCOOL_NO_REG }, 2, 7, 0 }, 338 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 339 }; 340 341 struct dbcool_sensor ADT7475_sensor_table[] = { 342 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 343 DBCOOL_LOCAL_HIGHLIM, 344 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 345 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 346 DBCOOL_REMOTE1_HIGHLIM, 347 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 348 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 349 DBCOOL_REMOTE2_HIGHLIM, 350 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 351 { DBC_VOLT, { DBCOOL_VCCP, 352 DBCOOL_VCCP_HIGHLIM, 353 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 354 { DBC_VOLT, { DBCOOL_VCC, 355 DBCOOL_VCC_HIGHLIM, 356 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 357 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 358 DBCOOL_NO_REG, 359 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 360 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 361 DBCOOL_NO_REG, 362 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 363 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 364 DBCOOL_NO_REG, 365 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 366 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 367 DBCOOL_NO_REG, 368 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 369 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 370 DBCOOL_NO_REG, 371 DBCOOL_NO_REG }, 0, 5, 0 }, 372 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 373 DBCOOL_NO_REG, 374 DBCOOL_NO_REG }, 0, 6, 0 }, 375 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 376 DBCOOL_NO_REG, 377 DBCOOL_NO_REG }, 0, 7, 0 }, 378 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 379 DBCOOL_NO_REG, 380 DBCOOL_NO_REG }, 1, 5, 0 }, 381 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 382 DBCOOL_NO_REG, 383 DBCOOL_NO_REG }, 1, 6, 0 }, 384 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 385 DBCOOL_NO_REG, 386 DBCOOL_NO_REG }, 1, 7, 0 }, 387 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 388 DBCOOL_NO_REG, 389 DBCOOL_NO_REG }, 2, 5, 0 }, 390 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 391 DBCOOL_NO_REG, 392 DBCOOL_NO_REG }, 2, 6, 0 }, 393 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 394 DBCOOL_NO_REG, 395 DBCOOL_NO_REG }, 2, 7, 0 }, 396 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 397 }; 398 399 /* 400 * The registers of dbcool_power_control must be in the same order as 401 * in enum dbc_pwm_params 402 */ 403 struct dbcool_power_control ADT7475_power_table[] = { 404 { { DBCOOL_PWM1_CTL, DBCOOL_PWM1_MINDUTY, 405 DBCOOL_PWM1_MAXDUTY, DBCOOL_PWM1_CURDUTY }, 406 "fan_control_1" }, 407 { { DBCOOL_PWM2_CTL, DBCOOL_PWM2_MINDUTY, 408 DBCOOL_PWM2_MAXDUTY, DBCOOL_PWM2_CURDUTY }, 409 "fan_control_2" }, 410 { { DBCOOL_PWM3_CTL, DBCOOL_PWM3_MINDUTY, 411 DBCOOL_PWM3_MAXDUTY, DBCOOL_PWM3_CURDUTY }, 412 "fan_control_3" }, 413 { { 0, 0, 0, 0 }, NULL } 414 }; 415 416 struct dbcool_sensor ADT7466_sensor_table[] = { 417 { DBC_TEMP, { DBCOOL_ADT7466_LCL_TEMP_MSB, 418 DBCOOL_ADT7466_LCL_TEMP_HILIM, 419 DBCOOL_ADT7466_LCL_TEMP_LOLIM }, 0, 0, 0 }, 420 { DBC_TEMP, { DBCOOL_ADT7466_REM_TEMP_MSB, 421 DBCOOL_ADT7466_REM_TEMP_HILIM, 422 DBCOOL_ADT7466_REM_TEMP_LOLIM }, 1, 0, 0 }, 423 { DBC_VOLT, { DBCOOL_ADT7466_VCC, 424 DBCOOL_ADT7466_VCC_HILIM, 425 DBCOOL_ADT7466_VCC_LOLIM }, 4, 0, 0 }, 426 { DBC_VOLT, { DBCOOL_ADT7466_AIN1, 427 DBCOOL_ADT7466_AIN1_HILIM, 428 DBCOOL_ADT7466_AIN1_LOLIM }, 9, 0, 6 }, 429 { DBC_VOLT, { DBCOOL_ADT7466_AIN2, 430 DBCOOL_ADT7466_AIN2_HILIM, 431 DBCOOL_ADT7466_AIN2_LOLIM }, 10, 0, 6 }, 432 { DBC_FAN, { DBCOOL_ADT7466_FANA_LSB, 433 DBCOOL_NO_REG, 434 DBCOOL_ADT7466_FANA_LOLIM_LSB }, 5, 0, 0 }, 435 { DBC_FAN, { DBCOOL_ADT7466_FANB_LSB, 436 DBCOOL_NO_REG, 437 DBCOOL_ADT7466_FANB_LOLIM_LSB }, 6, 0, 0 }, 438 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 439 }; 440 441 struct dbcool_sensor ADM1027_sensor_table[] = { 442 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 443 DBCOOL_LOCAL_HIGHLIM, 444 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 445 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 446 DBCOOL_REMOTE1_HIGHLIM, 447 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 448 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 449 DBCOOL_REMOTE2_HIGHLIM, 450 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 451 { DBC_VOLT, { DBCOOL_VCCP, 452 DBCOOL_VCCP_HIGHLIM, 453 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 454 { DBC_VOLT, { DBCOOL_VCC, 455 DBCOOL_VCC_HIGHLIM, 456 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 457 { DBC_VOLT, { DBCOOL_25VIN, 458 DBCOOL_25VIN_HIGHLIM, 459 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 }, 460 { DBC_VOLT, { DBCOOL_5VIN, 461 DBCOOL_5VIN_HIGHLIM, 462 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 }, 463 { DBC_VOLT, { DBCOOL_12VIN, 464 DBCOOL_12VIN_HIGHLIM, 465 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 }, 466 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 467 DBCOOL_NO_REG, 468 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 469 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 470 DBCOOL_NO_REG, 471 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 472 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 473 DBCOOL_NO_REG, 474 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 475 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 476 DBCOOL_NO_REG, 477 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 478 { DBC_VID, { DBCOOL_VID_REG, 479 DBCOOL_NO_REG, 480 DBCOOL_NO_REG }, 16, 0, 0 }, 481 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 482 DBCOOL_NO_REG, 483 DBCOOL_NO_REG }, 0, 5, 0 }, 484 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 485 DBCOOL_NO_REG, 486 DBCOOL_NO_REG }, 0, 6, 0 }, 487 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 488 DBCOOL_NO_REG, 489 DBCOOL_NO_REG }, 0, 7, 0 }, 490 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 491 DBCOOL_NO_REG, 492 DBCOOL_NO_REG }, 1, 5, 0 }, 493 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 494 DBCOOL_NO_REG, 495 DBCOOL_NO_REG }, 1, 6, 0 }, 496 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 497 DBCOOL_NO_REG, 498 DBCOOL_NO_REG }, 1, 7, 0 }, 499 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 500 DBCOOL_NO_REG, 501 DBCOOL_NO_REG }, 2, 5, 0 }, 502 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 503 DBCOOL_NO_REG, 504 DBCOOL_NO_REG }, 2, 6, 0 }, 505 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 506 DBCOOL_NO_REG, 507 DBCOOL_NO_REG }, 2, 7, 0 }, 508 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 509 }; 510 511 struct dbcool_sensor ADM1030_sensor_table[] = { 512 { DBC_TEMP, { DBCOOL_ADM1030_L_TEMP, 513 DBCOOL_ADM1030_L_HI_LIM, 514 DBCOOL_ADM1030_L_LO_LIM }, 0, 0, 0 }, 515 { DBC_TEMP, { DBCOOL_ADM1030_R_TEMP, 516 DBCOOL_ADM1030_R_HI_LIM, 517 DBCOOL_ADM1030_R_LO_LIM }, 1, 0, 0 }, 518 { DBC_FAN, { DBCOOL_ADM1030_FAN_TACH, 519 DBCOOL_NO_REG, 520 DBCOOL_ADM1030_FAN_LO_LIM }, 5, 0, 0 }, 521 { DBC_CTL, { DBCOOL_ADM1030_L_TMIN, 522 DBCOOL_NO_REG, 523 DBCOOL_NO_REG }, 0, 8, 0 }, 524 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH, 525 DBCOOL_NO_REG, 526 DBCOOL_NO_REG }, 0, 9, 0 }, 527 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH, 528 DBCOOL_NO_REG, 529 DBCOOL_NO_REG }, 0, 6, 0 }, 530 { DBC_CTL, { DBCOOL_ADM1030_R_TMIN, 531 DBCOOL_NO_REG, 532 DBCOOL_NO_REG }, 1, 8, 0 }, 533 { DBC_CTL, { DBCOOL_ADM1030_R_TTHRESH, 534 DBCOOL_NO_REG, 535 DBCOOL_NO_REG }, 1, 9, 0 }, 536 { DBC_CTL, { DBCOOL_ADM1030_R_TTHRESH, 537 DBCOOL_NO_REG, 538 DBCOOL_NO_REG }, 1, 6, 0 }, 539 { DBC_EOF, {0, 0, 0 }, 0, 0, 0 } 540 }; 541 542 struct dbcool_power_control ADM1030_power_table[] = { 543 { { DBCOOL_ADM1030_CFG1, DBCOOL_NO_REG, DBCOOL_NO_REG, 544 DBCOOL_ADM1030_FAN_SPEED_CFG }, 545 "fan_control_1" }, 546 { { 0, 0, 0, 0 }, NULL } 547 }; 548 549 struct dbcool_sensor ADM1031_sensor_table[] = { 550 { DBC_TEMP, { DBCOOL_ADM1030_L_TEMP, 551 DBCOOL_ADM1030_L_HI_LIM, 552 DBCOOL_ADM1030_L_LO_LIM }, 0, 0, 0 }, 553 { DBC_TEMP, { DBCOOL_ADM1030_R_TEMP, 554 DBCOOL_ADM1030_R_HI_LIM, 555 DBCOOL_ADM1030_R_LO_LIM }, 1, 0, 0 }, 556 { DBC_TEMP, { DBCOOL_ADM1031_R2_TEMP, 557 DBCOOL_ADM1031_R2_HI_LIM, 558 DBCOOL_ADM1031_R2_LO_LIM }, 2, 0, 0 }, 559 { DBC_FAN, { DBCOOL_ADM1030_FAN_TACH, 560 DBCOOL_NO_REG, 561 DBCOOL_ADM1030_FAN_LO_LIM }, 5, 0, 0 }, 562 { DBC_FAN, { DBCOOL_ADM1031_FAN2_TACH, 563 DBCOOL_NO_REG, 564 DBCOOL_ADM1031_FAN2_LO_LIM }, 6, 0, 0 }, 565 { DBC_CTL, { DBCOOL_ADM1030_L_TMIN, 566 DBCOOL_NO_REG, 567 DBCOOL_NO_REG }, 0, 8, 0 }, 568 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH, 569 DBCOOL_NO_REG, 570 DBCOOL_NO_REG }, 0, 9, 0 }, 571 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH, 572 DBCOOL_NO_REG, 573 DBCOOL_NO_REG }, 0, 6, 0 }, 574 { DBC_CTL, { DBCOOL_ADM1030_R_TMIN, 575 DBCOOL_NO_REG, 576 DBCOOL_NO_REG }, 1, 8, 0 }, 577 { DBC_CTL, { DBCOOL_ADM1030_R_TTHRESH, 578 DBCOOL_NO_REG, 579 DBCOOL_NO_REG }, 1, 9, 0 }, 580 { DBC_CTL, { DBCOOL_ADM1030_R_TTHRESH, 581 DBCOOL_NO_REG, 582 DBCOOL_NO_REG }, 1, 6, 0 }, 583 { DBC_CTL, { DBCOOL_ADM1031_R2_TMIN, 584 DBCOOL_NO_REG, 585 DBCOOL_NO_REG }, 2, 8, 0 }, 586 { DBC_CTL, { DBCOOL_ADM1031_R2_TTHRESH, 587 DBCOOL_NO_REG, 588 DBCOOL_NO_REG }, 2, 9, 0 }, 589 { DBC_CTL, { DBCOOL_ADM1031_R2_TTHRESH, 590 DBCOOL_NO_REG, 591 DBCOOL_NO_REG }, 2, 6, 0 }, 592 { DBC_EOF, {0, 0, 0 }, 0, 0, 0 } 593 }; 594 595 struct dbcool_power_control ADM1031_power_table[] = { 596 { { DBCOOL_ADM1030_CFG1, DBCOOL_NO_REG, DBCOOL_NO_REG, 597 DBCOOL_ADM1030_FAN_SPEED_CFG }, 598 "fan_control_1" }, 599 { { DBCOOL_ADM1030_CFG1, DBCOOL_NO_REG, DBCOOL_NO_REG, 600 DBCOOL_ADM1030_FAN_SPEED_CFG }, 601 "fan_control_2" }, 602 { { 0, 0, 0, 0 }, NULL } 603 }; 604 605 struct dbcool_sensor EMC6D103S_sensor_table[] = { 606 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 607 DBCOOL_LOCAL_HIGHLIM, 608 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 609 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 610 DBCOOL_REMOTE1_HIGHLIM, 611 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 612 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 613 DBCOOL_REMOTE2_HIGHLIM, 614 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 615 { DBC_VOLT, { DBCOOL_VCCP, 616 DBCOOL_VCCP_HIGHLIM, 617 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 618 { DBC_VOLT, { DBCOOL_VCC, 619 DBCOOL_VCC_HIGHLIM, 620 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 621 { DBC_VOLT, { DBCOOL_25VIN, 622 DBCOOL_25VIN_HIGHLIM, 623 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 }, 624 { DBC_VOLT, { DBCOOL_5VIN, 625 DBCOOL_5VIN_HIGHLIM, 626 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 }, 627 { DBC_VOLT, { DBCOOL_12VIN, 628 DBCOOL_12VIN_HIGHLIM, 629 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 }, 630 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 631 DBCOOL_NO_REG, 632 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 633 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 634 DBCOOL_NO_REG, 635 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 636 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 637 DBCOOL_NO_REG, 638 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 639 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 640 DBCOOL_NO_REG, 641 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 642 { DBC_VID, { DBCOOL_VID_REG, 643 DBCOOL_NO_REG, 644 DBCOOL_NO_REG }, 16, 0, 0 }, 645 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 646 DBCOOL_NO_REG, 647 DBCOOL_NO_REG }, 0, 5, 0 }, 648 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 649 DBCOOL_NO_REG, 650 DBCOOL_NO_REG }, 0, 6, 0 }, 651 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 652 DBCOOL_NO_REG, 653 DBCOOL_NO_REG }, 1, 5, 0 }, 654 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 655 DBCOOL_NO_REG, 656 DBCOOL_NO_REG }, 1, 6, 0 }, 657 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 658 DBCOOL_NO_REG, 659 DBCOOL_NO_REG }, 2, 5, 0 }, 660 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 661 DBCOOL_NO_REG, 662 DBCOOL_NO_REG }, 2, 6, 0 }, 663 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 664 }; 665 666 struct chip_id chip_table[] = { 667 { DBCOOL_COMPANYID, ADT7490_DEVICEID, ADT7490_REV_ID, 668 ADT7490_sensor_table, ADT7475_power_table, 669 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_PECI, 670 90000 * 60, "ADT7490" }, 671 { DBCOOL_COMPANYID, ADT7476_DEVICEID, 0xff, 672 ADT7476_sensor_table, ADT7475_power_table, 673 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY, 674 90000 * 60, "ADT7476" }, 675 { DBCOOL_COMPANYID, ADT7475_DEVICEID, 0xff, 676 ADT7475_sensor_table, ADT7475_power_table, 677 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_SHDN, 678 90000 * 60, "ADT7475" }, 679 { DBCOOL_COMPANYID, ADT7473_DEVICEID, ADT7473_REV_ID1, 680 ADT7475_sensor_table, ADT7475_power_table, 681 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_SHDN, 682 90000 * 60, "ADT7460/ADT7463" }, 683 { DBCOOL_COMPANYID, ADT7473_DEVICEID, ADT7473_REV_ID2, 684 ADT7475_sensor_table, ADT7475_power_table, 685 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_SHDN, 686 90000 * 60, "ADT7463-1" }, 687 { DBCOOL_COMPANYID, ADT7468_DEVICEID, 0xff, 688 ADT7476_sensor_table, ADT7475_power_table, 689 DBCFLAG_TEMPOFFSET | DBCFLAG_MULTI_VCC | DBCFLAG_HAS_MAXDUTY | 690 DBCFLAG_4BIT_VER | DBCFLAG_HAS_SHDN, 691 90000 * 60, "ADT7467/ADT7468" }, 692 { DBCOOL_COMPANYID, ADT7466_DEVICEID, 0xff, 693 ADT7466_sensor_table, NULL, 694 DBCFLAG_ADT7466 | DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_SHDN, 695 82000 * 60, "ADT7466" }, 696 { DBCOOL_COMPANYID, ADT7463_DEVICEID, ADT7463_REV_ID1, 697 ADM1027_sensor_table, ADT7475_power_table, 698 DBCFLAG_MULTI_VCC | DBCFLAG_4BIT_VER | DBCFLAG_HAS_SHDN, 699 90000 * 60, "ADT7463" }, 700 { DBCOOL_COMPANYID, ADT7463_DEVICEID, ADT7463_REV_ID2, 701 ADM1027_sensor_table, ADT7475_power_table, 702 DBCFLAG_MULTI_VCC | DBCFLAG_4BIT_VER | DBCFLAG_HAS_SHDN | 703 DBCFLAG_HAS_VID_SEL, 704 90000 * 60, "ADT7463" }, 705 { DBCOOL_COMPANYID, ADM1027_DEVICEID, ADM1027_REV_ID, 706 ADM1027_sensor_table, ADT7475_power_table, 707 DBCFLAG_MULTI_VCC | DBCFLAG_4BIT_VER, 708 90000 * 60, "ADM1027" }, 709 { DBCOOL_COMPANYID, ADM1030_DEVICEID, 0xff, 710 ADM1030_sensor_table, ADM1030_power_table, 711 DBCFLAG_ADM1030 | DBCFLAG_NO_READBYTE, 712 11250 * 60, "ADM1030" }, 713 { DBCOOL_COMPANYID, ADM1031_DEVICEID, 0xff, 714 ADM1031_sensor_table, ADM1030_power_table, 715 DBCFLAG_ADM1030 | DBCFLAG_NO_READBYTE, 716 11250 * 60, "ADM1031" }, 717 { SMSC_COMPANYID, EMC6D103S_DEVICEID, EMC6D103S_REV_ID, 718 EMC6D103S_sensor_table, ADT7475_power_table, 719 DBCFLAG_4BIT_VER, 720 90000 * 60, "EMC6D103S" }, 721 { 0, 0, 0, NULL, NULL, 0, 0, NULL } 722 }; 723 724 static const char *behavior[] = { 725 "remote1", "local", "remote2", "full-speed", 726 "disabled", "local+remote2","all-temps", "manual" 727 }; 728 729 static char dbcool_cur_behav[16]; 730 731 CFATTACH_DECL_NEW(dbcool, sizeof(struct dbcool_softc), 732 dbcool_match, dbcool_attach, dbcool_detach, NULL); 733 734 static const struct device_compatible_entry compat_data[] = { 735 { .compat = "i2c-adm1031" }, 736 { .compat = "adt7467" }, 737 { .compat = "adt7460" }, 738 { .compat = "adm1030" }, 739 DEVICE_COMPAT_EOL 740 }; 741 742 int 743 dbcool_match(device_t parent, cfdata_t cf, void *aux) 744 { 745 struct i2c_attach_args *ia = aux; 746 struct dbcool_chipset dc; 747 dc.dc_tag = ia->ia_tag; 748 dc.dc_addr = ia->ia_addr; 749 dc.dc_chip = NULL; 750 dc.dc_readreg = dbcool_readreg; 751 dc.dc_writereg = dbcool_writereg; 752 int match_result; 753 754 if (iic_use_direct_match(ia, cf, compat_data, &match_result)) 755 return match_result; 756 757 if ((ia->ia_addr & DBCOOL_ADDRMASK) != DBCOOL_ADDR) 758 return 0; 759 if (dbcool_chip_ident(&dc) >= 0) 760 return I2C_MATCH_ADDRESS_AND_PROBE; 761 762 return 0; 763 } 764 765 void 766 dbcool_attach(device_t parent, device_t self, void *aux) 767 { 768 struct dbcool_softc *sc = device_private(self); 769 struct i2c_attach_args *args = aux; 770 uint8_t ver; 771 772 sc->sc_dc.dc_addr = args->ia_addr; 773 sc->sc_dc.dc_tag = args->ia_tag; 774 sc->sc_dc.dc_chip = NULL; 775 sc->sc_dc.dc_readreg = dbcool_readreg; 776 sc->sc_dc.dc_writereg = dbcool_writereg; 777 sc->sc_dev = self; 778 sc->sc_prop = args->ia_prop; 779 prop_object_retain(sc->sc_prop); 780 781 if (dbcool_chip_ident(&sc->sc_dc) < 0 || sc->sc_dc.dc_chip == NULL) 782 panic("could not identify chip at addr %d", args->ia_addr); 783 784 aprint_naive("\n"); 785 aprint_normal("\n"); 786 787 ver = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_REVISION_REG); 788 if (sc->sc_dc.dc_chip->flags & DBCFLAG_4BIT_VER) 789 if (sc->sc_dc.dc_chip->company == SMSC_COMPANYID) 790 { 791 aprint_normal_dev(self, "SMSC %s Controller " 792 "(rev 0x%02x, stepping 0x%02x)\n", 793 sc->sc_dc.dc_chip->name, ver >> 4, ver & 0x0f); 794 } else { 795 aprint_normal_dev(self, "%s dBCool(tm) Controller " 796 "(rev 0x%02x, stepping 0x%02x)\n", 797 sc->sc_dc.dc_chip->name, ver >> 4, ver & 0x0f); 798 } 799 else 800 aprint_normal_dev(self, "%s dBCool(tm) Controller " 801 "(rev 0x%04x)\n", sc->sc_dc.dc_chip->name, ver); 802 803 sc->sc_sysctl_log = NULL; 804 805 #ifdef _MODULE 806 sysctl_dbcoolsetup(&sc->sc_sysctl_log); 807 #endif 808 809 dbcool_setup(self); 810 811 if (!pmf_device_register(self, dbcool_pmf_suspend, dbcool_pmf_resume)) 812 aprint_error_dev(self, "couldn't establish power handler\n"); 813 } 814 815 static int 816 dbcool_detach(device_t self, int flags) 817 { 818 struct dbcool_softc *sc = device_private(self); 819 820 pmf_device_deregister(self); 821 822 sysmon_envsys_unregister(sc->sc_sme); 823 824 sysctl_teardown(&sc->sc_sysctl_log); 825 826 sc->sc_sme = NULL; 827 return 0; 828 } 829 830 /* 831 * On suspend, we save the state of the SHDN bit, then set it 832 * On resume, we restore the previous state of the SHDN bit (which 833 * we saved in sc_suspend) 834 */ 835 static bool 836 dbcool_do_pmf(device_t dev, const pmf_qual_t *qual, bool suspend) 837 { 838 struct dbcool_softc *sc = device_private(dev); 839 uint8_t reg, bit, cfg; 840 841 if ((sc->sc_dc.dc_chip->flags & DBCFLAG_HAS_SHDN) == 0) 842 return true; 843 844 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) { 845 reg = DBCOOL_ADT7466_CONFIG2; 846 bit = DBCOOL_ADT7466_CFG2_SHDN; 847 } else { 848 reg = DBCOOL_CONFIG2_REG; 849 bit = DBCOOL_CFG2_SHDN; 850 } 851 cfg = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 852 if (suspend) { 853 sc->sc_suspend = (cfg & bit) != 0; 854 cfg |= bit; 855 } else { 856 cfg &= sc->sc_suspend ? bit : 0; 857 } 858 sc->sc_dc.dc_writereg(&sc->sc_dc, reg, cfg); 859 860 return true; 861 } 862 863 bool 864 dbcool_pmf_suspend(device_t dev, const pmf_qual_t *qual) 865 { 866 867 return dbcool_do_pmf(dev, qual, true); 868 } 869 870 bool 871 dbcool_pmf_resume(device_t dev, const pmf_qual_t *qual) 872 { 873 874 return dbcool_do_pmf(dev, qual, false); 875 } 876 877 uint8_t 878 dbcool_readreg(struct dbcool_chipset *dc, uint8_t reg) 879 { 880 uint8_t data = 0; 881 882 if (iic_acquire_bus(dc->dc_tag, 0) != 0) 883 return data; 884 885 if (dc->dc_chip == NULL || dc->dc_chip->flags & DBCFLAG_NO_READBYTE) { 886 /* ADM1027 doesn't support i2c read_byte protocol */ 887 if (iic_smbus_send_byte(dc->dc_tag, dc->dc_addr, reg, 0) != 0) 888 goto bad; 889 (void)iic_smbus_receive_byte(dc->dc_tag, dc->dc_addr, &data, 0); 890 } else 891 (void)iic_smbus_read_byte(dc->dc_tag, dc->dc_addr, reg, &data, 892 0); 893 894 bad: 895 iic_release_bus(dc->dc_tag, 0); 896 return data; 897 } 898 899 void 900 dbcool_writereg(struct dbcool_chipset *dc, uint8_t reg, uint8_t val) 901 { 902 if (iic_acquire_bus(dc->dc_tag, 0) != 0) 903 return; 904 905 (void)iic_smbus_write_byte(dc->dc_tag, dc->dc_addr, reg, val, 0); 906 907 iic_release_bus(dc->dc_tag, 0); 908 } 909 910 static bool 911 dbcool_islocked(struct dbcool_softc *sc) 912 { 913 uint8_t cfg_reg; 914 915 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 916 return 0; 917 918 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) 919 cfg_reg = DBCOOL_ADT7466_CONFIG1; 920 else 921 cfg_reg = DBCOOL_CONFIG1_REG; 922 923 if (sc->sc_dc.dc_readreg(&sc->sc_dc, cfg_reg) & DBCOOL_CFG1_LOCK) 924 return 1; 925 else 926 return 0; 927 } 928 929 static int 930 dbcool_read_temp(struct dbcool_softc *sc, uint8_t reg, bool extres) 931 { 932 uint8_t t1, t2, t3, val, ext = 0; 933 int temp; 934 935 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) { 936 /* 937 * ADT7466 temps are in strange location 938 */ 939 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADT7466_CONFIG1); 940 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 941 if (extres) 942 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, reg + 1); 943 } else if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) { 944 /* 945 * ADM1030 temps are in their own special place, too 946 */ 947 if (extres) { 948 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_TEMP_EXTRES); 949 if (reg == DBCOOL_ADM1030_L_TEMP) 950 ext >>= 6; 951 else if (reg == DBCOOL_ADM1031_R2_TEMP) 952 ext >>= 4; 953 else 954 ext >>= 1; 955 ext &= 0x03; 956 } 957 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 958 } else if (extres) { 959 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES2_REG); 960 961 /* Read all msb regs to unlatch them */ 962 t1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_12VIN); 963 t1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_REMOTE1_TEMP); 964 t2 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_REMOTE2_TEMP); 965 t3 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_LOCAL_TEMP); 966 switch (reg) { 967 case DBCOOL_REMOTE1_TEMP: 968 val = t1; 969 ext >>= 2; 970 break; 971 case DBCOOL_LOCAL_TEMP: 972 val = t3; 973 ext >>= 4; 974 break; 975 case DBCOOL_REMOTE2_TEMP: 976 val = t2; 977 ext >>= 6; 978 break; 979 default: 980 val = 0; 981 break; 982 } 983 ext &= 0x03; 984 } 985 else 986 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 987 988 /* Check for invalid temp values */ 989 if ((sc->sc_temp_offset == 0 && val == 0x80) || 990 (sc->sc_temp_offset != 0 && val == 0)) 991 return 0; 992 993 /* If using offset mode, adjust, else treat as signed */ 994 if (sc->sc_temp_offset) { 995 temp = val; 996 temp -= sc->sc_temp_offset; 997 } else 998 temp = (int8_t)val; 999 1000 /* Convert degC to uK and include extended precision bits */ 1001 temp *= 1000000; 1002 temp += 250000 * (int)ext; 1003 temp += 273150000U; 1004 1005 return temp; 1006 } 1007 1008 static int 1009 dbcool_read_rpm(struct dbcool_softc *sc, uint8_t reg) 1010 { 1011 int rpm; 1012 uint8_t rpm_lo, rpm_hi; 1013 1014 rpm_lo = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 1015 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 1016 rpm_hi = (rpm_lo == 0xff)?0xff:0x0; 1017 else 1018 rpm_hi = sc->sc_dc.dc_readreg(&sc->sc_dc, reg + 1); 1019 1020 rpm = (rpm_hi << 8) | rpm_lo; 1021 if (rpm == 0xffff) 1022 return 0; /* 0xffff indicates stalled/failed fan */ 1023 1024 /* don't divide by zero */ 1025 return (rpm == 0)? 0 : (sc->sc_dc.dc_chip->rpm_dividend / rpm); 1026 } 1027 1028 /* Provide chip's supply voltage, in microvolts */ 1029 static int 1030 dbcool_supply_voltage(struct dbcool_softc *sc) 1031 { 1032 if (sc->sc_dc.dc_chip->flags & DBCFLAG_MULTI_VCC) { 1033 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_CONFIG1_REG) & DBCOOL_CFG1_Vcc) 1034 return 5002500; 1035 else 1036 return 3300000; 1037 } else if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) { 1038 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADT7466_CONFIG1) & 1039 DBCOOL_ADT7466_CFG1_Vcc) 1040 return 5000000; 1041 else 1042 return 3300000; 1043 } else 1044 return 3300000; 1045 } 1046 1047 /* 1048 * Nominal voltages are calculated in microvolts 1049 */ 1050 static int 1051 dbcool_read_volt(struct dbcool_softc *sc, uint8_t reg, int nom_idx, bool extres) 1052 { 1053 uint8_t ext = 0, v1, v2, v3, v4, val; 1054 int64_t ret; 1055 int64_t nom; 1056 1057 nom = nominal_voltages[nom_idx]; 1058 if (nom < 0) 1059 nom = sc->sc_supply_voltage; 1060 1061 /* ADT7466 voltages are in strange locations with only 8-bits */ 1062 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) 1063 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 1064 else 1065 /* 1066 * It's a "normal" dbCool chip - check for regs that 1067 * share extended resolution bits since we have to 1068 * read all the MSB registers to unlatch them. 1069 */ 1070 if (!extres) 1071 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 1072 else if (reg == DBCOOL_12VIN) { 1073 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES2_REG) & 0x03; 1074 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 1075 (void)dbcool_read_temp(sc, DBCOOL_LOCAL_TEMP, true); 1076 } else if (reg == DBCOOL_VTT || reg == DBCOOL_IMON) { 1077 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES_VTT_IMON); 1078 v1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_IMON); 1079 v2 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VTT); 1080 if (reg == DBCOOL_IMON) { 1081 val = v1; 1082 ext >>= 6; 1083 } else { 1084 val = v2; 1085 ext >>= 4; 1086 } 1087 ext &= 0x0f; 1088 } else { 1089 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES1_REG); 1090 v1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_25VIN); 1091 v2 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VCCP); 1092 v3 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VCC); 1093 v4 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_5VIN); 1094 1095 switch (reg) { 1096 case DBCOOL_25VIN: 1097 val = v1; 1098 break; 1099 case DBCOOL_VCCP: 1100 val = v2; 1101 ext >>= 2; 1102 break; 1103 case DBCOOL_VCC: 1104 val = v3; 1105 ext >>= 4; 1106 break; 1107 case DBCOOL_5VIN: 1108 val = v4; 1109 ext >>= 6; 1110 break; 1111 default: 1112 val = nom = 0; 1113 } 1114 ext &= 0x03; 1115 } 1116 1117 /* 1118 * Scale the nominal value by the 10-bit fraction 1119 * 1120 * Returned value is in microvolts. 1121 */ 1122 ret = val; 1123 ret <<= 2; 1124 ret |= ext; 1125 ret = (ret * nom) / 0x300; 1126 1127 return ret; 1128 } 1129 1130 static int 1131 sysctl_dbcool_temp(SYSCTLFN_ARGS) 1132 { 1133 struct sysctlnode node; 1134 struct dbcool_softc *sc; 1135 int reg, error; 1136 uint8_t chipreg; 1137 uint8_t newreg; 1138 1139 node = *rnode; 1140 sc = (struct dbcool_softc *)node.sysctl_data; 1141 chipreg = node.sysctl_num & 0xff; 1142 1143 if (sc->sc_temp_offset) { 1144 reg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1145 reg -= sc->sc_temp_offset; 1146 } else 1147 reg = (int8_t)sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1148 1149 node.sysctl_data = ® 1150 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1151 1152 if (error || newp == NULL) 1153 return error; 1154 1155 /* We were asked to update the value - sanity check before writing */ 1156 if (*(int *)node.sysctl_data < -64 || 1157 *(int *)node.sysctl_data > 127 + sc->sc_temp_offset) 1158 return EINVAL; 1159 1160 newreg = *(int *)node.sysctl_data; 1161 newreg += sc->sc_temp_offset; 1162 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1163 return 0; 1164 } 1165 1166 static int 1167 sysctl_adm1030_temp(SYSCTLFN_ARGS) 1168 { 1169 struct sysctlnode node; 1170 struct dbcool_softc *sc; 1171 int reg, error; 1172 uint8_t chipreg, oldreg, newreg; 1173 1174 node = *rnode; 1175 sc = (struct dbcool_softc *)node.sysctl_data; 1176 chipreg = node.sysctl_num & 0xff; 1177 1178 oldreg = (int8_t)sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1179 reg = (oldreg >> 1) & ~0x03; 1180 1181 node.sysctl_data = ® 1182 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1183 1184 if (error || newp == NULL) 1185 return error; 1186 1187 /* We were asked to update the value - sanity check before writing */ 1188 if (*(int *)node.sysctl_data < 0 || *(int *)node.sysctl_data > 127) 1189 return EINVAL; 1190 1191 newreg = *(int *)node.sysctl_data; 1192 newreg &= ~0x03; 1193 newreg <<= 1; 1194 newreg |= (oldreg & 0x07); 1195 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1196 return 0; 1197 } 1198 1199 static int 1200 sysctl_adm1030_trange(SYSCTLFN_ARGS) 1201 { 1202 struct sysctlnode node; 1203 struct dbcool_softc *sc; 1204 int reg, error, newval; 1205 uint8_t chipreg, oldreg, newreg; 1206 1207 node = *rnode; 1208 sc = (struct dbcool_softc *)node.sysctl_data; 1209 chipreg = node.sysctl_num & 0xff; 1210 1211 oldreg = (int8_t)sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1212 reg = oldreg & 0x07; 1213 1214 node.sysctl_data = ® 1215 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1216 1217 if (error || newp == NULL) 1218 return error; 1219 1220 /* We were asked to update the value - sanity check before writing */ 1221 newval = *(int *)node.sysctl_data; 1222 1223 if (newval == 5) 1224 newreg = 0; 1225 else if (newval == 10) 1226 newreg = 1; 1227 else if (newval == 20) 1228 newreg = 2; 1229 else if (newval == 40) 1230 newreg = 3; 1231 else if (newval == 80) 1232 newreg = 4; 1233 else 1234 return EINVAL; 1235 1236 newreg |= (oldreg & ~0x07); 1237 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1238 return 0; 1239 } 1240 1241 static int 1242 sysctl_dbcool_duty(SYSCTLFN_ARGS) 1243 { 1244 struct sysctlnode node; 1245 struct dbcool_softc *sc; 1246 int reg, error; 1247 uint8_t chipreg, oldreg, newreg; 1248 1249 node = *rnode; 1250 sc = (struct dbcool_softc *)node.sysctl_data; 1251 chipreg = node.sysctl_num & 0xff; 1252 1253 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1254 reg = (uint32_t)oldreg; 1255 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 1256 reg = ((reg & 0x0f) * 100) / 15; 1257 else 1258 reg = (reg * 100) / 255; 1259 node.sysctl_data = ® 1260 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1261 1262 if (error || newp == NULL) 1263 return error; 1264 1265 /* We were asked to update the value - sanity check before writing */ 1266 if (*(int *)node.sysctl_data < 0 || *(int *)node.sysctl_data > 100) 1267 return EINVAL; 1268 1269 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) { 1270 newreg = *(uint8_t *)(node.sysctl_data) * 15 / 100; 1271 newreg |= oldreg & 0xf0; 1272 } else 1273 newreg = *(uint8_t *)(node.sysctl_data) * 255 / 100; 1274 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1275 return 0; 1276 } 1277 1278 static int 1279 sysctl_dbcool_behavior(SYSCTLFN_ARGS) 1280 { 1281 struct sysctlnode node; 1282 struct dbcool_softc *sc; 1283 int i, reg, error; 1284 uint8_t chipreg, oldreg, newreg; 1285 1286 node = *rnode; 1287 sc = (struct dbcool_softc *)node.sysctl_data; 1288 chipreg = node.sysctl_num & 0xff; 1289 1290 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1291 1292 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) { 1293 if ((sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_CFG2) & 1) == 0) 1294 reg = 4; 1295 else if ((oldreg & 0x80) == 0) 1296 reg = 7; 1297 else if ((oldreg & 0x60) == 0) 1298 reg = 4; 1299 else 1300 reg = 6; 1301 } else 1302 reg = (oldreg >> 5) & 0x07; 1303 1304 strlcpy(dbcool_cur_behav, behavior[reg], sizeof(dbcool_cur_behav)); 1305 node.sysctl_data = dbcool_cur_behav; 1306 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1307 1308 if (error || newp == NULL) 1309 return error; 1310 1311 /* We were asked to update the value - convert string to value */ 1312 newreg = __arraycount(behavior); 1313 for (i = 0; i < __arraycount(behavior); i++) 1314 if (strcmp(node.sysctl_data, behavior[i]) == 0) 1315 break; 1316 if (i >= __arraycount(behavior)) 1317 return EINVAL; 1318 newreg = i; 1319 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) { 1320 /* 1321 * ADM1030 splits fan controller behavior across two 1322 * registers. We also do not support Auto-Filter mode 1323 * nor do we support Manual-RPM-feedback. 1324 */ 1325 if (newreg == 4) { 1326 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_CFG2); 1327 oldreg &= ~0x01; 1328 sc->sc_dc.dc_writereg(&sc->sc_dc, DBCOOL_ADM1030_CFG2, oldreg); 1329 } else { 1330 if (newreg == 0) 1331 newreg = 4; 1332 else if (newreg == 6) 1333 newreg = 7; 1334 else if (newreg == 7) 1335 newreg = 0; 1336 else 1337 return EINVAL; 1338 newreg <<= 5; 1339 newreg |= (oldreg & 0x1f); 1340 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1341 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_CFG2) | 1; 1342 sc->sc_dc.dc_writereg(&sc->sc_dc, DBCOOL_ADM1030_CFG2, oldreg); 1343 } 1344 } else { 1345 newreg = (sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg) & 0x1f) | (i << 5); 1346 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1347 } 1348 return 0; 1349 } 1350 1351 static int 1352 sysctl_dbcool_slope(SYSCTLFN_ARGS) 1353 { 1354 struct sysctlnode node; 1355 struct dbcool_softc *sc; 1356 int reg, error; 1357 uint8_t chipreg; 1358 uint8_t newreg; 1359 1360 node = *rnode; 1361 sc = (struct dbcool_softc *)node.sysctl_data; 1362 chipreg = node.sysctl_num & 0xff; 1363 1364 reg = (sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg) >> 4) & 0x0f; 1365 node.sysctl_data = ® 1366 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1367 1368 if (error || newp == NULL) 1369 return error; 1370 1371 /* We were asked to update the value - sanity check before writing */ 1372 if (*(int *)node.sysctl_data < 0 || *(int *)node.sysctl_data > 0x0f) 1373 return EINVAL; 1374 1375 newreg = (sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg) & 0x0f) | 1376 (*(int *)node.sysctl_data << 4); 1377 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1378 return 0; 1379 } 1380 1381 static int 1382 sysctl_dbcool_thyst(SYSCTLFN_ARGS) 1383 { 1384 struct sysctlnode node; 1385 struct dbcool_softc *sc; 1386 int reg, error; 1387 uint8_t chipreg; 1388 uint8_t newreg, newhyst; 1389 1390 node = *rnode; 1391 sc = (struct dbcool_softc *)node.sysctl_data; 1392 chipreg = node.sysctl_num & 0x7f; 1393 1394 /* retrieve 4-bit value */ 1395 newreg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1396 if ((node.sysctl_num & 0x80) == 0) 1397 reg = newreg >> 4; 1398 else 1399 reg = newreg; 1400 reg = reg & 0x0f; 1401 1402 node.sysctl_data = ® 1403 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1404 1405 if (error || newp == NULL) 1406 return error; 1407 1408 /* We were asked to update the value - sanity check before writing */ 1409 newhyst = *(int *)node.sysctl_data; 1410 if (newhyst > 0x0f) 1411 return EINVAL; 1412 1413 /* Insert new value into field and update register */ 1414 if ((node.sysctl_num & 0x80) == 0) { 1415 newreg &= 0x0f; 1416 newreg |= (newhyst << 4); 1417 } else { 1418 newreg &= 0xf0; 1419 newreg |= newhyst; 1420 } 1421 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1422 return 0; 1423 } 1424 1425 #ifdef DBCOOL_DEBUG 1426 1427 /* 1428 * These routines can be used for debugging. reg_select is used to 1429 * select any arbitrary register in the device. reg_access is used 1430 * to read (and optionally update) the selected register. 1431 * 1432 * No attempt is made to validate the data passed. If you use these 1433 * routines, you are assumed to know what you're doing! 1434 * 1435 * Caveat user 1436 */ 1437 static int 1438 sysctl_dbcool_reg_select(SYSCTLFN_ARGS) 1439 { 1440 struct sysctlnode node; 1441 struct dbcool_softc *sc; 1442 int reg, error; 1443 1444 node = *rnode; 1445 sc = (struct dbcool_softc *)node.sysctl_data; 1446 1447 reg = sc->sc_user_reg; 1448 node.sysctl_data = ® 1449 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1450 1451 if (error || newp == NULL) 1452 return error; 1453 1454 sc->sc_user_reg = *(int *)node.sysctl_data; 1455 return 0; 1456 } 1457 1458 static int 1459 sysctl_dbcool_reg_access(SYSCTLFN_ARGS) 1460 { 1461 struct sysctlnode node; 1462 struct dbcool_softc *sc; 1463 int reg, error; 1464 uint8_t chipreg; 1465 uint8_t newreg; 1466 1467 node = *rnode; 1468 sc = (struct dbcool_softc *)node.sysctl_data; 1469 chipreg = sc->sc_user_reg; 1470 1471 reg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1472 node.sysctl_data = ® 1473 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1474 1475 if (error || newp == NULL) 1476 return error; 1477 1478 newreg = *(int *)node.sysctl_data; 1479 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1480 return 0; 1481 } 1482 #endif /* DBCOOL_DEBUG */ 1483 1484 /* 1485 * Encode an index number and register number for use as a sysctl_num 1486 * so we can select the correct device register later. 1487 */ 1488 #define DBC_PWM_SYSCTL(seq, reg) ((seq << 8) | reg) 1489 1490 void 1491 dbcool_setup(device_t self) 1492 { 1493 struct dbcool_softc *sc = device_private(self); 1494 const struct sysctlnode *me = NULL; 1495 #ifdef DBCOOL_DEBUG 1496 struct sysctlnode *node = NULL; 1497 #endif 1498 uint8_t cfg_val, cfg_reg; 1499 int ret, error; 1500 1501 /* 1502 * Some chips are capable of reporting an extended temperature range 1503 * by default. On these models, config register 5 bit 0 can be set 1504 * to 1 for compatability with other chips that report 2s complement. 1505 */ 1506 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) { 1507 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADT7466_CONFIG1) & 0x80) 1508 sc->sc_temp_offset = 64; 1509 else 1510 sc->sc_temp_offset = 0; 1511 } else if (sc->sc_dc.dc_chip->flags & DBCFLAG_TEMPOFFSET) { 1512 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_CONFIG5_REG) & 1513 DBCOOL_CFG5_TWOSCOMP) 1514 sc->sc_temp_offset = 0; 1515 else 1516 sc->sc_temp_offset = 64; 1517 } else 1518 sc->sc_temp_offset = 0; 1519 1520 /* Determine Vcc for this chip */ 1521 sc->sc_supply_voltage = dbcool_supply_voltage(sc); 1522 1523 ret = sysctl_createv(&sc->sc_sysctl_log, 0, NULL, &me, 1524 CTLFLAG_READWRITE, 1525 CTLTYPE_NODE, device_xname(self), NULL, 1526 NULL, 0, NULL, 0, 1527 CTL_HW, CTL_CREATE, CTL_EOL); 1528 if (ret == 0) 1529 sc->sc_root_sysctl_num = me->sysctl_num; 1530 else 1531 sc->sc_root_sysctl_num = 0; 1532 1533 aprint_debug_dev(self, 1534 "Supply voltage %"PRId64".%06"PRId64"V, %s temp range\n", 1535 sc->sc_supply_voltage / 1000000, 1536 sc->sc_supply_voltage % 1000000, 1537 sc->sc_temp_offset ? "extended" : "normal"); 1538 1539 /* Create the sensors for this device */ 1540 sc->sc_sme = sysmon_envsys_create(); 1541 if (dbcool_setup_sensors(sc)) 1542 goto out; 1543 1544 if (sc->sc_root_sysctl_num != 0) { 1545 /* If supported, create sysctl tree for fan PWM controllers */ 1546 if (sc->sc_dc.dc_chip->power != NULL) 1547 dbcool_setup_controllers(sc); 1548 1549 #ifdef DBCOOL_DEBUG 1550 ret = sysctl_createv(&sc->sc_sysctl_log, 0, NULL, 1551 (void *)&node, 1552 CTLFLAG_READWRITE, CTLTYPE_INT, "reg_select", NULL, 1553 sysctl_dbcool_reg_select, 1554 0, (void *)sc, sizeof(int), 1555 CTL_HW, me->sysctl_num, CTL_CREATE, CTL_EOL); 1556 if (node != NULL) 1557 node->sysctl_data = sc; 1558 1559 ret = sysctl_createv(&sc->sc_sysctl_log, 0, NULL, 1560 (void *)&node, 1561 CTLFLAG_READWRITE, CTLTYPE_INT, "reg_access", NULL, 1562 sysctl_dbcool_reg_access, 1563 0, (void *)sc, sizeof(int), 1564 CTL_HW, me->sysctl_num, CTL_CREATE, CTL_EOL); 1565 if (node != NULL) 1566 node->sysctl_data = sc; 1567 #endif /* DBCOOL_DEBUG */ 1568 } 1569 1570 /* 1571 * Read and rewrite config register to activate device 1572 */ 1573 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 1574 cfg_reg = DBCOOL_ADM1030_CFG1; 1575 else if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) 1576 cfg_reg = DBCOOL_ADT7466_CONFIG1; 1577 else 1578 cfg_reg = DBCOOL_CONFIG1_REG; 1579 cfg_val = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_CONFIG1_REG); 1580 if ((cfg_val & DBCOOL_CFG1_START) == 0) { 1581 cfg_val |= DBCOOL_CFG1_START; 1582 sc->sc_dc.dc_writereg(&sc->sc_dc, cfg_reg, cfg_val); 1583 } 1584 if (dbcool_islocked(sc)) 1585 aprint_normal_dev(self, "configuration locked\n"); 1586 1587 sc->sc_sme->sme_name = device_xname(self); 1588 sc->sc_sme->sme_cookie = sc; 1589 sc->sc_sme->sme_refresh = dbcool_refresh; 1590 sc->sc_sme->sme_set_limits = dbcool_set_limits; 1591 sc->sc_sme->sme_get_limits = dbcool_get_limits; 1592 1593 if ((error = sysmon_envsys_register(sc->sc_sme)) != 0) { 1594 aprint_error_dev(self, 1595 "unable to register with sysmon (%d)\n", error); 1596 goto out; 1597 } 1598 1599 return; 1600 1601 out: 1602 sysmon_envsys_destroy(sc->sc_sme); 1603 } 1604 1605 static int 1606 dbcool_setup_sensors(struct dbcool_softc *sc) 1607 { 1608 int i; 1609 int error = 0; 1610 uint8_t vid_reg, vid_val; 1611 struct chip_id *chip = sc->sc_dc.dc_chip; 1612 1613 for (i=0; chip->table[i].type != DBC_EOF; i++) { 1614 if (i < DBCOOL_MAXSENSORS) 1615 sc->sc_sysctl_num[i] = -1; 1616 else if (chip->table[i].type != DBC_CTL) { 1617 aprint_normal_dev(sc->sc_dev, "chip table too big!\n"); 1618 break; 1619 } 1620 switch (chip->table[i].type) { 1621 case DBC_TEMP: 1622 sc->sc_sensor[i].units = ENVSYS_STEMP; 1623 sc->sc_sensor[i].state = ENVSYS_SINVALID; 1624 sc->sc_sensor[i].flags |= ENVSYS_FMONLIMITS; 1625 sc->sc_sensor[i].flags |= ENVSYS_FHAS_ENTROPY; 1626 error = dbcool_attach_sensor(sc, i); 1627 break; 1628 case DBC_VOLT: 1629 /* 1630 * If 12V-In pin has been reconfigured as 6th bit 1631 * of VID code, don't create a 12V-In sensor 1632 */ 1633 if ((chip->flags & DBCFLAG_HAS_VID_SEL) && 1634 (chip->table[i].reg.val_reg == DBCOOL_12VIN) && 1635 (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VID_REG) & 1636 0x80)) 1637 break; 1638 1639 sc->sc_sensor[i].units = ENVSYS_SVOLTS_DC; 1640 sc->sc_sensor[i].state = ENVSYS_SINVALID; 1641 sc->sc_sensor[i].flags |= ENVSYS_FMONLIMITS; 1642 sc->sc_sensor[i].flags |= ENVSYS_FHAS_ENTROPY; 1643 error = dbcool_attach_sensor(sc, i); 1644 break; 1645 case DBC_FAN: 1646 sc->sc_sensor[i].units = ENVSYS_SFANRPM; 1647 sc->sc_sensor[i].state = ENVSYS_SINVALID; 1648 sc->sc_sensor[i].flags |= ENVSYS_FMONLIMITS; 1649 sc->sc_sensor[i].flags |= ENVSYS_FHAS_ENTROPY; 1650 error = dbcool_attach_sensor(sc, i); 1651 break; 1652 case DBC_VID: 1653 sc->sc_sensor[i].units = ENVSYS_INTEGER; 1654 sc->sc_sensor[i].state = ENVSYS_SINVALID; 1655 sc->sc_sensor[i].flags |= ENVSYS_FMONNOTSUPP; 1656 1657 /* retrieve 5- or 6-bit value */ 1658 vid_reg = chip->table[i].reg.val_reg; 1659 vid_val = sc->sc_dc.dc_readreg(&sc->sc_dc, vid_reg); 1660 if (chip->flags & DBCFLAG_HAS_VID_SEL) 1661 vid_val &= 0x3f; 1662 else 1663 vid_val &= 0x1f; 1664 sc->sc_sensor[i].value_cur = vid_val; 1665 1666 error = dbcool_attach_sensor(sc, i); 1667 break; 1668 case DBC_CTL: 1669 error = dbcool_attach_temp_control(sc, i, chip); 1670 if (error) { 1671 aprint_error_dev(sc->sc_dev, 1672 "attach index %d failed %d\n", 1673 i, error); 1674 error = 0; 1675 } 1676 break; 1677 default: 1678 aprint_error_dev(sc->sc_dev, 1679 "sensor_table index %d has bad type %d\n", 1680 i, chip->table[i].type); 1681 break; 1682 } 1683 if (error) 1684 break; 1685 } 1686 return error; 1687 } 1688 1689 static int 1690 dbcool_attach_sensor(struct dbcool_softc *sc, int idx) 1691 { 1692 int name_index; 1693 int error = 0; 1694 char name[8]; 1695 const char *desc; 1696 1697 name_index = sc->sc_dc.dc_chip->table[idx].name_index; 1698 snprintf(name, 7, "s%02x", sc->sc_dc.dc_chip->table[idx].reg.val_reg); 1699 if (prop_dictionary_get_cstring_nocopy(sc->sc_prop, name, &desc)) { 1700 strlcpy(sc->sc_sensor[idx].desc, desc, 1701 sizeof(sc->sc_sensor[idx].desc)); 1702 } else { 1703 strlcpy(sc->sc_sensor[idx].desc, dbc_sensor_names[name_index], 1704 sizeof(sc->sc_sensor[idx].desc)); 1705 } 1706 sc->sc_regs[idx] = &sc->sc_dc.dc_chip->table[idx].reg; 1707 sc->sc_nom_volt[idx] = sc->sc_dc.dc_chip->table[idx].nom_volt_index; 1708 1709 error = sysmon_envsys_sensor_attach(sc->sc_sme, &sc->sc_sensor[idx]); 1710 return error; 1711 } 1712 1713 static int 1714 dbcool_attach_temp_control(struct dbcool_softc *sc, int idx, 1715 struct chip_id *chip) 1716 { 1717 const struct sysctlnode *me2 = NULL, *node; 1718 int j, ret, sysctl_index, rw_flag; 1719 uint8_t sysctl_reg; 1720 char name[SYSCTL_NAMELEN]; 1721 1722 /* Search for the corresponding temp sensor */ 1723 for (j = 0; j < idx; j++) { 1724 if (j >= DBCOOL_MAXSENSORS || chip->table[j].type != DBC_TEMP) 1725 continue; 1726 if (chip->table[j].name_index == chip->table[idx].name_index) 1727 break; 1728 } 1729 if (j >= idx) /* Temp sensor not found */ 1730 return ENOENT; 1731 1732 /* create sysctl node for the sensor if not one already there */ 1733 if (sc->sc_sysctl_num[j] == -1) { 1734 int name_index = sc->sc_dc.dc_chip->table[idx].name_index; 1735 1736 ret = sysctl_createv(&sc->sc_sysctl_log, 0, NULL, &me2, 1737 CTLFLAG_READWRITE, 1738 CTLTYPE_NODE, dbc_sensor_names[name_index], 1739 sc->sc_sensor[j].desc, 1740 NULL, 0, NULL, 0, 1741 CTL_HW, sc->sc_root_sysctl_num, CTL_CREATE, 1742 CTL_EOL); 1743 if (me2 != NULL) 1744 sc->sc_sysctl_num[j] = me2->sysctl_num; 1745 else 1746 return ret; 1747 } 1748 /* add sysctl leaf node for this control variable */ 1749 sysctl_index = chip->table[idx].sysctl_index; 1750 sysctl_reg = chip->table[idx].reg.val_reg; 1751 strlcpy(name, dbc_sysctl_table[sysctl_index].name, sizeof(name)); 1752 if (dbc_sysctl_table[sysctl_index].lockable && dbcool_islocked(sc)) 1753 rw_flag = CTLFLAG_READONLY | CTLFLAG_OWNDESC; 1754 else 1755 rw_flag = CTLFLAG_READWRITE | CTLFLAG_OWNDESC; 1756 ret = sysctl_createv(&sc->sc_sysctl_log, 0, NULL, &node, rw_flag, 1757 CTLTYPE_INT, name, 1758 SYSCTL_DESCR(dbc_sysctl_table[sysctl_index].desc), 1759 dbc_sysctl_table[sysctl_index].helper, 1760 0, (void *)sc, sizeof(int), 1761 CTL_HW, sc->sc_root_sysctl_num, 1762 sc->sc_sysctl_num[j], 1763 DBC_PWM_SYSCTL(idx, sysctl_reg), CTL_EOL); 1764 1765 return ret; 1766 } 1767 1768 static void 1769 dbcool_setup_controllers(struct dbcool_softc *sc) 1770 { 1771 int i, j, rw_flag; 1772 uint8_t sysctl_reg; 1773 struct chip_id *chip = sc->sc_dc.dc_chip; 1774 const struct sysctlnode *me2 = NULL; 1775 const struct sysctlnode *node = NULL; 1776 char name[SYSCTL_NAMELEN]; 1777 1778 for (i = 0; chip->power[i].desc != NULL; i++) { 1779 snprintf(name, sizeof(name), "fan_ctl_%d", i); 1780 sysctl_createv(&sc->sc_sysctl_log, 0, NULL, &me2, 1781 CTLFLAG_READWRITE | CTLFLAG_OWNDESC, 1782 CTLTYPE_NODE, name, NULL, 1783 NULL, 0, NULL, 0, 1784 CTL_HW, sc->sc_root_sysctl_num, CTL_CREATE, CTL_EOL); 1785 1786 for (j = DBC_PWM_BEHAVIOR; j < DBC_PWM_LAST_PARAM; j++) { 1787 if (j == DBC_PWM_MAX_DUTY && 1788 (chip->flags & DBCFLAG_HAS_MAXDUTY) == 0) 1789 continue; 1790 sysctl_reg = chip->power[i].power_regs[j]; 1791 if (sysctl_reg == DBCOOL_NO_REG) 1792 continue; 1793 strlcpy(name, dbc_sysctl_table[j].name, sizeof(name)); 1794 if (dbc_sysctl_table[j].lockable && dbcool_islocked(sc)) 1795 rw_flag = CTLFLAG_READONLY | CTLFLAG_OWNDESC; 1796 else 1797 rw_flag = CTLFLAG_READWRITE | CTLFLAG_OWNDESC; 1798 (sysctl_createv)(&sc->sc_sysctl_log, 0, NULL, 1799 &node, rw_flag, 1800 (j == DBC_PWM_BEHAVIOR)? 1801 CTLTYPE_STRING:CTLTYPE_INT, 1802 name, 1803 SYSCTL_DESCR(dbc_sysctl_table[j].desc), 1804 dbc_sysctl_table[j].helper, 1805 0, sc, 1806 ( j == DBC_PWM_BEHAVIOR)? 1807 sizeof(dbcool_cur_behav): sizeof(int), 1808 CTL_HW, sc->sc_root_sysctl_num, me2->sysctl_num, 1809 DBC_PWM_SYSCTL(j, sysctl_reg), CTL_EOL); 1810 } 1811 } 1812 } 1813 1814 static void 1815 dbcool_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 1816 { 1817 struct dbcool_softc *sc=sme->sme_cookie; 1818 int i, nom_volt_idx, cur; 1819 struct reg_list *reg; 1820 1821 i = edata->sensor; 1822 reg = sc->sc_regs[i]; 1823 1824 edata->state = ENVSYS_SVALID; 1825 switch (edata->units) 1826 { 1827 case ENVSYS_STEMP: 1828 cur = dbcool_read_temp(sc, reg->val_reg, true); 1829 break; 1830 case ENVSYS_SVOLTS_DC: 1831 nom_volt_idx = sc->sc_nom_volt[i]; 1832 cur = dbcool_read_volt(sc, reg->val_reg, nom_volt_idx, 1833 true); 1834 break; 1835 case ENVSYS_SFANRPM: 1836 cur = dbcool_read_rpm(sc, reg->val_reg); 1837 break; 1838 case ENVSYS_INTEGER: 1839 return; 1840 default: 1841 edata->state = ENVSYS_SINVALID; 1842 return; 1843 } 1844 1845 if (cur == 0 && (edata->units != ENVSYS_SFANRPM)) 1846 edata->state = ENVSYS_SINVALID; 1847 1848 /* 1849 * If fan is "stalled" but has no low limit, treat 1850 * it as though the fan is not installed. 1851 */ 1852 else if (edata->units == ENVSYS_SFANRPM && cur == 0 && 1853 !(edata->upropset & (PROP_CRITMIN | PROP_WARNMIN))) 1854 edata->state = ENVSYS_SINVALID; 1855 1856 edata->value_cur = cur; 1857 } 1858 1859 int 1860 dbcool_chip_ident(struct dbcool_chipset *dc) 1861 { 1862 /* verify this is a supported dbCool chip */ 1863 uint8_t c_id, d_id, r_id; 1864 int i; 1865 1866 c_id = dc->dc_readreg(dc, DBCOOL_COMPANYID_REG); 1867 d_id = dc->dc_readreg(dc, DBCOOL_DEVICEID_REG); 1868 r_id = dc->dc_readreg(dc, DBCOOL_REVISION_REG); 1869 1870 /* The EMC6D103S only supports read_byte and since dc->dc_chip is 1871 * NULL when we call dc->dc_readreg above we use 1872 * send_byte/receive_byte which doesn't work. 1873 * 1874 * So if we only get 0's back then try again with dc->dc_chip 1875 * set to the EMC6D103S_DEVICEID and which doesn't have 1876 * DBCFLAG_NO_READBYTE set so read_byte will be used 1877 */ 1878 if ((c_id == 0) && (d_id == 0) && (r_id == 0)) { 1879 for (i = 0; chip_table[i].company != 0; i++) 1880 if ((SMSC_COMPANYID == chip_table[i].company) && 1881 (EMC6D103S_DEVICEID == chip_table[i].device)) { 1882 dc->dc_chip = &chip_table[i]; 1883 break; 1884 } 1885 c_id = dc->dc_readreg(dc, DBCOOL_COMPANYID_REG); 1886 d_id = dc->dc_readreg(dc, DBCOOL_DEVICEID_REG); 1887 r_id = dc->dc_readreg(dc, DBCOOL_REVISION_REG); 1888 } 1889 1890 for (i = 0; chip_table[i].company != 0; i++) 1891 if ((c_id == chip_table[i].company) && 1892 (d_id == chip_table[i].device || 1893 chip_table[i].device == 0xff) && 1894 (r_id == chip_table[i].rev || 1895 chip_table[i].rev == 0xff)) { 1896 dc->dc_chip = &chip_table[i]; 1897 return i; 1898 } 1899 1900 aprint_debug("dbcool_chip_ident: addr 0x%02x c_id 0x%02x d_id 0x%02x" 1901 " r_id 0x%02x: No match.\n", dc->dc_addr, c_id, d_id, 1902 r_id); 1903 1904 return -1; 1905 } 1906 1907 /* 1908 * Retrieve sensor limits from the chip registers 1909 */ 1910 static void 1911 dbcool_get_limits(struct sysmon_envsys *sme, envsys_data_t *edata, 1912 sysmon_envsys_lim_t *limits, uint32_t *props) 1913 { 1914 int index = edata->sensor; 1915 struct dbcool_softc *sc = sme->sme_cookie; 1916 1917 *props &= ~(PROP_CRITMIN | PROP_CRITMAX); 1918 switch (edata->units) { 1919 case ENVSYS_STEMP: 1920 dbcool_get_temp_limits(sc, index, limits, props); 1921 break; 1922 case ENVSYS_SVOLTS_DC: 1923 dbcool_get_volt_limits(sc, index, limits, props); 1924 break; 1925 case ENVSYS_SFANRPM: 1926 dbcool_get_fan_limits(sc, index, limits, props); 1927 1928 /* FALLTHROUGH */ 1929 default: 1930 break; 1931 } 1932 *props &= ~PROP_DRIVER_LIMITS; 1933 1934 /* If both limits provided, make sure they're sane */ 1935 if ((*props & PROP_CRITMIN) && 1936 (*props & PROP_CRITMAX) && 1937 (limits->sel_critmin >= limits->sel_critmax)) 1938 *props &= ~(PROP_CRITMIN | PROP_CRITMAX); 1939 1940 /* 1941 * If this is the first time through, save these values 1942 * in case user overrides them and then requests a reset. 1943 */ 1944 if (sc->sc_defprops[index] == 0) { 1945 sc->sc_defprops[index] = *props | PROP_DRIVER_LIMITS; 1946 sc->sc_deflims[index] = *limits; 1947 } 1948 } 1949 1950 static void 1951 dbcool_get_temp_limits(struct dbcool_softc *sc, int idx, 1952 sysmon_envsys_lim_t *lims, uint32_t *props) 1953 { 1954 struct reg_list *reg = sc->sc_regs[idx]; 1955 uint8_t lo_lim, hi_lim; 1956 1957 lo_lim = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->lo_lim_reg); 1958 hi_lim = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->hi_lim_reg); 1959 1960 if (sc->sc_temp_offset) { 1961 if (lo_lim > 0x01) { 1962 lims->sel_critmin = lo_lim - sc->sc_temp_offset; 1963 *props |= PROP_CRITMIN; 1964 } 1965 if (hi_lim != 0xff) { 1966 lims->sel_critmax = hi_lim - sc->sc_temp_offset; 1967 *props |= PROP_CRITMAX; 1968 } 1969 } else { 1970 if (lo_lim != 0x80 && lo_lim != 0x81) { 1971 lims->sel_critmin = (int8_t)lo_lim; 1972 *props |= PROP_CRITMIN; 1973 } 1974 1975 if (hi_lim != 0x7f) { 1976 lims->sel_critmax = (int8_t)hi_lim; 1977 *props |= PROP_CRITMAX; 1978 } 1979 } 1980 1981 /* Convert temp limits to microKelvin */ 1982 lims->sel_critmin *= 1000000; 1983 lims->sel_critmin += 273150000; 1984 lims->sel_critmax *= 1000000; 1985 lims->sel_critmax += 273150000; 1986 } 1987 1988 static void 1989 dbcool_get_volt_limits(struct dbcool_softc *sc, int idx, 1990 sysmon_envsys_lim_t *lims, uint32_t *props) 1991 { 1992 struct reg_list *reg = sc->sc_regs[idx]; 1993 int64_t limit; 1994 int nom; 1995 1996 nom = nominal_voltages[sc->sc_dc.dc_chip->table[idx].nom_volt_index]; 1997 if (nom < 0) 1998 nom = dbcool_supply_voltage(sc); 1999 nom *= 1000000; /* scale for microvolts */ 2000 2001 limit = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->lo_lim_reg); 2002 if (limit != 0x00 && limit != 0xff) { 2003 limit *= nom; 2004 limit /= 0xc0; 2005 lims->sel_critmin = limit; 2006 *props |= PROP_CRITMIN; 2007 } 2008 limit = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->hi_lim_reg); 2009 if (limit != 0x00 && limit != 0xff) { 2010 limit *= nom; 2011 limit /= 0xc0; 2012 lims->sel_critmax = limit; 2013 *props |= PROP_CRITMAX; 2014 } 2015 } 2016 2017 static void 2018 dbcool_get_fan_limits(struct dbcool_softc *sc, int idx, 2019 sysmon_envsys_lim_t *lims, uint32_t *props) 2020 { 2021 struct reg_list *reg = sc->sc_regs[idx]; 2022 int32_t limit; 2023 2024 limit = dbcool_read_rpm(sc, reg->lo_lim_reg); 2025 if (limit) { 2026 lims->sel_critmin = limit; 2027 *props |= PROP_CRITMIN; 2028 } 2029 } 2030 2031 /* 2032 * Update sensor limits in the chip registers 2033 */ 2034 static void 2035 dbcool_set_limits(struct sysmon_envsys *sme, envsys_data_t *edata, 2036 sysmon_envsys_lim_t *limits, uint32_t *props) 2037 { 2038 int index = edata->sensor; 2039 struct dbcool_softc *sc = sme->sme_cookie; 2040 2041 if (limits == NULL) { 2042 limits = &sc->sc_deflims[index]; 2043 props = &sc->sc_defprops[index]; 2044 } 2045 switch (edata->units) { 2046 case ENVSYS_STEMP: 2047 dbcool_set_temp_limits(sc, index, limits, props); 2048 break; 2049 case ENVSYS_SVOLTS_DC: 2050 dbcool_set_volt_limits(sc, index, limits, props); 2051 break; 2052 case ENVSYS_SFANRPM: 2053 dbcool_set_fan_limits(sc, index, limits, props); 2054 2055 /* FALLTHROUGH */ 2056 default: 2057 break; 2058 } 2059 *props &= ~PROP_DRIVER_LIMITS; 2060 } 2061 2062 static void 2063 dbcool_set_temp_limits(struct dbcool_softc *sc, int idx, 2064 sysmon_envsys_lim_t *lims, uint32_t *props) 2065 { 2066 struct reg_list *reg = sc->sc_regs[idx]; 2067 int32_t limit; 2068 2069 if (*props & PROP_CRITMIN) { 2070 limit = lims->sel_critmin - 273150000; 2071 limit /= 1000000; 2072 if (sc->sc_temp_offset) { 2073 limit += sc->sc_temp_offset; 2074 if (limit < 0) 2075 limit = 0; 2076 else if (limit > 255) 2077 limit = 255; 2078 } else { 2079 if (limit < -127) 2080 limit = -127; 2081 else if (limit > 127) 2082 limit = 127; 2083 } 2084 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, 2085 (uint8_t)limit); 2086 } else if (*props & PROP_DRIVER_LIMITS) { 2087 if (sc->sc_temp_offset) 2088 limit = 0x00; 2089 else 2090 limit = 0x80; 2091 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, 2092 (uint8_t)limit); 2093 } 2094 2095 if (*props & PROP_CRITMAX) { 2096 limit = lims->sel_critmax - 273150000; 2097 limit /= 1000000; 2098 if (sc->sc_temp_offset) { 2099 limit += sc->sc_temp_offset; 2100 if (limit < 0) 2101 limit = 0; 2102 else if (limit > 255) 2103 limit = 255; 2104 } else { 2105 if (limit < -127) 2106 limit = -127; 2107 else if (limit > 127) 2108 limit = 127; 2109 } 2110 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg, 2111 (uint8_t)limit); 2112 } else if (*props & PROP_DRIVER_LIMITS) { 2113 if (sc->sc_temp_offset) 2114 limit = 0xff; 2115 else 2116 limit = 0x7f; 2117 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg, 2118 (uint8_t)limit); 2119 } 2120 } 2121 2122 static void 2123 dbcool_set_volt_limits(struct dbcool_softc *sc, int idx, 2124 sysmon_envsys_lim_t *lims, uint32_t *props) 2125 { 2126 struct reg_list *reg = sc->sc_regs[idx]; 2127 int64_t limit; 2128 int nom; 2129 2130 nom = nominal_voltages[sc->sc_dc.dc_chip->table[idx].nom_volt_index]; 2131 if (nom < 0) 2132 nom = dbcool_supply_voltage(sc); 2133 nom *= 1000000; /* scale for microvolts */ 2134 2135 if (*props & PROP_CRITMIN) { 2136 limit = lims->sel_critmin; 2137 limit *= 0xc0; 2138 limit /= nom; 2139 if (limit > 0xff) 2140 limit = 0xff; 2141 else if (limit < 0) 2142 limit = 0; 2143 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, limit); 2144 } else if (*props & PROP_DRIVER_LIMITS) 2145 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, 0); 2146 2147 if (*props & PROP_CRITMAX) { 2148 limit = lims->sel_critmax; 2149 limit *= 0xc0; 2150 limit /= nom; 2151 if (limit > 0xff) 2152 limit = 0xff; 2153 else if (limit < 0) 2154 limit = 0; 2155 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg, limit); 2156 } else if (*props & PROP_DRIVER_LIMITS) 2157 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg, 0xff); 2158 } 2159 2160 static void 2161 dbcool_set_fan_limits(struct dbcool_softc *sc, int idx, 2162 sysmon_envsys_lim_t *lims, uint32_t *props) 2163 { 2164 struct reg_list *reg = sc->sc_regs[idx]; 2165 int32_t limit, dividend; 2166 2167 if (*props & PROP_CRITMIN) { 2168 limit = lims->sel_critmin; 2169 if (limit == 0) 2170 limit = 0xffff; 2171 else { 2172 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 2173 dividend = 11250 * 60; 2174 else 2175 dividend = 90000 * 60; 2176 limit = limit / dividend; 2177 if (limit > 0xffff) 2178 limit = 0xffff; 2179 } 2180 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, 2181 limit & 0xff); 2182 limit >>= 8; 2183 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg + 1, 2184 limit & 0xff); 2185 } else if (*props & PROP_DRIVER_LIMITS) { 2186 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, 0xff); 2187 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg + 1, 0xff); 2188 } 2189 } 2190 2191 MODULE(MODULE_CLASS_DRIVER, dbcool, "i2cexec,sysmon_envsys"); 2192 2193 #ifdef _MODULE 2194 #include "ioconf.c" 2195 #endif 2196 2197 static int 2198 dbcool_modcmd(modcmd_t cmd, void *opaque) 2199 { 2200 int error = 0; 2201 #ifdef _MODULE 2202 static struct sysctllog *dbcool_sysctl_clog; 2203 #endif 2204 2205 switch (cmd) { 2206 case MODULE_CMD_INIT: 2207 #ifdef _MODULE 2208 error = config_init_component(cfdriver_ioconf_dbcool, 2209 cfattach_ioconf_dbcool, cfdata_ioconf_dbcool); 2210 sysctl_dbcoolsetup(&dbcool_sysctl_clog); 2211 #endif 2212 return error; 2213 case MODULE_CMD_FINI: 2214 #ifdef _MODULE 2215 error = config_fini_component(cfdriver_ioconf_dbcool, 2216 cfattach_ioconf_dbcool, cfdata_ioconf_dbcool); 2217 sysctl_teardown(&dbcool_sysctl_clog); 2218 #endif 2219 return error; 2220 default: 2221 return ENOTTY; 2222 } 2223 } 2224
Indexes created Wed Sep 24 05:09:52 GMT 2025