ds1307.c revision 1.10
1 /* $NetBSD: ds1307.c,v 1.10 2008/04/06 20:25:59 cegger Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: ds1307.c,v 1.10 2008/04/06 20:25:59 cegger Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/kernel.h> 45 #include <sys/fcntl.h> 46 #include <sys/uio.h> 47 #include <sys/conf.h> 48 #include <sys/event.h> 49 50 #include <dev/clock_subr.h> 51 52 #include <dev/i2c/i2cvar.h> 53 #include <dev/i2c/ds1307reg.h> 54 55 struct dsrtc_softc { 56 struct device sc_dev; 57 i2c_tag_t sc_tag; 58 int sc_address; 59 int sc_open; 60 struct todr_chip_handle sc_todr; 61 }; 62 63 static void dsrtc_attach(struct device *, struct device *, void *); 64 static int dsrtc_match(struct device *, struct cfdata *, void *); 65 66 CFATTACH_DECL(dsrtc, sizeof(struct dsrtc_softc), 67 dsrtc_match, dsrtc_attach, NULL, NULL); 68 extern struct cfdriver dsrtc_cd; 69 70 dev_type_open(dsrtc_open); 71 dev_type_close(dsrtc_close); 72 dev_type_read(dsrtc_read); 73 dev_type_write(dsrtc_write); 74 75 const struct cdevsw dsrtc_cdevsw = { 76 dsrtc_open, dsrtc_close, dsrtc_read, dsrtc_write, noioctl, 77 nostop, notty, nopoll, nommap, nokqfilter, D_OTHER 78 }; 79 80 static int dsrtc_clock_read(struct dsrtc_softc *, struct clock_ymdhms *); 81 static int dsrtc_clock_write(struct dsrtc_softc *, struct clock_ymdhms *); 82 static int dsrtc_gettime(struct todr_chip_handle *, struct clock_ymdhms *); 83 static int dsrtc_settime(struct todr_chip_handle *, struct clock_ymdhms *); 84 85 static int 86 dsrtc_match(struct device *parent, struct cfdata *cf, void *arg) 87 { 88 struct i2c_attach_args *ia = arg; 89 90 if (ia->ia_addr == DS1307_ADDR) 91 return (1); 92 93 return (0); 94 } 95 96 static void 97 dsrtc_attach(struct device *parent, struct device *self, void *arg) 98 { 99 struct dsrtc_softc *sc = device_private(self); 100 struct i2c_attach_args *ia = arg; 101 102 aprint_naive(": Real-time Clock/NVRAM\n"); 103 aprint_normal(": DS1307 Real-time Clock/NVRAM\n"); 104 105 sc->sc_tag = ia->ia_tag; 106 sc->sc_address = ia->ia_addr; 107 sc->sc_open = 0; 108 sc->sc_todr.cookie = sc; 109 sc->sc_todr.todr_gettime = NULL; 110 sc->sc_todr.todr_settime = NULL; 111 sc->sc_todr.todr_gettime_ymdhms = dsrtc_gettime; 112 sc->sc_todr.todr_settime_ymdhms = dsrtc_settime; 113 sc->sc_todr.todr_setwen = NULL; 114 115 todr_attach(&sc->sc_todr); 116 } 117 118 /*ARGSUSED*/ 119 int 120 dsrtc_open(dev_t dev, int flag, int fmt, struct lwp *l) 121 { 122 struct dsrtc_softc *sc; 123 124 if ((sc = device_lookup(&dsrtc_cd, minor(dev))) == NULL) 125 return (ENXIO); 126 127 /* XXX: Locking */ 128 129 if (sc->sc_open) 130 return (EBUSY); 131 132 sc->sc_open = 1; 133 return (0); 134 } 135 136 /*ARGSUSED*/ 137 int 138 dsrtc_close(dev_t dev, int flag, int fmt, struct lwp *l) 139 { 140 struct dsrtc_softc *sc; 141 142 if ((sc = device_lookup(&dsrtc_cd, minor(dev))) == NULL) 143 return (ENXIO); 144 145 sc->sc_open = 0; 146 return (0); 147 } 148 149 /*ARGSUSED*/ 150 int 151 dsrtc_read(dev_t dev, struct uio *uio, int flags) 152 { 153 struct dsrtc_softc *sc; 154 u_int8_t ch, cmdbuf[1]; 155 int a, error; 156 157 if ((sc = device_lookup(&dsrtc_cd, minor(dev))) == NULL) 158 return (ENXIO); 159 160 if (uio->uio_offset >= DS1307_NVRAM_SIZE) 161 return (EINVAL); 162 163 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 164 return (error); 165 166 while (uio->uio_resid && uio->uio_offset < DS1307_NVRAM_SIZE) { 167 a = (int)uio->uio_offset; 168 cmdbuf[0] = a + DS1307_NVRAM_START; 169 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 170 sc->sc_address, cmdbuf, 1, 171 &ch, 1, 0)) != 0) { 172 iic_release_bus(sc->sc_tag, 0); 173 aprint_error_dev(&sc->sc_dev, "dsrtc_read: read failed at 0x%x\n", a); 174 return (error); 175 } 176 if ((error = uiomove(&ch, 1, uio)) != 0) { 177 iic_release_bus(sc->sc_tag, 0); 178 return (error); 179 } 180 } 181 182 iic_release_bus(sc->sc_tag, 0); 183 184 return (0); 185 } 186 187 /*ARGSUSED*/ 188 int 189 dsrtc_write(dev_t dev, struct uio *uio, int flags) 190 { 191 struct dsrtc_softc *sc; 192 u_int8_t cmdbuf[2]; 193 int a, error; 194 195 if ((sc = device_lookup(&dsrtc_cd, minor(dev))) == NULL) 196 return (ENXIO); 197 198 if (uio->uio_offset >= DS1307_NVRAM_SIZE) 199 return (EINVAL); 200 201 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 202 return (error); 203 204 while (uio->uio_resid && uio->uio_offset < DS1307_NVRAM_SIZE) { 205 a = (int)uio->uio_offset; 206 cmdbuf[0] = a + DS1307_NVRAM_START; 207 if ((error = uiomove(&cmdbuf[1], 1, uio)) != 0) 208 break; 209 210 if ((error = iic_exec(sc->sc_tag, 211 uio->uio_resid ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 212 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 213 aprint_error_dev(&sc->sc_dev, "dsrtc_write: write failed at 0x%x\n", a); 214 break; 215 } 216 } 217 218 iic_release_bus(sc->sc_tag, 0); 219 220 return (error); 221 } 222 223 static int 224 dsrtc_gettime(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 225 { 226 struct dsrtc_softc *sc = ch->cookie; 227 struct clock_ymdhms check; 228 int retries; 229 230 memset(dt, 0, sizeof(*dt)); 231 memset(&check, 0, sizeof(check)); 232 233 /* 234 * Since we don't support Burst Read, we have to read the clock twice 235 * until we get two consecutive identical results. 236 */ 237 retries = 5; 238 do { 239 dsrtc_clock_read(sc, dt); 240 dsrtc_clock_read(sc, &check); 241 } while (memcmp(dt, &check, sizeof(check)) != 0 && --retries); 242 243 return (0); 244 } 245 246 static int 247 dsrtc_settime(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 248 { 249 struct dsrtc_softc *sc = ch->cookie; 250 251 if (dsrtc_clock_write(sc, dt) == 0) 252 return (-1); 253 254 return (0); 255 } 256 257 static int 258 dsrtc_clock_read(struct dsrtc_softc *sc, struct clock_ymdhms *dt) 259 { 260 u_int8_t bcd[DS1307_NRTC_REGS], cmdbuf[1]; 261 int i; 262 263 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 264 aprint_error_dev(&sc->sc_dev, "dsrtc_clock_read: failed to acquire I2C bus\n"); 265 return (0); 266 } 267 268 /* Read each RTC register in order. */ 269 for (i = DS1307_SECONDS; i < DS1307_NRTC_REGS; i++) { 270 cmdbuf[0] = i; 271 272 if (iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 273 sc->sc_address, cmdbuf, 1, 274 &bcd[i], 1, I2C_F_POLL)) { 275 iic_release_bus(sc->sc_tag, I2C_F_POLL); 276 aprint_error_dev(&sc->sc_dev, "dsrtc_clock_read: failed to read rtc " 277 "at 0x%x\n", i); 278 return (0); 279 } 280 } 281 282 /* Done with I2C */ 283 iic_release_bus(sc->sc_tag, I2C_F_POLL); 284 285 /* 286 * Convert the DS1307's register values into something useable 287 */ 288 dt->dt_sec = FROMBCD(bcd[DS1307_SECONDS] & DS1307_SECONDS_MASK); 289 dt->dt_min = FROMBCD(bcd[DS1307_MINUTES] & DS1307_MINUTES_MASK); 290 291 if ((bcd[DS1307_HOURS] & DS1307_HOURS_24HRS) == 0) { 292 dt->dt_hour = FROMBCD(bcd[DS1307_HOURS] & 293 DS1307_HOURS_12MASK); 294 if (bcd[DS1307_HOURS] & DS1307_HOURS_12HRS_PM) 295 dt->dt_hour += 12; 296 } else { 297 dt->dt_hour = FROMBCD(bcd[DS1307_HOURS] & 298 DS1307_HOURS_24MASK); 299 } 300 301 dt->dt_day = FROMBCD(bcd[DS1307_DATE] & DS1307_DATE_MASK); 302 dt->dt_mon = FROMBCD(bcd[DS1307_MONTH] & DS1307_MONTH_MASK); 303 304 /* XXX: Should be an MD way to specify EPOCH used by BIOS/Firmware */ 305 dt->dt_year = FROMBCD(bcd[DS1307_YEAR]) + POSIX_BASE_YEAR; 306 307 return (1); 308 } 309 310 static int 311 dsrtc_clock_write(struct dsrtc_softc *sc, struct clock_ymdhms *dt) 312 { 313 uint8_t bcd[DS1307_NRTC_REGS], cmdbuf[2]; 314 int i; 315 316 /* 317 * Convert our time representation into something the DS1307 318 * can understand. 319 */ 320 bcd[DS1307_SECONDS] = TOBCD(dt->dt_sec); 321 bcd[DS1307_MINUTES] = TOBCD(dt->dt_min); 322 bcd[DS1307_HOURS] = TOBCD(dt->dt_hour) | DS1307_HOURS_24HRS; 323 bcd[DS1307_DATE] = TOBCD(dt->dt_day); 324 bcd[DS1307_DAY] = TOBCD(dt->dt_wday); 325 bcd[DS1307_MONTH] = TOBCD(dt->dt_mon); 326 bcd[DS1307_YEAR] = TOBCD((dt->dt_year - POSIX_BASE_YEAR) % 100); 327 328 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 329 aprint_error_dev(&sc->sc_dev, "dsrtc_clock_write: failed to acquire I2C bus\n"); 330 return (0); 331 } 332 333 /* Stop the clock */ 334 cmdbuf[0] = DS1307_SECONDS; 335 cmdbuf[1] = DS1307_SECONDS_CH; 336 337 if (iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 338 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) { 339 iic_release_bus(sc->sc_tag, I2C_F_POLL); 340 aprint_error_dev(&sc->sc_dev, "dsrtc_clock_write: failed to Hold Clock\n"); 341 return (0); 342 } 343 344 /* 345 * Write registers in reverse order. The last write (to the Seconds 346 * register) will undo the Clock Hold, above. 347 */ 348 for (i = DS1307_NRTC_REGS - 1; i >= 0; i--) { 349 cmdbuf[0] = i; 350 if (iic_exec(sc->sc_tag, 351 i ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 352 sc->sc_address, cmdbuf, 1, &bcd[i], 1, 353 I2C_F_POLL)) { 354 iic_release_bus(sc->sc_tag, I2C_F_POLL); 355 aprint_error_dev(&sc->sc_dev, "dsrtc_clock_write: failed to write rtc " 356 " at 0x%x\n", i); 357 /* XXX: Clock Hold is likely still asserted! */ 358 return (0); 359 } 360 } 361 362 iic_release_bus(sc->sc_tag, I2C_F_POLL); 363 364 return (1); 365 } 366
Indexes created Thu Oct 02 14:10:14 GMT 2025