ds1307.c revision 1.11
1 /* $NetBSD: ds1307.c,v 1.11 2008/05/04 15:26:29 xtraeme Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: ds1307.c,v 1.11 2008/05/04 15:26:29 xtraeme Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/kernel.h> 45 #include <sys/fcntl.h> 46 #include <sys/uio.h> 47 #include <sys/conf.h> 48 #include <sys/event.h> 49 50 #include <dev/clock_subr.h> 51 52 #include <dev/i2c/i2cvar.h> 53 #include <dev/i2c/ds1307reg.h> 54 55 struct dsrtc_softc { 56 device_t sc_dev; 57 i2c_tag_t sc_tag; 58 int sc_address; 59 int sc_open; 60 struct todr_chip_handle sc_todr; 61 }; 62 63 static void dsrtc_attach(device_t, device_t, void *); 64 static int dsrtc_match(device_t, cfdata_t, void *); 65 66 CFATTACH_DECL_NEW(dsrtc, sizeof(struct dsrtc_softc), 67 dsrtc_match, dsrtc_attach, NULL, NULL); 68 extern struct cfdriver dsrtc_cd; 69 70 dev_type_open(dsrtc_open); 71 dev_type_close(dsrtc_close); 72 dev_type_read(dsrtc_read); 73 dev_type_write(dsrtc_write); 74 75 const struct cdevsw dsrtc_cdevsw = { 76 dsrtc_open, dsrtc_close, dsrtc_read, dsrtc_write, noioctl, 77 nostop, notty, nopoll, nommap, nokqfilter, D_OTHER 78 }; 79 80 static int dsrtc_clock_read(struct dsrtc_softc *, struct clock_ymdhms *); 81 static int dsrtc_clock_write(struct dsrtc_softc *, struct clock_ymdhms *); 82 static int dsrtc_gettime(struct todr_chip_handle *, struct clock_ymdhms *); 83 static int dsrtc_settime(struct todr_chip_handle *, struct clock_ymdhms *); 84 85 static int 86 dsrtc_match(device_t parent, cfdata_t cf, void *arg) 87 { 88 struct i2c_attach_args *ia = arg; 89 90 if (ia->ia_addr == DS1307_ADDR) 91 return (1); 92 93 return (0); 94 } 95 96 static void 97 dsrtc_attach(device_t parent, device_t self, void *arg) 98 { 99 struct dsrtc_softc *sc = device_private(self); 100 struct i2c_attach_args *ia = arg; 101 102 aprint_naive(": Real-time Clock/NVRAM\n"); 103 aprint_normal(": DS1307 Real-time Clock/NVRAM\n"); 104 105 sc->sc_tag = ia->ia_tag; 106 sc->sc_address = ia->ia_addr; 107 sc->sc_dev = self; 108 sc->sc_open = 0; 109 sc->sc_todr.cookie = sc; 110 sc->sc_todr.todr_gettime = NULL; 111 sc->sc_todr.todr_settime = NULL; 112 sc->sc_todr.todr_gettime_ymdhms = dsrtc_gettime; 113 sc->sc_todr.todr_settime_ymdhms = dsrtc_settime; 114 sc->sc_todr.todr_setwen = NULL; 115 116 todr_attach(&sc->sc_todr); 117 } 118 119 /*ARGSUSED*/ 120 int 121 dsrtc_open(dev_t dev, int flag, int fmt, struct lwp *l) 122 { 123 struct dsrtc_softc *sc; 124 125 if ((sc = device_lookup(&dsrtc_cd, minor(dev))) == NULL) 126 return (ENXIO); 127 128 /* XXX: Locking */ 129 130 if (sc->sc_open) 131 return (EBUSY); 132 133 sc->sc_open = 1; 134 return (0); 135 } 136 137 /*ARGSUSED*/ 138 int 139 dsrtc_close(dev_t dev, int flag, int fmt, struct lwp *l) 140 { 141 struct dsrtc_softc *sc; 142 143 if ((sc = device_lookup(&dsrtc_cd, minor(dev))) == NULL) 144 return (ENXIO); 145 146 sc->sc_open = 0; 147 return (0); 148 } 149 150 /*ARGSUSED*/ 151 int 152 dsrtc_read(dev_t dev, struct uio *uio, int flags) 153 { 154 struct dsrtc_softc *sc; 155 u_int8_t ch, cmdbuf[1]; 156 int a, error; 157 158 if ((sc = device_lookup(&dsrtc_cd, minor(dev))) == NULL) 159 return (ENXIO); 160 161 if (uio->uio_offset >= DS1307_NVRAM_SIZE) 162 return (EINVAL); 163 164 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 165 return (error); 166 167 while (uio->uio_resid && uio->uio_offset < DS1307_NVRAM_SIZE) { 168 a = (int)uio->uio_offset; 169 cmdbuf[0] = a + DS1307_NVRAM_START; 170 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 171 sc->sc_address, cmdbuf, 1, 172 &ch, 1, 0)) != 0) { 173 iic_release_bus(sc->sc_tag, 0); 174 aprint_error_dev(sc->sc_dev, 175 "dsrtc_read: read failed at 0x%x\n", a); 176 return (error); 177 } 178 if ((error = uiomove(&ch, 1, uio)) != 0) { 179 iic_release_bus(sc->sc_tag, 0); 180 return (error); 181 } 182 } 183 184 iic_release_bus(sc->sc_tag, 0); 185 186 return (0); 187 } 188 189 /*ARGSUSED*/ 190 int 191 dsrtc_write(dev_t dev, struct uio *uio, int flags) 192 { 193 struct dsrtc_softc *sc; 194 u_int8_t cmdbuf[2]; 195 int a, error; 196 197 if ((sc = device_lookup(&dsrtc_cd, minor(dev))) == NULL) 198 return (ENXIO); 199 200 if (uio->uio_offset >= DS1307_NVRAM_SIZE) 201 return (EINVAL); 202 203 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 204 return (error); 205 206 while (uio->uio_resid && uio->uio_offset < DS1307_NVRAM_SIZE) { 207 a = (int)uio->uio_offset; 208 cmdbuf[0] = a + DS1307_NVRAM_START; 209 if ((error = uiomove(&cmdbuf[1], 1, uio)) != 0) 210 break; 211 212 if ((error = iic_exec(sc->sc_tag, 213 uio->uio_resid ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 214 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 215 aprint_error_dev(sc->sc_dev, 216 "dsrtc_write: write failed at 0x%x\n", a); 217 break; 218 } 219 } 220 221 iic_release_bus(sc->sc_tag, 0); 222 223 return (error); 224 } 225 226 static int 227 dsrtc_gettime(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 228 { 229 struct dsrtc_softc *sc = ch->cookie; 230 struct clock_ymdhms check; 231 int retries; 232 233 memset(dt, 0, sizeof(*dt)); 234 memset(&check, 0, sizeof(check)); 235 236 /* 237 * Since we don't support Burst Read, we have to read the clock twice 238 * until we get two consecutive identical results. 239 */ 240 retries = 5; 241 do { 242 dsrtc_clock_read(sc, dt); 243 dsrtc_clock_read(sc, &check); 244 } while (memcmp(dt, &check, sizeof(check)) != 0 && --retries); 245 246 return (0); 247 } 248 249 static int 250 dsrtc_settime(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 251 { 252 struct dsrtc_softc *sc = ch->cookie; 253 254 if (dsrtc_clock_write(sc, dt) == 0) 255 return (-1); 256 257 return (0); 258 } 259 260 static int 261 dsrtc_clock_read(struct dsrtc_softc *sc, struct clock_ymdhms *dt) 262 { 263 u_int8_t bcd[DS1307_NRTC_REGS], cmdbuf[1]; 264 int i; 265 266 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 267 aprint_error_dev(sc->sc_dev, 268 "dsrtc_clock_read: failed to acquire I2C bus\n"); 269 return (0); 270 } 271 272 /* Read each RTC register in order. */ 273 for (i = DS1307_SECONDS; i < DS1307_NRTC_REGS; i++) { 274 cmdbuf[0] = i; 275 276 if (iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 277 sc->sc_address, cmdbuf, 1, 278 &bcd[i], 1, I2C_F_POLL)) { 279 iic_release_bus(sc->sc_tag, I2C_F_POLL); 280 aprint_error_dev(sc->sc_dev, 281 "dsrtc_clock_read: failed to read rtc " 282 "at 0x%x\n", i); 283 return (0); 284 } 285 } 286 287 /* Done with I2C */ 288 iic_release_bus(sc->sc_tag, I2C_F_POLL); 289 290 /* 291 * Convert the DS1307's register values into something useable 292 */ 293 dt->dt_sec = FROMBCD(bcd[DS1307_SECONDS] & DS1307_SECONDS_MASK); 294 dt->dt_min = FROMBCD(bcd[DS1307_MINUTES] & DS1307_MINUTES_MASK); 295 296 if ((bcd[DS1307_HOURS] & DS1307_HOURS_24HRS) == 0) { 297 dt->dt_hour = FROMBCD(bcd[DS1307_HOURS] & 298 DS1307_HOURS_12MASK); 299 if (bcd[DS1307_HOURS] & DS1307_HOURS_12HRS_PM) 300 dt->dt_hour += 12; 301 } else { 302 dt->dt_hour = FROMBCD(bcd[DS1307_HOURS] & 303 DS1307_HOURS_24MASK); 304 } 305 306 dt->dt_day = FROMBCD(bcd[DS1307_DATE] & DS1307_DATE_MASK); 307 dt->dt_mon = FROMBCD(bcd[DS1307_MONTH] & DS1307_MONTH_MASK); 308 309 /* XXX: Should be an MD way to specify EPOCH used by BIOS/Firmware */ 310 dt->dt_year = FROMBCD(bcd[DS1307_YEAR]) + POSIX_BASE_YEAR; 311 312 return (1); 313 } 314 315 static int 316 dsrtc_clock_write(struct dsrtc_softc *sc, struct clock_ymdhms *dt) 317 { 318 uint8_t bcd[DS1307_NRTC_REGS], cmdbuf[2]; 319 int i; 320 321 /* 322 * Convert our time representation into something the DS1307 323 * can understand. 324 */ 325 bcd[DS1307_SECONDS] = TOBCD(dt->dt_sec); 326 bcd[DS1307_MINUTES] = TOBCD(dt->dt_min); 327 bcd[DS1307_HOURS] = TOBCD(dt->dt_hour) | DS1307_HOURS_24HRS; 328 bcd[DS1307_DATE] = TOBCD(dt->dt_day); 329 bcd[DS1307_DAY] = TOBCD(dt->dt_wday); 330 bcd[DS1307_MONTH] = TOBCD(dt->dt_mon); 331 bcd[DS1307_YEAR] = TOBCD((dt->dt_year - POSIX_BASE_YEAR) % 100); 332 333 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 334 aprint_error_dev(sc->sc_dev, 335 "dsrtc_clock_write: failed to acquire I2C bus\n"); 336 return (0); 337 } 338 339 /* Stop the clock */ 340 cmdbuf[0] = DS1307_SECONDS; 341 cmdbuf[1] = DS1307_SECONDS_CH; 342 343 if (iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 344 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) { 345 iic_release_bus(sc->sc_tag, I2C_F_POLL); 346 aprint_error_dev(sc->sc_dev, 347 "dsrtc_clock_write: failed to Hold Clock\n"); 348 return (0); 349 } 350 351 /* 352 * Write registers in reverse order. The last write (to the Seconds 353 * register) will undo the Clock Hold, above. 354 */ 355 for (i = DS1307_NRTC_REGS - 1; i >= 0; i--) { 356 cmdbuf[0] = i; 357 if (iic_exec(sc->sc_tag, 358 i ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 359 sc->sc_address, cmdbuf, 1, &bcd[i], 1, 360 I2C_F_POLL)) { 361 iic_release_bus(sc->sc_tag, I2C_F_POLL); 362 aprint_error_dev(sc->sc_dev, 363 "dsrtc_clock_write: failed to write rtc " 364 " at 0x%x\n", i); 365 /* XXX: Clock Hold is likely still asserted! */ 366 return (0); 367 } 368 } 369 370 iic_release_bus(sc->sc_tag, I2C_F_POLL); 371 372 return (1); 373 } 374
Indexes created Thu Oct 02 14:10:14 GMT 2025